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=
K(0,
j
)
0
(3)
I
c
0
= I
x
0
I
0
I
x
0
=
g
x
2
g
x
2
g
j
2
I
0
=
g
j
2
g
x
2
g
j
2
where x y g ,g are pre-calculated and stored in a table and extracted by linear interpolation method. The torque
commands during a commutation interval are illustrated in Fig. 6. In this method (TDF III), the saturation and
mutual coupling between the phases are neglected. In reference [1], Krishnan has also proposed the method TDF IV,
which takes the mutual coupling into consideration and the TDF V, which includes both saturation and mutual
coupling. The practical implementation of methods TDF IV and TDF V is however very difficult, due to the fact
that the mutual coupling between the phases is not easily determined. Therefore, we prefer to consider only the
method TDF III, and try to improve its drawback (Section III).
D. Simulation Results
The performance of the SRM drive system was evaluated by using Torque Distribution Function, TDF-III. The
torquecommand was set to 100 Nm and the motors speed was set to 1000 rpm and 3000 rpm. In commutation
intervals, the torque command was divided into two parts so that two phases could reduce torque ripple. Simulation
results illustrate that at 1000 rpm, the torque ripple is very small. However, at a speed of 3000 rpm, torque ripple is
very large.
III. PROPOSED TORQUE DISTRIBUTION FUNCTION
Because of the non-idealized current controller, the actual currents need a specified time to track their commands.
As a result, actual phase torques cannot track commands that produce torque ripple, especially in high speed
applications; in other words, the higher the speed of the motor, the larger the torque ripple that will be produced. For
this reason, a new TDF is proposed to reduce torque ripple, especially in SRM drive high-speed applications.
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
5
Fig. 6. Torque commands in commutation interval.
Fig.7. Phase current, phase torques and total torque at 1000rpm (upper) and 3000 rpm (lower) and torque
reference of 100Nm (red line real torque and green line command torque).
In the proposed Torque Distribution Function [14], the torque command is actively compensated for in each
phase,
resulting in a flat total command torque. The following equations describe this method. In the table, T
a*,
T
b*
and
T
c*
are the phase torque commands, and T
e
is the torque command.
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
6
TABLE I. EQUATIONS OF PROPOSED TDF
angle 0-3
I
u
x
g
u
2
g
u
2
+g
c
2
I
c
I
b
x
0
I
c
x
g
c
2
g
u
2
+g
c
2
I
c
+ (I
u
x
1
2
g
c
i
c
2
)
angle 3
I
u
x
g
u
2
g
u
2
+g
b
2
I
c
+ (I
b
x
1
2
g
b
i
b
2
)
I
b
x
g
b
2
g
u
2
+g
b
2
I
c
I
c
x
0
angle
I
u
x
g
b
2
g
b
2
+g
c
2
I
c
+ (I
c
x
1
2
g
c
i
c
2
)
I
b
x
0
I
c
x
g
c
2
g
b
2
+g
c
2
I
c
As illustrated in the simulation results, the torque command is not flat (green curve). However, the actual torque
(red curve) is quite flat, thereby significantly reducing torque ripple.
IV. REAL-TIME SIMULATION OF SRM DRIVES
A. RT-LAB real-time simulation platform
RT-LAB, from Opal-RT Technologies, is a real-time simulation platform that enables HIL simulation of
controllers, electric plants or both, through automatic code generation methods. The entire process occurs
without the need for handwritten C code, enabling very rapid deployment of prototyped controllers or HIL-
simulated plants. The process is notably very efficient when applied to I/O code because RT-LAB provides a set
of Simulink blocks that automatically configure common I/O functions, like analog inputs/outputs and time-
stamping capable digital I/Os, with a 10 nanosecond resolution. Special interpolating models use this timing
information to greatly increase simulation accuracy [10]. RT-LAB simulators can also be equipped with a user
programmable FPGA card. The FPGA card can be programmed with the Xilinx System Generator blockset for
Simulink enabling implementation of complex sensor models like resolvers, Resolver-To-Digital and FM
resolvers or even complex motor drives [11], [12].
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
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Fig. 8. Phase current, phase torques and total torque at speed of 3000 rpm and load torque of 100 Nm (red line
real torque and green line command torque).
TABLE II. RT-LAB SIMULATOR CHARACTERISTICS
Hardware
PC with dual Quad-Core Intel
processor (2.3 GHz)
Real-time OS QNX or RedHawk Linux
RT-LAB version 8.2.5
Digital I/O 16 Din-16 Dout (Time Stamped)
Analog I/O 16 Analog Inputs and 16 Outputs
B. Test case: constant turn-on and turn-off angles and 10A dead band.
The SRM drive discussed in this paper is simulated in real-time on the RT-LAB real-time simulation platform,
using 2 cores of a dual quad-core PC. Table II summarizes the characteristics of the RT-LAB system used in this
paper. A very basic type of SRM control with fixed turn on and turn-off angles will be used as an example. The
task separation for the experiment is shown in Fig. 9. A sample time of 13 s was reached with an I/O interface
consisting of 6 digital inputs for the IGBT gates, 3 digital outputs (used for quadrature encoder emulation) and 5
Analog Outputs for motor currents and resolver signals. The final simulation time of 15 s was chosen to leave
margin available for a more complex model. In this test, however, the sensors are idealized, and only the
numerical value of the angle is transmitted between cores. The most important difference is the current ripple
amplitude during current regulation. The 15 s simulation run exhibits higher ripple (as much as 2 times the
nominal 10A gap) because of the increased delay in the current loop. In an SRM, this component of the torque
ripple is a magnitude lower than the overall torque ripple and may therefore minimally affect the overall testing
purpose of the real-time simulator. As previously mentioned, the SRM drive was simulated on an RT-LAB
system with Hardware- In-the-Loop capability. This section shows the model signals obtained during real-time
simulation. A 100 N.m torque is applied so that the SRM runs in current regulation mode in steady state.
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
8
Fig. 9. Real-time simulation of an SRM drive: task separation.
Fig. 10. Simulation runs at 1 us and 15 us (with zoom in the lower).
Fig. 11. shows the currents for the 3 phases of the motor, with an analog output scaling of 1/50 V/A. The lower
oscilloscope grab of Fig. 11 shows the current of phase A, along with the corresponding IGBT gate signals. The
correspondence between the IGBT gate level and current slope sign is clearly apparent in this figure.
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
9
Fig. 11. Motor currents: all 3 phases (upper); phase A with gate signals
(lower).
V. REAL-TIME SIMULATION OF AN SRM WITH FPGAS AS COMPUTATIONAL ENGINE.
Real-time simulation of SRM drives on a CPU-based real-time simulator can produce accurate results, but can
also have the undesirable effect of causing current overshoots because of model latency. In this case, this latency
has prevented the testing of the proposed TDF method in real-time. To remedy this problem, an FPGA
implementation is desirable because it offers a very low calculation and I/O latency. FPGA implementations of a
standard Park-model PMSM drive [6] and a Finite- Element Analysis (FEA) based PMSM drive [7] have been
demonstrated, and have a total latency just above 1 microsecond, including I/Os. The SRM model has a
calculation structure very similar to an FEA-based PMSM, as follows: flux integration, followed by the
multiplication by inductance inverse to compute machine currents. However, in the case of the SRM, the flux
current characteristic is two-dimensional, while in [11] a 3-D table was necessary to store inductance values as a
function of current amplitude and sector, as well as rotor position. Consequently, the SRM implementation on an
FPGA should be easier. Simulation results similar to Fig. 11. (1 microsecond curves), but with minimal
overshoot, are expected. The RT-LAB system comes with a user programmable FPGA card based on the Virtex
II-Pro (11K cells, 44 multipliers, PCI interface). An improved FPGA card based on the SPARTAN-3 chip from
Xilinx has recently become available (77K cells 104 multipliers, PCIe interface). The support for the
SPARTAN-3 chip provides an undeniable boost to the capability of the system. Logic cells, the standard
measure of FPGA resource availability, are increased 7 fold with the SPARTAN-3. A more subtle advantage, the
2.5 times increase in hardware multiplier, greatly increases FPGA drive design possibilities, since multiplication
operations are very common in drive models. The increased I/O number also enables the possible connection of
several drives implemented on the chip. Finally, RT-LAB can also be interfaced with a Virtex-5 board with 288
multiplier units and PCIe interface.
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
10
Fig. 12. Design flow in RT-LAB
The interface to the CPU-side of the simulator is also very important. A typical RT-LAB application (automotive
applications, for example) will have several motor drives interacting electrically, as well as through a mechanical
system. The latter, for example, is typically complex and relatively slow, and therefore best implemented using
Simulink on a regular CPU, using a standard code generation technique. Consequently, a fast data exchange
mechanism is required to conduct mixed type simulation (CPU-FPGA). The PCI Express (PCIe) support
available on the SPARTAN-3 design greatly increases the data exchange rate between CPU and FPGA. Finally,
the I/O access time is minimal with FPGA implementations because the FPGA card is hardwired with the Digital
I/Os and Analog converters. The most important objective is to make the whole design process easy and
straightforward. With RT-LAB, this process follows the Model-Based Design paradigm in which the user
develops specifications, and conducts model design and test simply by interacting with the high level model,
usually designed in Simulink. When FPGA design is involved, the same process flow, described in Fig. 12, is
maintained except that Xilinx ISE FPGA code generation tools are involved in the process.
Fig. 13. Experimental setup.
VI. CONCLUSION
The paper has presented modeling, simulation and control SRM using Torque Distribution Function, developed
by R.Krishnan, to reduce torque ripple. In this paper, the authors have also proposed a novel Torque Distribution
Function to reduce torque ripple at high speed. The simulation results have confirmed excellent response of the
torque by novel TDF. This paper has also demonstrated the feasibility of real-time simulation of a SRM drive,
based on the RT-LAB simulator. The real time simulation was conducted on 2 cores of an 8-core standard PC at
a sample time of 13 s, including digital and analog I/O access time. Acceptable results have been produced,
despite some overshoot when the current converter hysteresis gap is not too small. However, for a very
demanding control algorithm, such as Torque Distribution Function method, the
American Journal of Information Sciences
ISSN (Paper) 2568-5171 ISSN (Online) 2568-5546
Vol.6 No.2 2013 www.congresspress.com
11
standard CPU-based approach presents input-output latency issues at the I/O level that will prevent an accurate
simulation from being performed. In this case, an implementation of the SRM drive on the FPGA should solve
the problem. This FPGA-implementation was not presented in the paper. It is believed that the FPGA
implementation should not be problematic because a machine of similar complexity, a FPGA-based PMSM with
FEA-based inductance profile, has already been designed using RT-LAB.
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