Cheer Tek

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CT212
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE CTK CONFIDENTIAL, NO DISCLOSURE
CT212
DVB Decoder Chip
www.DataSheet4U.com Specification
Rev. 0.9
Page 1
The above information is the exclusive intellectual property of Cheertek Inc. and shall not be disclosed, distributed or reproduced without permission from Cheertek Inc.
Copyright (C) 2003 Cheertek Inc. All Rights Reserved.
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CT212
Table of Contents
1. 2. 3. 4. 5. 6. 7. 8.
GENERAL DESCRIPTION...................................................................................................... 3 FEATURES................................................................................................................................. 4 PIN CONFIGURATION ........................................................................................................... 7 PIN DESCRIPTION .................................................................................................................. 8 SYSTEM DIAGRAM .............................................................................................................. 18 BLOCK DIAGRAM ................................................................................................................ 19 FUNCTIONAL DESCRIPTION ............................. ERROR! BOOKMARK NOT DEFINED. PACKAGE SPECIFICATION................................................................................................ 20
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CT212
1. General Description
The CT212 is a high integration single-chip DIGITAL TV STB backend processor. It integrates MPEG A/V decoder, MPEG transport de-multiplex processor, micro-controller, and TV encoder onto a chip, facilitating a cost-effective solution for DIGITAL TV STB receivers.
The CT212 performs real-time PID filtering, decompression of MPEG1, MPEG2 video, MPEG and LPCM audio. Also, it supports EPG and VBI functions such as teletext, WSS/CGMS and closed caption.
In A/V presentation, the CT212 supports stereo and multi-channel audio output with a variety of sound effect. It also supports digital audio output through S/PDIF port. The embedded TV encoder supports CVBS, S-video, component YCbCr, RGB and progressive YPbPr formats.
The micro-controller is fully compliant to standard Turbo 8032 core. This provides easy development of system firmware and user interface.
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CT212
2. Features
System operation ISO/IEC 13818 transport stream decoding EPG for digital TV and set top box applications Teletext with VBI (Vertical Blanking Insertion) or OSD Transport de-multiplexing and NIM interface 32 PID filters Accept both 188 and 204 byte packet formats CRC-32 accelerator PCR clock recovery and PWM generator Parallel/serial interface with NIM (Network Interface Module) Maximal input clock rate: 13MHz for parallel and 104MHz for serial 2-wire serial interface with NIM control
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Audio decoding and processing Decode MPEG2 and MPEG1 Audio at sampling frequency of 16K, 22.05K, 24K, 32K, 44.1K, and 48KHz Decode Linear PCM at sampling frequency of 44.1 KHz, 48KHz and 96 KHz Output serial PCM audio data with 16, 18, 20 and 24 bits resolution and sampling rate at 16K, 22.05K, 24K, 32K, 44.1K, 48K and 96 KHz Support 3D surround sound Support key-shift S/PDIF output meet IEC958 spec, supporting compressed AC-3 and stereo digital PCM Digital mute control and volume adjustment
Video decoding and processing Decode MPEG2 Main Profile Main Level and MPEG1 video streams, up to 720 480 at 30 Hz and 720 576 at 25 Hz resolution Support 16:9 and 4:3 TV aspect ratios, by Pan & Scan and Letter Box conversion
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CT212
Support frame rate conversion for different video formats Support flexible horizontal and vertical scaling of x 16 ~ x 1/16 BrightView to brighten the details of dark area in a picture: Normal/Bright/Soft Fade in/out control Support background picture Support 16 color 32x32 cursor Four rectangle strip planes. OSD (On Screen Display) 2 bits, 4 bits and 8 bits per pixel, up to 256 color palettes

One line to full screen OSD Region-based alpha-blending Scroll display capability
Highlight processing Seamlessly link adjacent OSD regions
64 mix-weighting level for blending OSD and video Bitmap OSD

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Support horizontal pixel duplication to enlarge bitmap automatically. Support sub-region redraw to facilitate bitmap display.
Font OSD:

Support 2 bits/pixel encoding font OSD. Support eight kinds of font size for each region Maximum 256 characters in one font table Eight choices of font size to build font table: 4 pixels to 32 pixels in 4 pixels step Support horizontal pixel duplication to enlarge character automatically. Maximum 44 characters display and maximum 8 different font colors for each region Support color-change option to enrich font color.
TV encoder NTSC-M, PAL-B, D, G, H, I, NC, M encoding Support interlace and progressive scan Page 5
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CT212
Programmable Y/C delay relationship Four 10-bit DACs run at 2X pixel rate, provide CVBS/S-video, RGB, YCbCr and progressive scan YPbPr output formats Teletext, WSS/CGMS and closed captioning
Embedded micro-controller 8-bit micro-controller compatible to Turbo 8032 Up to 50MHz operating frequency 256-byte Scratchpad RAM Embedded 32K-byte data memory 64K-byte address space for external Program memory 32K-byte address space for external Data Memory Three 16-bit timer/counters Five 8-bit bi-directional ports Six interrupt channels
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One programmable watch-dog timer Two programmable full duplex serial port
Electrical and physical characteristics Build-in PLL Single 27 MHz clock input crystal with PCR control Support 16M, 32M and 64M SDRAM operating at up to 133MHz 1.8V and 3.3V dual power supply 208 pin PQFP
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CT212
3. Pin Configuration
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CT212
4. Pin Description
4.1 System Signals and Power/Ground
Pin name OSCI OSCO CLKO RESET# EMU Type I O O I I Description Clock input. It can be oscillator or crystal input. Frequency is 27MHz. Output terminal for crystal connection. This signal also emulates as VCLK for digital video pixel clock output Clock output, frequency programmable, see reg. CLKO definition System reset, active LOW Emulation mode select EMU =0, normal operation, enable internal micro-controller, =1, select emulation mode, disable internal micro-controller. General purpose IO bus A bits[7:0], initial in input state/digital pixel data bus bits[7:0] Clock control PWM output for PCR recovery Loop filter, connected to a capacitor Loop filter, connected to a capacitor 1.8V analog power supply Analog ground 3.3V digital power supply for IO driving buffer Digital ground for IO driving buffer 1.8V digital power supply for core Digital ground for core
GPA[7:0]/PD[7:0] PWM VLFM VLFA AVD18 AVSSP VDDP VSSP VDD VSS
I/O O AI AI AP AG DP DG DP DG
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4.2 Micro-controller Interface Signals

Pin name ALE Type I/O Internal uC mode (EMU=0) Address latch enable output. It is used to latch the address low byte expressed on port0. PSEN# I/O Program strobe enable output. It is used to strobe code of the external program memory. LATS: Low byte address conveying type select input. LATS=0, mux with SAD[7:0]; LATS=1, conveyed on SA[7:0] External uC mode (EMU=1) ALE: Address latch enable input.
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CT212
PORT0 [7:0]
I/O
Port0 is an 8-bit bi-directional I/O port. In accesses to external memory, port0 outputs the low byte of the external memory address, time-multiplexed with the data byte being written or read.
SAD[7:0]: low byte address and data bus, bi-directional.
SA[7:0]/GPA[15: 8]
I/O
SA[7:0]: lower address byte for external program and data memories, latched by ALE from Port0 address phase, output. This is the default. Alternately these pins can be used as general purpose IO signals. GPA[15:8]: general purpose IO bus A bits[15:8], bi-directional.
LATS=1, SA[7:0]: low byte address bus, input. LATS=0, SA[7:0] output or GPA[15:8] selected by register
PORT2 [7:0]
I/O
Port2 is an 8-bit bi-directional I/O port with internal pull-up. Port2 also serves as memory address bus.
SA[15:8]: high byte address bus, input.
In accesses to external memory, port2 outputs www.DataSheet4U.com the high byte of the external memory address. PORT1 [7:0] I/O Port1 is an 8-bit bi-directional I/O port with internal pull-up. P1.0 and p1.1 also serve the T2 and T2EX functions, respectively. P1.2 and P1.3 also serve the RXD2 and TXD2, respectively. P1.4: GPB0, general purpose IO bus B bit 0, initial in input state P1.5, P1.6 and P1.7 also serve external interrupt inputs P1.4: INTTS#, output P1.5: CS#, input
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CT212
PORT3 [7:0]
I/O
Port3 is an 8-bit bi-directional I/O port with internal pull-up. Port3 also serve following special functions: P3.0 RXD1 (serial input port) P3.1 TXD1 (serial output port) P3.2 IR input P3.3: GPB1, general purpose IO bus B bit 1, initial in input state P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR# (external data memory write) P3.7 RD# (external data memory read)
P3.3: INTM#, output P3.6: WR#, input P3.7: RD#, input
PORT5 [7:0]
I/O
Port5 is an 8-bit bi-directional I/O port, default in input state.
FWR#
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Flash write enable output
4.2.1 External Micro-controller Mode

Pin name ALE Type I Description Address latch enable. It is used to latch the low byte address of SAD[7:0] as LATS=0. LATS I Low byte address conveying type select, input only. LATS=0, mux with SAD[7:0]; LATS=1, conveyed on SA[7:0]. SAD[7:0] I/O When ALE is active (ALE=1), it is the low byte of the address. And it is time-multiplexed with the data byte being written(WR# active) or read(RD# active).
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CT212
SA[7:0]/GPA[15: 8]
I/O
When LATS=1, SA[7:0] input is specified, representing the low byte address bus, input. When LATS=0, two options: one is SA[7:0] output of the low byte address latched from SAD[7:0] input by ALE; the other is GPA[15:8], general purpose IO bus A bits[15:8], bi-directional; SA[7:0] output is default.
SA[15:8] CS# INTTS# INTM# WR# RD#
I I O O I I
The high byte of the address bus. Chip select input, active low Interrupt request of on-chip transport de-multiplex processor, active low. Interrupt request of on-chip AV decoder, active low. Write enable, active low. Read enable, active low.
4.3 SDRAM Interface Signals

Pin name MA[11:0] Type O
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Description (64M type) SDRAM Address bus output Alternative (2x16M type) MA[11]: no use MA[10:0]: Address bus output
BS[1:0]
SDRAM Bank Select output
BS[0]: BA, Bank address output BS[1]: SCS1#, Chip select output of 2nd SDRAM, active low
MD[15:0]
I/O
SDRAM Data bus keeps as input state except for WRITE operation
MD[15:0]
SDCLK SDCLKI SCS#
O I O
SDRAM Clock Output SDRAM Clock Input SDRAM Chip Select output, active Low
SDCLK SDCLKI SCS0#, Chip select output of 1st SDRAM, active low RAS#
RAS#
Row Address Strobe output, active Low
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CT212
CAS#
Column Address Strobe output, active Low
CAS#
SWE# DQML DQMH
O O O
Write Enable output, active Low Low byte data mask, active High High byte data mask, active High
SWE# DQML DQMH
4.4 Video Interface Signals

Pin name AVO0 Type AO Description Four kinds of analog video output supoorted: CVBS(composite)/S-video(Y/C), YCbCr(component), RGB(component) and YPbPr Progressive scan. Mode 1: CVBS + S-video(Y/C) Mode 2: CVBS+YCbCr
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This pin is: In mode 1: (CVBS) analog composite signal output. 2: (Y) analog luminance signal output. 3: (G) analog Green signal output. 4: (Y) analog progressive luminance signal output. AVO1 AO This pin is: In mode 1: (Y) analog luminance signal output, 2: (Cb) analog chrominance signal output. 3: (B) analog blue signal output. 4: (Pb) analog progressive chrominance signal output. AVO2 AO This pin is: In mode 1: (C) analog chrominance signal output, 2: (Cr) analog chrominance signal output. 3: (R) analog red signal output. 4: (Pr) analog progressive chrominance signal output. Page 12
Mode 3: CVBS+RGB
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CT212
AVO3
AO
This pin is: In mode 1: (CVBS) analog composite signal output. 2: (CVBS) analog composite signal output. 3: (CVBS) analog composite signal output. 4: (Y) analog progressive luminance signal output.
FSADJ
AO
Full-scale adjust control pin. The full-scale current of DAC is controlled by connecting a resister (RSET) between this pin and AVSSref. The full-scale current IOUT = K * VREF / RSET (mA), K = 2765 for 3.3V VDD.
VREF
AO
Voltage reference output. Typical value is 0.9V. A 0.1uF ceramic capacitor decouples this pin to AVSSref
AVD33 AVSS AVDDref AVSSref VDDDAC VSSDAC GPB2/Hsync
AP AG AP AG DP
3.3v analog power supply of video DAC Analog ground of video DAC 3.3v analog reference voltage supply of video DAC Analog reference ground of video DAC
DG I/O
3.3V digital power supply of video DAC www.DataSheet4U.com Digital ground of video DAC General purpose IO bus B bit 2, initial in input state/Horizontal sync output; GPB2 by default
GPB3/Vsync
I/O
General purpose IO bus B bit 3, initial in input state/Vertical sync output; GPB3 by default
4.5 Audio Interface Signals

Pin name ACLK Type I/O Description Clock for audio sampling rate. Its frequency can be 256fs or 384fs. (fs is audio sampling rate.) The default is in output state and 384fs. PCMCLK PCMSD0 PCMSD1 PCMSD2 O O O O Audio PCM clock output PCM Serial Data output for left/right channel or stereo L/R channel PCM Serial Data output for left surround/right surround channel PCM Serial Data output for center/LFE channel Page 13
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CT212
PCMSD3 PCMWS S/PDIF
O O O
PCM Serial Data output for down-mixed L/R channel PCM channel word select output IEC-958 self-clocking digital serial output
4.6 NIM Interface Signals

Pin name Nimerr Nimsyn Nimvld Nimclk Nimd[7]/NimdA Nimd[6:1] Nimd[0]/NimdB SCL SDA LNBC[4:0] Type I I I I I Description Error of parallel/serial input Sync of parallel/serial input Valid of parallel/serial input Clock of parallel/serial input Parallel data input bit[7]/serial data input A
I Parallel data input bits[6:1] www.DataSheet4U.com I Parallel data input bits[0]/serial data input B I/O I/O O Serial control clock Serial control data LNB control output bits[4:0], reflecting the setting of corresponding bits in reg. LNB control
4.7 Panel Control Signals

Pin name Stbyled# Lockled# Keydet Dsplycm[3:0] Type O O I O Description Standby LED indicator, active low NIM lock LED indicator, active low Front panel key pressed detection Front panel 7-seg display common port[3:0]
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CT212
DsplyA DsplyB DsplyC DsplyD DsplyE DsplyF DsplyG DsplyP Dsplyclk
O O O O O O O O O
A segment of 7-seg display, active high B segment of 7-seg display, active high C segment of 7-seg display, active high D segment of 7-seg display, active high E segment of 7-seg display, active high F segment of 7-seg display, active high G segment of 7-seg display, active high Dot of 7-seg display, active high Clock for 7-seg display and key-pad scanning
4.8 Pin Map

Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSSP VDDP MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 DQML VDD MD15 VSSP MD14 MD13 MD12 Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
no. no. no. www.DataSheet4U.com 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 AVSSP LNBC0 LNBC1 LNBC2 LNBC3 VDDP LNBC4 VSSP VSS SCL VDD SDA CLKO PWM OSCI OSCO Nimsyn 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 NC VREF FSADJ AVD33 AVO0 AVSS AVD33 AVO1 AVSS AVD33 AVO2 AVSS AVD33 AVO3 AVSS GPB3/Vsync GPB2/Hsync 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 VDDP P1.3 VDD GPB0/INTTS# VSS P1.5/CS# P1.6 P1.7 P3.0 P3.1 P3.2 GPB1/INTM# P3.4 VDD P3.5 P3.6/WR# P3.7/RD# Page 15
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CT212
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS MD11 VDDP MD10 MD9 MD8 DQMH SDCLKI SDCLK VSSP MA11 MA9 MA8 MA7 MA6 MA5 VDDP MA4 SWE# VDD CAS# RAS# SCS#/SCS0# BS0/BA VSSP BS1/SCS1# VSS MA10 MA0 MA1 MA2 MA3 VDDP
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Nimerr Nimvld Nimclk Nimd7/NimdA Nimd6 Nimd5 Nimd4 Nimd3 Nimd2 Nimd1 Nimd0/NimdB VDD S/PDIF PCMSD3 PCMSD2
122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
SA0/GPA8 SA1/GPA9 VDD SA2/GPA10 SA3/GPA11 SA4/GPA12 SA5/GPA13 SA6/GPA14 SA7/GPA15 VSSP FWR# VDDP P2.0/SA8 P2.1/SA9 P2.2/SA10
174 175 176 177 178 179 180 181 182 183 184 185 186 187 188
P5.0 P5.1 P5.2 P5.3 VSSP P5.4 VSS P5.5 P5.6 P5.7 Lockled# Stbyled# Dsplyclk Dsplycm3 Dsplycm2 VDD Dsplycm1 VDDP Dsplycm0 DsplyA DsplyB DsplyC DsplyD DsplyE DsplyF DsplyG DsplyP VSS Keydet VSSP RESET# EMU AVSSP Page 16
85 PCMSD1 137 P2.3/SA11 189 www.DataSheet4U.com 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 PCMSD0 PCMWS PCMCLK VSSP ACLK VDDP GPA0/PD0 GPA1/PD1 GPA2/PD2 GPA3/PD3 VSS GPA4/PD4 GPA5/PD5 GPA6/PD6 GPA7/PD7 VDDDAC VSSDAC 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 P2.4/SA12 P2.5/SA13 P2.6/SA14 P2.7/SA15 VSS ALE PSEN#/LATS P0.7/SAD7 P0.6/SAD6 P0.5/SAD5 P0.4/SAD4 P0.3/SAD3 P0.2/SAD2 VSSP P0.1/SAD1 P0.0/SAD0 P1.0 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
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CT212
51 52
AVD18V VLFM
103 104
AVDDref AVSSref
155 156
P1.1 P1.2
207 208
VLFA AVD18
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CT212
5. System Diagram
The following diagram shows an example of CT212 application in a satellite DIGITAL TV STB receiver. In this example, CT212 operates with the NIM, SDRAM and audio DAC to achieve the purpose of low cost and simple system configuration. The Flash memory stores system firmware and command the system operation.
Satellite NIM Tuner

AD QPSK
1Mx16 *2 SDRAM
CVBS Y, C Y, Cr, Cb R, G, B
CT-212S
TS Demux MPEG-2 A/V decoder TV Encoder
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IR / Key Display Flash 4M bits
Audi
L/R 5.1 Channel
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CT212
6. Block Diagram
Following diagram shows the functional blocks of CT212.
M icrocontroller
Clock G enerator
Bitstream Parser
Transport Processor
Audio post-processor
NIM interface
Audio Decoder
digital audio out
Video Decoder
VBI Processor
Video post-processor & OSD
TV Encoder
analog video out
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SDRAM Interface controller
RISC Processor
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CT212
7.
Package Specification
HD D
208 157
156
E H
52
105
53
104
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c A
2
A See Detail F Seating Plane

1
L L1
Detail F
control dimensions are in mm
Symbol
Dimension in inch
Dimension in mm
Min Nom Max

0.145 0.004 0.122 0.006 0.004 1.097 1.097 0.016 1.193 1.193 0.012 0.043 0.127 0.008 0.006 1.102 1.102 0.020 1.205 1.205 0.020 0.051 0.132 0.010 0.010 1.107 1.107 0.024 1.217 1.217 0.028 0.059 0.004 0 10
Min Nom Max

3.68 0.10 3.10 0.15 0.10 27.87 27.87 0.40 30.30 30.30 0.30 1.10 3.23 0.20 0.15 28.00 28.00 0.50 30.60 30.60 0.50 1.30 3.35 0.25 0.25 28.13 28.13 0.60 30.90 30.90 0.70 1.50 0.10 0 10
A A1 A2 b c D E e HD HE L L1 y
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CT212
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Cheerteks Locations
Corporate Headquarter
5F-2, No.2-1, Li Hsin Rd. Science-Based Industrial Park Hsinchu, Taiwan, R.O.C. Tel: 886-3-666-7777 Fax: 886-3-611-2216, 886-3-666-7999
Cheertek (ShangHai) Ltd.

27F, 2299 Yan An Road (west), Shanghai, China Tel: 86-21-62361579; 86-21-6236599 Fax: 86-21-62361562
Shenzhen Office, Cheertek (ShangHai) Ltd.

Rm. 26C, Oriental Building, No.1072, Jian She Lu, Shenzhen , China Tel: 86-755-83643001 Fax: 86-755-83643186
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Copyright (C) 2003 Cheertek Inc. All Rights Reserved.

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Highlight processing Seamlessly link adjacent OSD regions

64 mix-weighting level for blending OSD and video Bitmap OSD

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4.2 Micro-controller Interface Signals

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SAD[7:0]: low byte address and data bus, bi-directional.

SA[15:8]: high byte address bus, input.

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P3.3: INTM#, output P3.6: WR#, input P3.7: RD#, input

Port5 is an 8-bit bi-directional I/O port, default in input state.

Flash write enable output

4.2.1 External Micro-controller Mode

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SA[15:8] CS# INTTS# INTM# WR# RD#

4.3 SDRAM Interface Signals

SDRAM Bank Select output

SDCLK SDCLKI SCS#

Row Address Strobe output, active Low

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Column Address Strobe output, active Low

SWE# DQML DQMH

SWE# DQML DQMH

4.4 Video Interface Signals

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AVD33 AVSS AVDDref AVSSref VDDDAC VSSDAC GPB2/Hsync

4.5 Audio Interface Signals

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PCMSD3 PCMWS S/PDIF

4.6 NIM Interface Signals

4.7 Panel Control Signals

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DsplyA DsplyB DsplyC DsplyD DsplyE DsplyF DsplyG DsplyP Dsplyclk

4.8 Pin Map

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Satellite NIM Tuner

L/R 5.1 Channel