#1, 1st Main 4th Cross, Dinnur Road R.T.Nagar, Bangalore -32. hemant_nautiyal@yahoo.co.

in Phone: 9448377029 (M) OBJECTIVE

Hemant Nautiyal

I did my M.Tech. from IIT Delhi in Communication Engineering(EE Deptt.) and currently working in C-DOT, Bangalore as Research Engineer.I am working as a team member for the design and implementation of Base-band unit for WCDMA base station. Seeking a challenging position in Wireless Engineering utilizing my proven abilities developed through my experience and education. My skills can be applied to fields related to wireless algorithm development and digital base-band design. I wish to use my skills for growing with a prestigious firm along with personal grooming. EDUCATIONALQUALIFICATIONS M.Tech in Communication Engineering IIT Delhi December 2001 C.G.P.A: 8.604/10

B.Tech in Electronics and Communication Engineering June 2000 College Of Technology C.G.P.A : 4.714 / 5 ( 85.64%) G.B.Pant Univ. Of Ag. & Tech. Pant Nagar.

SKILLSSUMMARY Programming Languages: VHDL, C, C++, MATLAB 5.3, Assembly Language Programming For TMS320C50 DSP processors and Microprocessor8085/86. Tools Technologies Devices : Synplify 7.2 for FPGA Synthesis, Quartus 3.0 Modelsim 5.7 for simulation. : WCMDA Physical Layer Standard (3GPP Rel 5). : Alteras FPGA, TIsDSP.

RELATEDSKILLSOFCONCERN Algorithm Development for enabling wireless technologies eg. Tx, Rx. Diversity and STC and implementation inFPGA. Hands-on experience designing and testing WCDMA 3G system A high level of motivation and quest for knowledge. Problem solving skills. A good team player.

WORK EXPERIENCE

Presently working for the Development of Rural Wireless Project for GSM and I am working for the study of standards of GSM Speech Coders(HR,FR,EFR). Feb 2003 June 2004 : Research Engineer, C-DOT, Bangalore,

PROJECT Implementation of WCDMA BaseStation(nodeB). Platform : WindowsXP, Alteras Stratix DSP and Nios Development board. Language : VHDL, C, Matlab. Responsibility : Design and Implementation of Rake Receiver and Controller. My first assignment was to study the WCDMA standard based on 3GPP release5 and enabling wireless technologies eg.: MIMO, Diversity, Beamforming and MUD. Next was about the algorithms for power control, SIR and Channel estimation and combining techniques. Implementation approach of Rake is based on system on programmbale chip(SOPC). Rake receiver code is written in VHDL. Nios soft processor is used to control the functionality of Rake receiver.Nios soft Processor is generated using SOPC builder to control the Rake receiver and Integration of soft processor is done with Rake. Finally whole system is fused in alteras Stratix FPGA. Next on-board testing and simulation is done of the whole system. Apr 2002 Feb 2003 : ScientistB, Defence Electronics & Application Lab(DRDO),

PROJECT Development of CDMA Base-band unit for secure SATCOM network. Platform : Windows2000

Language : VHDL, Matlab Responsibility : Development of serial parallel Matched Filter. I worked for the project, CDMA Base-band unit for secure SATCOM network in DRDO. I worked for the design and implementation of PN code generator and PN code Synchronizer (Matched filter) in FPGA using VHDL and schematic design entry.

M.Tech. PROJECTS
1. M Tech Major Project Completed six month M. Tech. project on, Semi-blind detection of Quasi-synchronous DS/CDMA signals using multiple transmit and receiver antennas under the guidance of Prof. Surendra Prasad, EE Deptt. IIT Delhi. The project aim was to incorporate transmit diversity by use of space-time coding technique for high data rate in multi-user ( DS-CDMA) environment, at the receiving end an array of antennas is used to detect signal by use of blind detection technique in which we dont need the channel information and user code, it is inspired by spatial smoothing technique. Simulation is done in Matlab 5.3. Minor Project of M. Tech. Topic: Study of Space time architectures and simulation of Bell labs space time architecture (BLAST) and simulation. Summary: In this project we study the techniques of using multiple antennas at the transmitter to increase the data rate by using space time block coding technique and to show the performance.

Relevant Courses Done/Undertaken in M.Tech. Computer network C++ , OS Estimation and Detection Digital Communication & Signal Theory Digital Signal Processing Implementation of DSP algorithms inTMS320C5X D.S.P. Processor using assembly langauage programming. Microstrip filter designing for high frequency.

B.E PROJECT The project aimed at implementing image compression technique using discrete cosine transform.
PERSONAL PARTICULARS Name : Hemant Nautiyal Late Shri B.P.Nautiyal 29th December 1977 Single Male

Father's Name : Date Of Birth : Marital Status : Sex :

Awards and achievements:

1.National scholarship holder upto Intermediate. 2. Merit Scholarship in throughout B.Tech. 3. Scored 97.90 percentile in GATE-2000. 4. IInd rank in branch in B.Tech. 5. IInd rank in branch in M.Tech.

Mailing Address #1, 1st Main 4th Cross, Dinnur Road R.T.Nagar, Bangalore -32. hemant_nautiyal@yahoo.co.in Phone: 9448377029(M)

Permanent Address H No. # 7, Amrakunj Srinagar(Garhwal), Pauri Uttaranchal-246174 01346-252938