7.

1 REPRESENTATION OF FLOATING-POINT NUMBERS

N = F x 2E
Examples of floating-point numbers using a 4-bit fraction and 4-bit exponent:
F = 0.101 E = 0101
F = 1.011 E = 1011
F = 1.000 E = 1000

N = 5/8 x 25
N = 5/8 x 25
N = 1 x 28

Normalization
Unnormalized:
Normalized:

F = 0.0101
F = 0.101

E = 0011
E = 0010

Unnormalized:
(shift F left)
Normalized

F = 1.11011 E = 1100
F = 1.1011 E = 1011
F = 1.011
E = 1010

Representation of Zero
F = 0.000, E = 1000

or

0.000 x 2-8

N = 5/16 x 23 = 5/2
N = 5/8 x 22 = 5/2
N = 5/32 x 24 = 5 x 29
N = 5/16 x 25 = 5 x 29
N = 5/8 x 26 = 5 x 29

Figure 7-1 Flowchart for Floating-Point Multiplication

Start

Add Exponents
Multiply Fractions

Set E = 8

Done

F=0
Y

F
Overflow
Y

Set F = 1/2
E <= E+1

F
Normalized

N
Shift F Left
E <= E-1

Exp
Overflow
N

Done

Set Indicator

Figure 7-2(a) Exponent Adder and Fraction Multiplier

E1
Load

Load

St

FV

Adx

Mdone
FZ

SM8
Inc
Dec

Adx

SM8

Main
Control

5-bit Full Adder

RSF = Inc
LSF = Dec

Fnorm
EV

Done

Load

E2

Figure 7-2(b) Exponent Adder and Fraction Multiplier

F
RSF
Load
AdSh
Sh

A (accumulator)
3

B
0

LSF

F2
4-bit Full Adder

M
Sh
AdSh

1's Complementer

Multiply
Control

Cm
Mdone

Load

F1

Adx

Figure 7-3 SM Chart for floating-Point Multiplication

1

FZ

S0 /
SM8
1

St

RSF

FV
1

Fnorm

1
S3 / Done

Load
S1 / Adx

LSF
add exponents,
start multiply
Fraction
Multiplier
Control

S2 /

EV

Mdone
1

St
0

Figure 7-4 State Graph for Multiplier Control

Adx'/0
S0
/Mdone
S4

S1
M/AdSh
M'/Sh

M/Cm AdSh
M'/Sh
S3

Adx M/AdSh
Adx M'/Sh

M/AdSh
M'/Sh

S2

Figure 7-5(a) VHDL Code for Floating-Point Multiplier

library BITLIB;
use BITLIB.bit_pack.all;
entity FMUL is
port (CLK, St: in bit; F1,E1,F2,E2: in bit_vector(3 downto 0);
F: out bit_vector(6 downto 0); V, done:out bit);
end FMUL;
architecture FMULB of FMUL is
signal A, B, C: bit_vector(3 downto 0);
-- fraction registers
signal X, Y: bit_vector(4 downto 0);
-- exponent registers
signal Load, Adx, Mdone, SM8, RSF, LSF, NC: bit; signal AdSh, Sh, Cm: bit;
signal PS1, NS1: integer range 0 to 3;
-- present and next state
signal State, Nextstate: integer range 0 to 4;
-- mulitplier control state
alias M: bit is B(0); constant one:bit_vector(4 downto 0):="00001";
constant neg_one:bit_vector(4 downto 0):="11111";
begin
main_control: process
begin
Load <= '0'; Adx <= '0';
-- clear control signals
SM8 <= '0'; RSF <= '0'; LSF <= '0';
case PS1 is
when 0 => done<='0'; V<='0';
-- clear outputs
if St = '1' then Load <= '1'; NS1 <= 1; F <= "0000000"; end if;
when 1 => Adx <= '1'; NS1 <= 2;

Figure 7-5(b) VHDL Code for Floating-Point Multiplier

when 2 => if Mdone = '1' then
-- wait for multiply
if A = "0000" then SM8 <= '1';
-- zero fraction
elsif A = "0100" and B = "0000" then -- fraction overflow
RSF <= '1';
-- shift AB right
elsif A(2) = A(1) then
-- test for unnormalized
LSF <= '1';
-- shift AB left
end if; NS1 <= 3;
end if;
when 3 =>
--test for exp overflow
if X(4) /= X(3) then V <= '1'; else V <= '0'; end if;
done <= '1';
F <= A(2 downto 0) & B;
--output fraction
if ST = '0' then NS1<=0; end if;
end case;
wait until rising_edge(CLK);
PS1 <= NS1;
wait for 0 ns;
--wait for state change
end process main_control;
mul2c: process
--2's complement multiply
begin
AdSh <= '0'; Sh <= '0'; Cm <= '0';
--clear control signals
case State is
when 0=> Mdone <= '0';
--start multiply
if Adx='1' then
if M = '1' then AdSh <= '1'; else Sh <= '1'; end if;
Nextstate <= 1;
end if;

Figure 7-5(c) VHDL Code for Floating-Point Multiplier

when 1 | 2 =>
--add/shift state
if M = '1' then AdSh <= '1'; else Sh <= '1'; end if;
Nextstate <= State + 1;
when 3 =>
if M = '1' then Cm <= '1'; AdSh <= '1'; else Sh <='1'; end if;
Nextstate <= 4;
when 4 => Mdone <= '1'; Nextstate <= 0;
end case;
wait until rising_edge(CLK);
State <= Nextstate;
wait for 0 ns;
--wait for state change
end process mul2c;
update: process
variable addout: bit_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if Cm = '0' then addout := add4(A,C,'0');
else addout := add4(A, not C,'1'); end if;
if Load = '1' then X <= E1(3)&E1; Y <= E2(3)&E2;
A <= "0000"; B <= F2; C <= F1; end if;
if ADX = '1' then addvec(X,Y,'0',X,NC,5); end if;
if SM8 = '1' then X <= "11000"; end if;
if RSF = '1' then A <= '0'&A(3 downto 1);
B <= A(0)&B(3 downto 1);
addvec(X,one,'0',X,NC,5); end if;

--update registers

--add 2's comp. of C

-- increment X

Figure 7-5(d) VHDL Code for Floating-Point Multiplier

if LSF = '1' then
A <= A(2 downto 0)&B(3); B <= B(2 downto 0)&'0';
addvec(X,neg_one,'0',X,NC,5); end if;
-- decrement X
if AdSh = '1' then
A <= (C(3) xor Cm) & addout(3 downto 1);
-- load shifted adder
B <= addout(0) & B(3 downto 1); end if;
-- output into A & B
if Sh = '1' then
A <= A(3) & A(3 downto 1);
-- right shift A & B
B <= A(0) & B(3 downto 1);
-- with sign extend
end if;
end process update;
end FMULB;

Figure 7-6(a) Test Data for Floating-Point Multiply

list f x f1 e1 f2 e2 v done
force f1 0111 0, 1001 200, 1000 400, 0000 600, 0111 800
force e1 0001 0, 1001 200, 0111 400, 1000 600, 0111 800
force f2 0111 0, 1001 200, 1000 400, 0000 600, 1001 800
force e2 1000 0, 0001 200, 1001 400, 1000 600, 0001 800
force st 1 0, 0 20, 1 200, 0 220, 1 400, 0 420, 1 600, 0 620, 1 800, 0 820
force clk 0 0, 1 10 -repeat 20
run 1000

Figure 7-6(b) Simulation Results for Floating-Point Multiply

ns delta
f
x
f1
e1
f2
e2
0
+0 0000000 00000 0000 0000 0000 0000
0
+1 0000000 00000 0111 0001 0111 1000
10
+1 0000000 00001 0111 0001 0111 1000
30
+1 0000000 11001 0111 0001 0111 1000
150
+2 0110001 11001 0111 0001 0111 1000
170
+2 0000000 11001 0111 0001 0111 1000
200
+0 0000000 11001 1001 1001 1001 0001
250
+1 0000000 11010 1001 1001 1001 0001
370
+2 0110001 11010 1001 1001 1001 0001
390
+2 0000000 11010 1001 1001 1001 0001
400
+0 0000000 11010 1000 0111 1000 1001
430
+1 0000000 00111 1000 0111 1000 1001
450
+1 0000000 00000 1000 0111 1000 1001
570
+1 0000000 00001 1000 0111 1000 1001
570
+2 0100000 00001 1000 0111 1000 1001
590
+2 0000000 00001 1000 0111 1000 1001
600
+0 0000000 00001 0000 1000 0000 1000
630
+1 0000000 11000 0000 1000 0000 1000
650
+1 0000000 10000 0000 1000 0000 1000
770
+1 0000000 11000 0000 1000 0000 1000
770
+2 0000000 11000 0000 1000 0000 1000
790
+2 0000000 11000 0000 1000 0000 1000
800
+0 0000000 11000 0111 0111 1001 0001
830
+1 0000000 00111 0111 0111 1001 0001
850
+1 0000000 01000 0111 0111 1001 0001
970
+2 1001111 01000 0111 0111 1001 0001
990
+2 0000000 01000 0111 0111 1001 0001

v
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0

done
0
0 (0.111 x 2 1) x (0.111 x 2-8)
0
0
1
= 0.110001 x 2-7
0
0 (1.001 x 2 -7) x (1.001 x 21)
0
1
= 0.110001 x 2-6
0
0 (1.000 x 2 7) x (1.000 x 2-7)
0
0
0
1
= 0.100000 x 21
0
0 (0.000 x 2 -8) x (0.000 x 2-8)
0
0
0
1
= 0.0000000 x 2-8
0
0 (0.111 x 2 7) x (1.001 x 21)
0
0
1
= 1.001111 x 28 (overflow)
0

Figure 7-7 Bus Structure for Floating-Point Multiplier

Fraction
Adder

C(F1)
Input

Exponent
Adder

B(F2)

X(E1) Y(E2)

Figure 7-8(a) Top-level Schematic for Floating-Point Multiplier

F10
D0 Q0
F11
D1 Q1
CO CO
F12
D2 Q2
F1[3-0]
F13
D3 Q3
F1[3-0]
FSUM[4-0]
CE
FS[4-0]
F1_Register
C
F2[3-0]
CLR
FD4CE
FRACTION
ADDER
GND
CLR
CLR A[3-0]
B3
A[3-0]
B3
FSUM1
S1
FSUM2
S2
FSUM3
A_Register
S3
FSUM4
F1C3
LSF
LSF
ADSH
FV
ADSH FV
RSF
FZ
FZ
RSF
SH
FN
FN
SH
C
C
DB0
DB1
DB2
DB3
L1
C

MAIN
C2
C
FV
FZ
FN

DONE
C2
ST
CLR
C
ADX
FV
FZ
RSF
FN
MDONE
LSF

MDONE

DONE
CLR
ADX
RSF
LSF
SM8

SM8

Multiplier
ADX
B0
C

IPAD4
ST
I3
SW0
I2
SW1
I1
LD
I0

ADX
B0
C

MDONE
ADSH
CD
SH

ADSH
CD
SH

FSUM[4-0]

IBUF4

A0

D2_4E
A0 B0
A1 B1
B2
E
B3

L1
L2
L3
L4

DB

LZ
LSF
RSF
ADSH
SH
C

B_Register
A0
FSUM0 S0
DB[3-0]
B[3-0]
LFZ
LSF
RSF
ADSH
SH
C

A0
A1
A2
B[3-0]

Data_Out1
A0
A1
A2
B[3-0]

Figure 7-8(b) Top-level Schematic for Floating-Point Multiplier

DB
LD
DONE

IPAD4
I3
I2
I1
I0

IBUF4
D3
D2
D1
D0

T BUFT4
DB3
DB2
DB1
DB0
DB[3-0]

F490
F15

C
BUFG
C2
BUFG

ADX
RSF
LSF

DONE
DB[3-0]
E1[4-0]
E1[4-0]

S4
SM8
L3
RSF
LSF
C
ADX

OSC4
FBM
F500K
F15K

Exponent
Adder

E1_Register (X)

DB0
DB1
DB2
DB3
L4
C

IN4
SM8
LE1
RSF
LSF
C
ADX

Data_Out2

IN
DE

S4

E1[4-0]
S[3-0]

E1[4-0]
E2[3-0]
V

E2_Register (Y)
D0 Q0 E20
E21
D1 Q1
E22
D2 Q2
D3 Q3 E23
CE
C
CLR
GND

ADX

E2[3-0]

S4

Figure 7-9 Main Control for Floating-Point Multiplier

DONE

FD
D

CLR
Q0

C
FD
D

ADX
Q1

C
FD
D

Q2

RSF

C
FD

FD
ST D
C2

C
MDONE
FV
FNORM
FZ

LSF
Q3

C
SM8

Figure 7-10 Multiplier Control

FD
D

MDONE

Q
Q4

CO
FD

Q
Q3

C
SH

FD
D

Q
Q2

C
ADX
FD
D

Q
Q1

C
C

BO

ADSH

Figure 7-11 A Register

X74_194
S1
S2
S3
F1C3
LSF

ADSH
RSF
SH

B3

SLI
A
QA
B
QB
C
QC
D
QD
SRI
S0
S1
CK
CLR

FV
A0
A1
A2
A3

FZ

FN

A[3-0]

C
CLR

Name=A.1

Figure 7-12 E1 Register

DB[3-0]

DB0
SM8
DB1

DB2

DB3
M2-1
IN4

SM8
LE1
ADX
DC
IC
C
DONE

D0
D1

Q
SE

D0
D1
D2
D3
D4
C
CE
RD

Q0
Q1
Q2
Q3
Q4

E10
E11
E12
E13
E14

E1[4-0]

RD5CR

GND
V

Figure 7-13 Exponent Adder

ADX
DE
IN

ADD4
E1[4-0]

E2[3-0]

E10
E11
E12
E13

E20
B0
E21
B1
E22

CI
A0
A1
A2
A3

B0
B1
B2
B3 CO

S0
S1
S2
S3

E14
B2

E23
B3

BUFT4
S0
S1
S2
S3

S4

S[3-0]

FLOATING POINT ADDITION (from page 259)

(F1 x 2E1) + (F2 x 2E2) = F x 2E
Example 1:

Example 2:

Add

F1 x 2E1 = 0.111 x 25 and F2 x 2E2 = 0.101 x 23

Unnormalize

0.101 x 23 = 0.0101 x 24 = 0.00101 x 25

Add fractions

(0.111 x 25) + (0.00101 x 25) = 01.00001 x 25

Fix Overflow

F x 2E = 0.100001 x 26

(1.100 x 22) + (0.100 x 21)

= (1.110 x 21) + (0.100 x 21) (after shifting F1)
= 0.010 x 21

(result of adding fractions is unnormalized)

= 0.100 x 22

(normalized by shifting left and subtracting one from

exponent)

FLOATING POINT ADDITION SUMMARY (from page 260)

1)

If exponents are not equal, shift the fraction with the smallest exponent
right and add 1 to its exponent; repeat until the exponents are equal.

2)

Add the fractions.

3)

(a) If fraction overflow occurs, shift right and add 1 to the exponent to
correct the overflow.
(b) If the fraction is unnormalized, shift left and subtract 1 from exponent
until the fraction is normalized.
(c) If the fraction is 0, set the exponent to the appropriate value.

4)

Check for exponent overflow.