Sequential Logic

Counters

Sequential Logic
Counters

Flip-Flops: The Building Block

Flip-Flops: The Building Block

Flip-Flops: The Building Block

Asynchronous Counters
async = events that DO NOT occur at the
same time

async counter = FFs within the counter

DO NOT have a common clock pulse

Asynchronous Counters
async = events that DO NOT occur at the
same time

async counter = FFs within the counter

DO NOT have a common clock pulse

Asynchronous Counters
async = events that DO NOT occur at the
same time

async counter = FFs within the counter

DO NOT have a common clock pulse

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

0 0

2-bit Asynchronous Binary Counter

0 0 0

2-bit Asynchronous Binary Counter

0 0

1 0

2-bit Asynchronous Binary Counter

0 0

1 0 1

2-bit Asynchronous Binary Counter

0 0

1 0

0 1

2-bit Asynchronous Binary Counter

0 0

1 0

0 1 1

2-bit Asynchronous Binary Counter

0 0

1 0

0 1

1 1

2-bit Asynchronous Binary Counter

0 0

1 0

0 1

1 1

3-bit Async Bin Counter

3-bit Async Bin Counter

3-bit Async Bin Counter

Asynchronous Counter a.k.a. Ripple Counter

Propagational Delay

Propagational Delay
o j a m a v d a s i d r

! e g a nt

Calculate the delay

Calculate the delay

re a Bew

Asynchronous Decade Counters

Asynchronous Decade Counters

Binary counters

Asynchronous Decade Counters

Binary counters count from 0 to 2
n-1 (n=no. of

FFs)

Asynchronous Decade Counters

Binary counters count from 0 to 2 (n=no. of FFs) What if ... you need to count just from 0 to 9?
n-1

The Answer

The Answer
Do partial decoding

The Answer
Do partial decoding

The Answer
Do partial decoding

The Answer
Do partial decoding

BCD Decade Counters

(4-bit asynchronous binary counter)

74LS93

(4-bit asynchronous binary counter)

74LS93

(4-bit asynchronous binary counter)

74LS93

(4-bit asynchronous binary counter)

74LS93

(4-bit asynchronous binary counter)

74LS93
C C CTR DIV 12

CLK A CLK B RO(1) RO(2)

Q0 Q1 Q2 Q3

That was async...

Now, its time for Synchronous counters

Synchronous Counter

Synchronous Counter
FFs in the counter are clocked at the same
time by a common clock pulse.

Synchronous Counter
FFs in the counter are clocked at the same
time by a common clock pulse. counter...

Lets begin with a 2-bit synchronous binary

2-bit Synchronous Binary Counter

Whats going on?

What would we get?

What would we get?

delay is neglected for simplicity

3-bit Synchronous Binary Counter

3-bit Synchronous Binary Counter

3-bit Synchronous Binary Counter

4-Bit Sync Bin Counter

4-bit Synchronous Decade Counter

Up/Down Sync Counters

Up/Down Sync Counters

progressing in either direction (up/down)

Up/Down Sync Counters

progressing in either direction (up/down) may be called a bidirectional counter

Up/Down Sync Counters

progressing in either direction (up/down) may be called a bidirectional counter

012345 up

Up/Down Sync Counters

progressing in either direction (up/down) may be called a bidirectional counter

012345432 up dn

Up/Down Sync Counters

progressing in either direction (up/down) may be called a bidirectional counter

012345432 34567 up dn up

Up/Down Sync Counters

progressing in either direction (up/down) may be called a bidirectional counter

0 1 2 3 4 5 4 3 2 3 4 5 6 7 6 5 etc... up dn up dn

Lets make one (3-bit counter)

Lets make one (3-bit counter)

Lets make one (3-bit counter)

Q0: J0 = K0 = 1

Lets make one (3-bit counter)

Q0: J0 = K0 = 1 Q1: J1 = K1 = (Q0 ! UP) + (Q0 ! DN)

Lets make one (3-bit counter)

Q0: J0 = K0 = 1 Q1: J1 = K1 = (Q0 ! UP) + (Q0 ! DN) Q2: J2 = K2 = (Q0 ! Q1 ! UP) + (Q0 ! Q1 ! DN)

Lets make one (3-bit counter)

Lets make one (3-bit counter)

Lets make one (3-bit counter)

Q0: J0 = K0 = 1

Lets make one (3-bit counter)

Q1: J1 = K1 = (Q0 ! UP) + (Q0 ! DN)

Lets make one (3-bit counter)

Q2: J2 = K2 = (Q0 ! Q1 ! UP) + (Q0 ! Q1 ! DN)

Lets make one (3-bit counter)

Design of Synchronous Counters

General Model of a Sequential Circuit

Step 1: State Diagram

3-bit Gray code counter

Step 2: Next-state Table

The next state is the state that the counter goes to from its present state upon the application of a clock pulse.

Step 3: Flip-op Transition Table

Step 4: Karnaugh Maps

Step 4: Karnaugh Maps

Step 4: Karnaugh Maps

Step 4: Karnaugh Maps

Step 4: Karnaugh Maps

Step 4: Karnaugh Maps

Step 5: Logic Expressions for FF Inputs

Step 5: Logic Expressions for FF Inputs

J0 = Q2Q1+Q2Q1 = Q2

_ _

Q1

Step 5: Logic Expressions for FF Inputs

K0 = Q2Q1+Q2Q1 = Q2

_ _ J0 = Q2Q1+Q2Q1 = Q2 _ _

Q1 Q1

Step 5: Logic Expressions for FF Inputs

K0 = Q2Q1+Q2Q1 = Q2 J1 = Q2Q0

_ _ J0 = Q2Q1+Q2Q1 = Q2 _ _ _

Q1 Q1

Step 5: Logic Expressions for FF Inputs

K0 = Q2Q1+Q2Q1 = Q2 J1 = Q2Q0 K1 = Q2Q0

_ _ J0 = Q2Q1+Q2Q1 = Q2 _ _ _

Q1 Q1

Step 5: Logic Expressions for FF Inputs

K0 = Q2Q1+Q2Q1 = Q2 J1 = Q2Q0 K1 = Q2Q0 J2 = Q1Q0

_ _ J0 = Q2Q1+Q2Q1 = Q2 _ _ _

Q1 Q1

Step 5: Logic Expressions for FF Inputs

K0 = Q2Q1+Q2Q1 = Q2 J1 = Q2Q0 K1 = Q2Q0 K2 = Q1Q0

_ _ J0 = Q2Q1+Q2Q1 = Q2 _ _ _

Q1 Q1

_ J2 = Q1Q0 _ _

Step 5: Logic Expressions for FF Inputs

K0 = Q2Q1+Q2Q1 = Q2 J1 = Q2Q0 K1 = Q2Q0 K2 = Q1Q0

_ _ J0 = Q2Q1+Q2Q1 = Q2 _ _ _

Q1 Q1

_ J2 = Q1Q0 _ _

Step 6: Counter Implementation

Step 6: Counter Implementation

K0 = Q2Q1+Q2Q1 = Q2

_ _ J0 = Q2Q _1+Q _ 2Q1 = Q2

Q1 Q1

Step 6: Counter Implementation

K0 = Q2Q1+Q2Q1 = Q2

_ _ J0 = Q2Q _1+Q _ 2Q1 = Q2

Q1 Q1

J1 = Q2Q0 K1 = Q2Q0

Step 6: Counter Implementation

K0 = Q2Q1+Q2Q1 = Q2

_ _ J0 = Q2Q _1+Q _ 2Q1 = Q2

Q1 Q1

J1 = Q2Q0 K1 = Q2Q0

K2 = Q1Q0

_ J2 = Q _ 1Q _0

Exercise

Exercise
001 (1) 111 (7) 101 (5) 010 (2)

Exercise
001 (1) 111 (7) 101 (5) 010 (2)

Thats all for synchronous counters

Now, its time for the last assignment.

Design the circuit

Design the circuit

000 100 001

101

011

111 110

010

Design the circuit

000 100 001

101

011

111 110

010

Design the circuit

000 100 001

101

011

111 110

010

Design the circuit

1

000

Y=1

100
1

001
1

101
1

011
1

111
1

010 110
1

Design the circuit

1

000
0

Y=1 Y=0

100
1 0

001
1 0

101
1 0 0 0 1 0

011
1

111

010
1

110

Design the circuit

1

000
0

Y=1 Y=0

100
1 0

001
1 0

101
1 0

3-bit up/down Gray code counter

011
0 1

111

0 1

010
1

110

What would you do?

What would you do?

Form a group of 4.

What would you do?

Form a group of 4. Do the design (follow the steps mentioned
previously).

What would you do?

Form a group of 4. Do the design (follow the steps mentioned
previously).

Explain each step and nish with the logic

circuit diagram.

How to submit?

How to submit?
Submit in electronic form (PDF le is
preferred) to my email apisake@cp.su.ac.th

How to submit?
Submit in electronic form (PDF le is
preferred) to my email apisake@cp.su.ac.th

email subject must include [517341]

How to submit?
Submit in electronic form (PDF le is
and ID number. preferred) to my email apisake@cp.su.ac.th

email subject must include [517341] Dont forget your group members name

How to submit?
Submit in electronic form (PDF le is
and ID number. preferred) to my email apisake@cp.su.ac.th

email subject must include [517341] Dont forget your group members name Deadline: Final exam date (To Be Announced)

HINT

HINT
There are 4 variables for the Karnaugh Map.

HINT
There are 4 variables for the Karnaugh Map. Designing a synchronous counter will appear
in your nal exam. Moreover, it would be a big score. ;-)

Lets continue...

Counter Decoding

Counter Decoding

Counter Decoding

Counter Application: A Digital Clock