Programmable Counter Design in LabVIEW Targeting DE FPGA Board

Goal:
The goal of this lab exercise is to develop a programmable counter using case and while loop structures. You will verify the design using DE FPGA Board and NI ELVIS system.

Design Problem Statement:

Design a 4-bit programmable counter which is capable of up- and down-counting, resetting, providing terminal count indication, loading a parallel 4-bit input, and holding a count based on required function through input signals. The counter will have reset as the highest precedence, hold as the next, followed by load, and up/down as the lowest precedence control input. The counter counts up when up/down is logic 1 and counts down otherwise. The Terminal Count is logic 1 when the Parallel Count Output is 15 when the counter is up-counting. It becomes logic 1 when the Parallel Count Output is 0 (zero) when the counter is down-counting. The block diagram is shown below.
Parallel Count Input 4 reset hold up/down load Programmable Counter Parallel Count Output 4 Terminal Count

Implementation:
Circuit functionality requires preservation of order of precedence of control input. The order of precedence can be implemented using cascaded select functional blocks. The terminal count is computed differently depending on whether up counting is going on or down-counting. This can be implemented using case structure. The increment and decrement functions are performed on unsigned integer whereas parallel input are Boolean, so they need to be converted to unsigned integer using build array and Boolean number conversion functions. Conversely, the output of the counter needs to be converted to Boolean so they can be connected to LEDs or GPIO lines. The whole design must be in a while loop which is controlled by stop input.

To get a quick introduction to LabVIEW, take the Learn LabVIEW in 3 hours course (http://www.ni.com/academic/learn_LabVIEW/) Section 1: Developing a design Procedure:
Extract counter_Lab.zip file in c:\NI\LabVIEW_Labs folder Start LabVIEW program (Start All Programs National Instruments LabVIEW) Select File New Project In the Project Explorer window, select My Computer, right-click and select New Targets and Devices

Click on New target or device and select DE FPGA Board under ELVIS

Click OK

Click File Save and save the project as counter in c:\NI\LabVIEW_Labs\counter_Lab folder Right-click on FPGA Target (Board1, DE FPGA Board) in Project Explorer and select New VI

Select File Save and browse to c:\NI\LabVIEW_labs\counter_Lab, give File name for the VI as counter and click OK Next add FPGA IOs Select FPGA Target (Board1, DE FPGA) in the Project Explorer, right-click and select New FPGA I/O I/Os available on the target board (DE FPGA) is displayed on the left side of the form In the Available Resources expand Slide Switches folder and select SW0 for up or down count - ON indicates up count and OFF indicates down count. Select SW4 down to SW1 for the load value, and click the Add button to add them to the project In the Available Resources expand Push Buttons folder and select BTN0, BTN1, BTN2 and BTN3 (BTN0 to reset the counter, BTN1 for loading initial value, BTN2 to hold counting, and BTN3 to terminate counting). Click on Add button to add them to the project. Similarly, expand Discrete LEDs folder, add LED4 for terminal count, and LED3 down to LED0 to display the current count Click OK to accept the selections and close the form The Project Explorer window will look like shown below

Add a while loop in the Block Diagram window Right-click on the while loop frame and select Add Shift Register Add numeric constant outside the while loop and connect to the input shift register Change the number representation of the numeric constant to U8 by rightclicking on it, selecting Representation, and finally selecting U8 from the palette menu

Since our programmable counter is going to have order of precedence- reset being the highest, next is load, followed by hold, we will need three instances of select block. We will also need an instance of select block to increment or decrement a count Add four instances of select from comparison palette library Select all four buttons from the project explorer view, drag them, and place them inside the while loop Similarly, select SW0 from the project explorer view and place it inside the while loop Add increment (+1) and decrement (-1) functions from Numeric palette library Add indicators to SW0 and BTN0 through BTN3

Label the indicators appropriately such as BTN0 BTN1 BTN2 BTN3 SW0 reset load hold stop up/down~

Wire them as shown in the following diagram

Create a constant at the True input of the right most select instance Right-click any where inside the while loop and add FPGA I/O Node from the FPGA I/O palette library ( ). You can also search for this by hitting the Search button Assign it to SW1 by clicking on it and selecting Slide Switches SW1 Expand it and resize such that it includes SW1 through SW4 Add Build Array from the Array palette library and expand it to have four elements Connect SW1 through SW4 outputs to the input of the Build Array instance Add Boolean Array to Number from Boolean palette library and connect output of the Build Array to the input of the Boolean Array to Number instance

Connect the output of the Boolean Array to Number to the True input terminal of 2nd select instance (from right) which is controlled by BTN1 At this stage the design should look like as shown below

Add FPGA I/O Node from the FPGA I/O palette library Assign it to LED0 Change the LED element mode operation to Change to Write by rightclicking on it and selecting Change to Write Expand it to have four I/Os with assignments to LED0 to LED3 Add Index Array from Array palette library Expand it to have four elements Add Number to Boolean Array from Boolean palette library Connect output of the right-most select to Number to Boolean Array, the output of which to Index Array, and the individual output of which to individual LEDs At this stage the design should look like the one shown below

Add a sequence structure for terminal count output and connect up/down to the select (?) input of the case structure Add Equal (comparator) from the comparison palette array inside the True case. Connect the output of the right most select to one input of the comparator through the case structure. Create a constant of value 15 at the other input Connect the output of the comparator to the case structure frame to bring out the result. The partial design is as shown below

Select False case, add zero comparator (Equal to 0), connect the input of the case structure to the input terminal Connect the output of the zero comparator to the output terminal of the case structure Add LED4 from the project explorer to the block diagram and connect it to the case structure output Add an indicator and label it as tc Switch to Front Panel (Ctrl-E) In the front panel, create an array from the Array and Cluster palette library Add a round LED in it and expand the array (in horizontal direction) to show four LEDs Change the name of the array to Count Hide its Index Display by right-clicking and selecting Visible Items -> Index Display Add another array, add switch in it, expand it to have four switches and label the array as Parallel Input. Hide its index display also Switch to the block diagram and connect the count to the output of the Number to Boolean Array Right-click on the Parallel Input array and change it to Indicator Connect the Parallel Input to the output of the Build Array Add the Loop Timer from the Timing palette library and set the count unit to ms Create a constant at the input of the Loop Timer instance and set its value to 1000 (1000 ms = 1 second) The complete design should like similar to shown below

Switch to the Block Diagram (Ctrl-E) window Change look and feel of various inputs, resize and re-position the objects to have a clear and meaningful view such as shown below

Save the VI

Section 2: Testing the design using the board Procedure:

Connect the board, the USB cable, and power ON the board Click on Run ( ) button or select Operate Run Once the Bitstream generation is completed, a message is displayed in the Compile Server progress window, click X button on the top-right corner to close it. Click OK to close the summary status window

The FPGA will be configured. Once configured, indicated by highlighted RUN button as well as DONE LED on the board turned ON, you can press do the testing of your design On the board, set switch SW4-SW1setting to 0101 (i.e. value 5), and SW0 to 1 (up). Set Press BTN1 (Load) button on the board to load the value and then release the button [make sure that you have pressed it for about 1 second so the hardware detects it as we have 1 second delay. Observe the counting values on the LEDs on the board as well as LEDs on the front panel Press BTN0 and then release it to see that the count value becoming 0000. Press BTN2 and keep it pressed and observe that the count value does not change. Release BTN2 and observe that the counting resumes. Press BTN0 to reset the counter and when it becomes 1111 (or 15) the LED4 (tc) will be turned ON for 1 second. Note that if the count value is

greater than 15 the counter keeps counting but you will not see the tc turned ON. The counter is capable of counting up to 256 as we have selected U8 as the data type. Now, change SW0 to 0 (down) and observe the counter counting down. Also observe that the tc becoming ON when the count is 0000 (zero). Once done with the testing, click the Stop button ( execution or press BTN3 to stop the execution ) to stop the

Section 3: Testing the design using the host tester VI Procedure:

Save the VI as counter_DUT.vi Delete switch, LEDs, and all buttons except BTN3 from the block diagram, still leaving the corresponding indicators in the design In the project explorer view, right-click on FPGA Target and select New FPGA I/O In the form, expand GPIO Lines folder, select GPIO0 through GPIO15 and add them. Click OK The project explorer window will look like this

In the Block Diagram window, add FPGA I/O Node from FPGA I/O palette library Right-click on the added node and select GPIO0. Expand and resize it such that GPIO0 through GPIO3 are included in that node Connect reset, load, hold, and up/down to GPIO0, GPIO1, GPIO2 and GPIO3

In the Block Diagram window, add FPGA I/O Node from FPGA I/O palette library Right-click on the added node and select GPIO4. Expand and resize it such that GPIO4 through GPIO7 are included in that node Connect input to the Build Array instance to GPIO4, GPIO5, GPIO6 and GPIO7 (see diagram below) In the Block Diagram window, add FPGA I/O Node from FPGA I/O palette library Right-click on the added node and select GPIO24. Change its functionality to write. Expand and resize it such that GPIO24 through GPIO11 are included in that node Connect output of the Index Array instance to GPIO8, GPIO9, GPIO10 and GPIO27 (see diagram below) In the Block Diagram window, add FPGA I/O Node from FPGA I/O palette library Right-click on the added node and select GPIO28. Change its functionality to write Connect tc GPIO28 (see diagram below) The completed diagram should look like as shown below

Save the VI

Click on Run button. The design will compile. When the bit generation is completed, click OK to close the dialog box. The FPGA will be configured Right-click on My Computer in the project explorer view, select Add File, browse to the project directory and add Simple FPGA Tester.vi Double-click on the Simple FPGA Tester.vi in the project explorer view to open it View and understand the block diagram Note that Digital Writer uses DIO channel 8 through 15 [channel 15 being least significant] to write to FPGA and Digital Reader uses DIO channel 0 through 7 [channel 7 being least significant] to read response from FPGA Using proto-boarding wires physically connect BB1/BB2 and BB5 connectors in the following manner BB1/BB2 Connectors GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 BB5 Connector DIO15 DIO14 DIO13 DIO12 DIO11 DIO10 DIO9 DIO8 DIO7 DIO6 DIO5 DIO4 DIO3

Click on the drop-down arrow of the Elvis II/II+ Device Name field and select the device corresponding to the Elvis II

Change the Number of Inputs to 8 and Number of Outputs to 5 Change the Wait time to 1000 ms Click on Browse button for the Input file and add load_and_upcount_TextInputList.txt Similarly, add the load_and_upcount_ExpectedOutputData.txt for the expected output. At this stage the front panel should look similar to

The input data file is a text file which can be opened/created using any text editor. The following figure shows the content of the file

The input file describes input in order of parallel input[3] (left most bit), parallel input[2], parallel input[1], parallel input[0], up/down, hold, load, and reset (right most bit ). The output file is also a text file which also can be opened/created using any text editor. The following figure shows the content of the file

According to this output file channels DIO0 through DIO2 are automatically assigned zero, whereas channel 3 is assigned to tc (terminal count) (left-most bit), channel 4 to output bit[3], channel 5 to output bit[2], channel 6 to output bit[1], and channel 7 to output bit[0] (right-most bit). Make sure that the counter_DUT.vi is still running Click the Run button on the tester front panel. The test will be run and the result will be displayed Now change the expected output file content. Change the fourth output from 01011 to 11111 to make the test fail. Save the change Power-cycle the ELVIS and FPGA board Run the test again and notice that the tester reports it as Failed. It also reports where it failed, what was the input, what was the expect output, what was the actual output, and error light is turned ON Once verified stop the counter_DUT run, close the project, close LabVIEW, and turn OFF the NI ELVIS-II as well as the board.

Conclusion:
In this exercise you learned how to design a programmable counter using while loop and case structures. You also learned how to implement priority logic using select palette to provide necessary precedence functionality. You verified the design using DE FPGA Board and also using NI ELVIS system.