16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder AIM: The main aim of the project is to design 16-Bit Wave-Pipelined SparseTree

RSFQ Adder. ABSTRACT: In this paper, we discuss the architecture, design, and testing of the first 16bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the I T!" 1# $%&cm' %()'*1 fabrication process* "ompared to the +ogge, tone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity -at the expense of latency. and almost no decrease in operation frequency* The 16-bit adder core -without /0-to-dc and dc-to- /0 converters. has 1121 3osephson junctions occupying an area of 4*5 mm'* It is designed for the target operation frequency of 6# 789 with the expected latency of 65' ps at the bias voltage of '*5 m:* The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of ;1*4<&=1#*><*

B !C" #IA$RAM:

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

/ig? tructural diagram of the 16-bit sparse-tree adder* The carry-out -"out. is the left-most bit and to the right of it is the most significant bit of the um result -bit 15.* The right-most bit is the least significant bit -bit #.*

T!! S: @ilinx 1*'I !, Aodelsim6*2c* APP ICATI!% A#&A%TA$'S: The 16-bit asynchronous parallel adder builds upon the proven hybrid wavepipelining techniques to provide 16-bit wide processing and synchroni9ation* It incorporates an energy efficient, low complexity sparse-tree structure with very high processing rate* R'F'R'%C'S:
V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

 A* Tana$a, 8* %$ai$e, %* /ujima$i, B* Bamanashi, C* Boshi$awa,

Cagasawa, +* Ta$agi, and C* Ta$agi, D1##-789 single-flux-quantum bitserial adder based on 1#-$%&cm' niobium process,EI!!! Trans* %ppl* upercond*, vol* '1, no* 6, pp* >1',>16* %* /* +irichen$o and F* %* Au$hanov, DImplementation of novel DpushforwardE G /0 "arry- ave erial %dders,E I!!! Trans* %ppl* upercond*, vol* 5, no* ', pp* 6#1#,6#16* %* B* +idiyarova- hevchen$o, +* B* )latov, !* A* Tol$acheva, and I* %* +ataeva, DG /0 asynchronous serial multiplier and spreading codes generator for multiuser detector,EI!!! Trans* %ppl* upercond*, vol* 16, no* ', pp* 2'1,26'* * :* )olons$y and %* :* Gylya$ov, DG /0 arithmetic bloc$s for ( ) applications,EI!!! Trans* %ppl* upercond*, vol* 5, no* ', pp* '4'6,'4'6* 8* )ar$, B* Bamanashi, C* Boshi$awa, A* Tana$a, and %* /ujima$i, D(esign of fast digit-serial adders using /0 logic circuits,EI!I"! !lectronics !xpress, vol* 6, no* 11, pp* 12#4,1216*

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &