Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC AIM: The main aim of the project is to design and implement

Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC!" A#ST$ACT: In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave pipelining achieves high speed without the above limitations. !ave pipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks. This results in lower power at the cost of speed. "ybrid scheme is aimed at combining the advantages of both pipelining and wave pipelining. "ence, we proposed the design and implementation of hybrid wave pipelined #$ $!T using lifting scheme in this paper. %or the purpose of comparison, non pipelined scheme as well as the scheme with pipelining within the blocks and between the blocks is implemented. %rom the results, it is concluded that the hybrid !& is faster than non pipelined and requires less area, less clock routing complexity and lower power than pipelined.

V.Mallikarjuna (Project manager)

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#%&C' DIA($AM:

%ig' (verall block diagram of one level #$ $!T

T&&%S: )ilinx *.#I+,, -odelsim ../c. A))%ICATI&* AD+A*TA(,S: The *01 bi orthogonal filters implemented on )ilinx +(2 device using the lifting scheme with the following three multipliers' with 3! &42-, 3!42- and hybrid !& & 3! 42-. %rom the implementation results, it is verified that hybrid !& & 3! 42- is faster compared to non pipelined
V.Mallikarjuna (Project manager)

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3! 42- and is register efficient, and less clock routing complexity compared to 3! &42-. The one level #$ $!T scheme is also implemented, in A+I2s using pipelining and non pipelining. It can be extended for whybrid !& for future work.

$,-,$,*C,S: 5. -artin and ". 2hang, 6+ystem on 2hip design,7 Proc. of Intl. conf. on ASIC, pp.8#. 3. A. $raper, 9. :. 3everidge, A. &. !. 3ohm, 2. :oss, and -. 2hawathe, 6Accelerated image processing on %&5As,7 IEEE ; <=+I $esign Transactions on Image Processing, vol. 8#, no. 8#, pp. 8>/?@ 8>>8. 5. =akshminarayanan, 3. <enkataramani, 9. +. 4umar, A. 4. Aousuf, and 5. +riram, 6$esign and %&5A implementation of image block encoders with #$ $!T,7 in Proceedings of IEEE Conference on Convergent Technologies for Asia-Pacific Region (TENCON !" , vol. ?, pp. 8B8>@8B8*, 3angalore, India. 4. 4. &arhi, #$SI Signal Processing S%stems, 9ohn!ileyC+ons, Dew Aork, DA, E+A.
V.Mallikarjuna (Project manager)

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 9. Dyathi and 9. 5. $elgado %rias, 6A "ybrid wave pipelined network router,7 IEEE Transactions on Circ&its and S%stems-I , '&ndamental Theor% and A((lications) vol. /*, no. 8#, pp. 81./@811#.

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &