Automotive MCU Overview - 2012 Ap

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April 2013
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, CWare, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2013 Freescale Semiconductor, Inc.
2011 Market Share
2011 Market Share
Global MCUs1
Global Auto MCUs1
9%
21%
Freescale Shipped 360M auto MCUs (> 4/car) in 11 We are in Approx 55 million new vehicles / year
Sources: 1. IHS iSuppli, May 2012
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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2013 Freescale Semiconductor, Inc.
80% percent of innovation is electronic
?
Advanced Driver Assistance Active-Passive Safety Green Powertrain Radar / Vision Telematics Infotainment 35% 30%
E.g. Audi A8: 100 ECUs, 270MB of S/W
Impossible to comply with regulation without electronic systems

Electronic cost as % of total car cost -Automotive OEM
50%
Airbag ABS / ESP Body Electronics Multiplexing 22% Electronic Fuel Injection 10% 2.5% 5%
15%
E.g.
1950
1960
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1970
1980
1990
2000
3
2005
2010
2025?
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Integrated BCM Gateways
AFS Front Light CAN LIN
Door SLP ripple cnt Light / LED ctrl Light / LED ctrl MCU Input Gateway 32bit 176 pin Monitor SBC BCM Output (208/256) Driver W/D & Light / Safety LED ctrl MCU Door SLP ripple cnt Rear Light Input Switches etc. Output Interior lighting etc. Rear Light
Front Light AFS
Light / RF LED ctrl Rx
Comfort Features
Vehicle Networking
Safety Related

Security

Door Module Window Lift Seat Module HVAC Electric sunroof/shade Interior lighting
Central Body Control Module Central Gateways: CAN, LIN, Flexray, Ethernet, MOST
Steering column lock Steering column adjustment Seat positioning Wipers and rain sensors Lighting and light sensors Convertible top Anti-pitch power windows
Immobilizer Keyless Entry Preventing hacking and counterfeit modules
Body systems embrace a broad variety of applications inside the cabin Body systems cover the widest range of performance requirements

Small 8-bit controllers and watchdogs General purpose 16-bit controllers High performance 32-bit compute engines
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Connected
More complex Gateways with higher performance and multicore usage (Expanding memory ) Ethernet and wireless communication Personalization options driving LIN nodes
Software Integration:
Autosar: Multicore-support OS MCAL Safety: SW-routines supporting self-test (Core/Memory) Security: Cryptography algorithmic support Application-support Motor Control-library Reference designs
Safe and Secure
Functional Safety - ISO26262 Several body-apps need ASIL A/B (some C/D) Reduced ASIL-assessment effort Security/Cryptography for Gateway and BCM modules
Power management in stop and run modes AUTOSAR SW management of partial/pretended networking EC-motors, LED-lighting
Green
Cost reduction via ECU integration Electrification of the car replacing mech. components Scalability of hardware and software Auto generated code to decrease dev costs
Cost Efficient
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Today
Dynamics Sensors Brakes Steering
Future
Dampers ADAS Airbags Tensioners (Radar,Camera) Ped. Protection Multimedia/ Telematics Entertainment Navigation Driver Instruments Controls
ECU Vehicle Dynamics & Safety Torque Management
ECU ECU ECU
Driver Interface (HMI)
Body, Security Lighting

Transmission Generator
Distributed Electronic Control Units

One ECU per mechanical function- Connected by multiple CAN and LIN interfaces
Engine
Electric Motor
Seats
Mirrors
Doors
Lighting
Distributed Computing
Major computing nodes on a high performance network organized by domains which control zones
Up to 80 individual ECUs Local and proprietary network structures Increasing software complexity Increasing cabling weight Increasing ... everything
Increasing data traffic Ethernet as the backbone Central Gateway will have an Ethernet Switch Lower power: Partial/pretended networking AUTOSAR 4.0
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BCM and Gateway Door, Window, Seat, HVAC, Other Body

Motor Control, Lighting, etc.
S08
8-bit Microcontroller Families
S12
16-bit Microcontroller Families
S12 MagniV
16-bit with Analog ASSP/MCUs
Qorivva
32-bit Single-Core Microcontr. Families
Qorivva
32-bit Dual-Core Microcontr. Families
System Basis Chip (SBC), Network Interconnect High Side Switches (eXtreme Switch), H-Bridges, Switch Monitoring
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Product Lines Qorivva

32-bit Power Architecture MPC5668G/E (Fado) MPC551xS/E/G MPC56xxB/C (Bolero)
Sampling
MPC57xxC (Calypso) MPC570xB (Bolero Next) S12ZVM (Carcassonne)
Proposal Planning Execution
S12 MagniV
Integrated HV Analog + MCU
Qualified
S12ZVC (Hearst) S12ZVL (Knox)
Production
S12VR (Tomar)
S12XE S12XS S12P S12G(A)
S12ZVFP
S12ZVB (Toledo) 250nm 180nm 130nm 90nm 55nm
S12
16bit CISC
S08
8bit CISC
S08D S08E S08SG S08SC S08QD 1Q
Sampling
First Sample Date (left edge) S08RN (with TSI)

S08RNA Product Qualification (right edge) 2Q 3Q 4Q 1Q 2Q 3Q 4Q
2Q
3Q
4Q
1Q
Past
2012
2013
2014
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New
Fully AEC-Q100 qualified suitable for any automotive application with ambient temperatures up to 125C The new scalable and pin-compatible S08RN families reuses existing core, IP and tools for easy migration from existing 8-bit S08 products.
S08RN Family of MCUs integrates key features like EEPROM, TSI (touch sensing interface) and motor control FlexTimer to further reduce system costs.
Suitable for any kind of Sensor-, Actuator- or User interface-module in an automotive LINNetwork
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128K 96K 60K 48K

AW60 AW48 AW32
DV128 DV96
C C C C C
DZ128 DZ96
C C C C
DN60 DN48 DN32
250 nm 180 nm
DV60 DV48 DV32 LG32 DV16 LG16 MP16
DZ60 DZ48 DZ32 EL32
RN(A)60
RN(A)48
CAN
Hi temp
32K
SG32 AW16
RN(A)32
Proposal Planning
DZ16 EL16 SL16
DN16
Execution Production
16K
SG16
RN(A)16
First Sample Date (left edge) Product Qualification (right edge) 4Q
8K 4K Flash Size
SG8 SG4
EL8 SC4
SL8 QD4
RN(A)8
EEPROM
RNA4
Past
1Q
2Q
3Q
4Q
1Q
2Q
3Q
2012
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2013
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Key Features & Benefits:

Optional
operation on low-power 32kHz Oscillator reduces power consumption Typ. Ridd [20MHz] / Stop idd: 5mA / 1uA 6x16-bit FlexTimer PWM and analog comparator for power-conversion (DC/DC-converter, lighting, motor control, ) 16 channel Touch-Sense Interface (TSI) for implementing buttons, sliders rotary (Centerstack / Domelight / RKE...) LIN-UART & 12-bit ADC for Lin-based sensor- or I/O nodes 20mA sink on up to 8 pin reduces cost for external components Low-cost non intrusive singlewire debugging via BDM Low current Startup (500uA) on RN16/8 and RNA4/2
Features
Flash (KB) RAM (KB) EEPROM (Byte) LIN/UART SPI IIC TSI (cap. Touchsensing) ADC channel (12-bit) Comparator Flex-Timer (16-bit) Mod. Timer (8-bit) Pincount
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LIN/SCI Up to 3 SPI Up to 2
GPIO Up to 55
12Bit ADC Up to 16ch FlexTimer Up to 6+2+2ch 16b 2ch 8b Mod.-timer Analog Comparator
S08 CPU 20MHz Bus IIC Up to 1 6-Bit DAC (internal) CRC DBG
60kB 48kB 32kB 16kB 8kB 4kB 2kB
WD+RTC 12-16ch TSI Interrupt (not on RNA) RAM 4kB 2kB 512B
Flash
EEPROM 4 byte Block (ECC) 256B 128B
S08RN60/48/32
60/48/32 4 256 3 2 1 16ch 16ch 1 6ch + 2ch + 2ch 2ch 64, 48, 32
S08RN16/8
16/8 2 256 2 1 1 12ch 12ch 1 6ch + 2ch 1ch 48, 32, 20, 16 12
S08RNA16/8
16/8 2 256 2 1 1 12ch 1 6ch + 2ch 1ch 48, 32, 20, 16
S08RNA4/2
4/2 0.5 128 1 8ch 1 2ch + 2ch 20, 16, 8
Touch Sense Interface

Touch Sense Software Library

Full API Configurable Rotary, Slider, Keypad decoders Flexible combination of any electrode array on the
same application Configurable smart auto-calibration mechanisms for environment hassles Auto repeat, stuck-up key, gorilla hand and other typical HMI functions Noise rejection algorithms
Runs with minimal CPU intervention: interrupt

in the case of a capacitance variation Low Power Operation (~1-3uA) allows wakeup capability from stop-modes No need for external components Detect electrode fault (too small or too big capacitance) Compensate temperature and Supply voltage variations
Application
System Configuration and Management System Setup
Decoders
Keypad Rotary Slider
TSS Library
Key Detector
Touch Sensing Module (TSI)

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TSI Module
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IGT_1 POS_PULSE VRS
IGNCOIL
Ignition Driver
IGNCOIL
VRS Conditioning
NEG_PULSE
IGT_2
Ignition Driver
PULSE
TPS
S08RN
F/B
Solenoid Driver
CHOKE SOLENOID
Analog Input Conditioning

ETEMP PWM 50kHz to 200kHz
DC-DC Converter
POS_PULSE Configured as Input Capture requiring a 16-bit Timer. NEG_PULSE Configured as Interrupt. TPS Throttle Position Sensor, ADC resolution 10/12 bit ??. ETEMP Engine Temperature Sensor, ADC resolution 10/12 bit ??.
IGT_1, IGT_2 Configured as Output Compares requiring a 16-bit Timer. PWM Output Switching Frequency Range 50kHz to 200kHz. PULSE Output Timer to Control the Pulse of Choke Solenoid F/B Configured as Interrupt
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Manchester Encoded Data
125kHz RF Tag reader
V-reg
BAT OFF
MCU
BAT ON
Key with transponder
Network Interface
Immobilizer ECU
BAT
Enable / Disable Ignition

Network Interface
CDI / EMS
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1M 512K
C S12XE100,768 XGATE, MPU, EE to 50MHz L Up 112,144,208pin C XGATE, MPU, EE Up to 50MHz L 80,112,144pin

S12XE512,384
256K
AS12G(A)240 C S12XE256 C S12XS256 XGATE, MPU, EE CEEPROM up to 40MHz Up to 50MHz L 64, 80, 112pin L 80,112,144pin L25MHz 48,.64.100pin
S12G(A)128 S12XE128 S12XS128 CS12P128,96 C C EEPROM XGATE, MPU, EE C up to 40MHz 32MHz Up to 50MHz L 48,64,80 pin L 64, 80, 112pin L 80,112pin L25MHz 48,64,100pin
128K
64K
CS12XS64 CS12P64 up to 40MHz 32MHz 64, 80, 112pin L 48,64,80 pin L C S12P32 32MHz L 48,64,80 pin
CEEPROM 25MHz L32,48,64pin L
S12G(N)A48,64
S12G64
EEPROM 25MHz
C L 48LQFP
S12GN32
S12GN(A)32
EEPROM 25MHz 20, 32. 48pin
32K
C L 48LQFP
EEPROM 25MHz
S12GN(A)16
16K Flash Size Past

High temp (Grade 0)
L
L C A
LIN CAN DAC
EEPROM 25MHz 20, 32, 48pin
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
2012
Production
2013
Execution Planning Proposal
No X-Gate X-Gate Coprocessor

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First Sample Date (left edge) Product Qualification (right edge)

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1-3 LIN/SCI 0-1 MSCAN
1-11KB RAM
ATD 8-16ch 10 Bit (12Bit on S12GA) DAC on S12GA Timer 16b 6-8ch PWM 6-8ch 8Bit (or 3-4ch 16-Bit) 32-100 LQFP 20TSSOP, 48QFN
16-240KB Flash
0,5-4 KB EEPROM DBG INT
One scalable family for all low-end body applications 16-bit performance and convenience True EEPROM onboard Multiple SCI and SPI modules Wide operating range Vdd = 3,13 .. 5,5V 25MHz Bus speed
Device Flash RAM EEPROM Freq
240K 240K 192K 192K 128K 128K 96K 96K 64K 64K 48K 48K 48K 32K 32K 16K 11K 11K 11K 11K 8K 8K 8K 8K 4K 4K 4K 4K 4K 2K 2K 1K 4K 4K 4K 4K 4K 4K 3K 3K 2K 2K 1.5K 1.5K 1.5K 1K 1K 512B
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1-3 SPI 0-1 ACMP GPIO
S12CPU 25MHz
MSCAN SCI SPI

1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1
ATD
16c12b 16c10b 16c12b 16c10b 12c10b 12c12b 12c10b 12c12b 12c10b 12c12b 12c10b 12c12b 12c10b 8c12b 8c10b 8c12b
PWM Tim
8c8b 8c8b 8c8b 8c8b 8c8b 8c8b 8c8b 8c8b 6c8b 6c8b 6c8b 6c8b 6c8b 6c8b 6c8b 6c8b 8c16b 8c16b 8c16b 8c16b 8c16b 8c16b 8c16b 8c16b 6c16b 6c16b 6c16b 6c16b 6c16b 6c16b 6c16b 6c16b
DAC ACMP
2c8b 0 2c8b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Packages
48/64/100 LQFP 48/64/100 LQFP 48/64/100 LQFP 48/64/100 LQFP 48/64/100 LQFP 48/64/100 LQFP 48/64/100 LQFP 48/64/100 LQFP 32/48/64 LQFP 32/48/64 LQFP 32/48/64 LQFP 32/48/64 LQFP 32/48/64 LQFP 20TSSOP 32/48LQFP/48QFN 48LQFP 20TSSOP 32/48LQFP/48QFN
S12GA240 S12G240 S12GA192
25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz 25MHz
Family Member Differences
S12G192 S12G128 S12GA128 S12G96 S12GA96 S12G64 S12GA64 S12G48 S12GA48 S12GN48 S12GN32 S12GNA32 S12GN16
S12GNA16
16K
1K
512B
25MHz
19 8c10b
6c8b
6c16b
48LQFP
Note: Not all peripherals are available in all package types.
VBAT
Vreg
5V
S12GN32
1 LIN/SCI 1 SPI 2KB RAM 32KB Flash 1KB EEPROM DBG S12CPU INT ATD 10b 16ch MUX Timer 16b 8ch
2H Topology Power Stage

4mOhm
4-poles/2ph BLDC Motor
4mOhm
COP API
ACMP
A_IP_ACMP_1C_5V_TSMC18LL Features
ACMP features:
48 LQFP
GPIO
New feature implemented on GN32
supply voltage Analog input voltage range Input offset output delay time Init delay Input leakage Comp hysteresis Stop mode Input Low Pass filter
3.13V - 5.5V 0 to VDDA-1.5V* max=40mV max=0.6us (analog only) max=1us max=1uA min=3mv,typ=6mV,max=20mV CMP is off Yes, typ=10MHz cut-off
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Input / Output blocks

Communication + power supply Vreg CAN CAN P/L Watchdog Wakeup SPI
Processing block
Output blocks

High beam left High beam right Rear break left Rear break right Interior 1 and 2 Front side marker right Front side market left
High side drivers
High side drivers
Low beam right

Low beam left Center mount break lamp Fog lamp left Fog lamp right Rear, turn and hazard left Rear, turn and hazard right
SPI
S12G
LIN LIN P/L LIN P/L LIN P/L
High side drivers
High side drivers
Switch inputs Low side drivers Analog inputs Power distribution relays.
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Neutral Clutch Switch Switch

Analog voltage depending on switch status
RPM
Inputs from vehicle

Analog voltage depending on switch status RH1 RH2 GND
Switches in LH 1. Horn 2. Left Blinker 3. Right Blinker 4. Pass 5 .High Beam
LH1 LH2 GND
Switches in RH 1. Starter Relay 2. Park Lamp 3. Low beam 4. Engine Kill
LH Switch Unit
Central BCM Unit

Outputs from BCM 1. Park Lamps 2. Low Beam 3. High Beam 4. Left Flasher 5. Right Flasher 6. Horn 7. Engine Kill 8. Starter Relay
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RH Switch Unit
Advantages: 1. Reduces losses due to elimination of high current mechanical switches 2. Additional protection and diagnostics for loads. 3. Reduces required number of high current wires going into switch bar units. 4. Reduces length of heavy gauge wires. 5. Eliminates Flasher Relay, Diode logic in wiring harness required for Neutral gear indication.
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Digital Logic
S12, PWMs, Timers, SRAM, SPI, SCI, GPIO, Watchdogs, etc.
High-Voltage Analog
Low Side & High Side Drivers, Voltage Regulator LIN/CAN Phy. etc.
Non-Volatile Memory
Flash, EEPROM
Existing Low Leakage 180nm CMOS+NVM
40V UHV Devices
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Motor Control
S12VRxx (Tomar)
2 LS for relay based DC motor control
Toledo S12ZVML/Cxx (Carcassonne)

6ch-MOSFET predriver for BLDC/PMSM motor control 4ch-MOSFET preDriver for H-Bridge-driven DC-motors
S12ZVMxx (Obidos)
No PHY (PWM-control) + 6ch-MOSFET pre-driver
Troy
Stepper motor control
ASSPs
S12ZVHxx (Lumen 4W)

LCD + Gauge
Instrument Cluster
Multi-PHY companion chip LED Lighting LIN enabled CAN enabled
2Q 3Q 4Q 1Q 2Q 3Q
S12ZVFP (Lumen HVAC)

LCD
S12ZVH (Lumen 2W)

LCD + Gauge
Coco
8# LIN-PHY Companion Controller
Teck - RGB-LED
Ambient Lighting
Lichtenstein
4-5ch LED-drive (DC/DC)
General Purpose
S12ZVLxx (Knox)
S12ZVCxx (Hearst)
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
Planning
4Q
1Q
2012
With LIN-PHY With CAN-PHY No comms (PWM-control)
2013
High temp (Grade 0)
2014
Production Execution
2015
Proposal
First Sample Date (left edge) Product Qualification (right edge)
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PAD0/AN0
PAD1/AN1
EVDD
VDDA
LGND
LIN
VSSA
PS1
PT3
PT2
PS0
PT1
Hall Sensor
PAD2/AN2
PAD3/AN3
PT0/RXD0
VDDX1
PAD4
LIN
LS0
LIN Physical Interface

2 Low Side Drivers
4ch 16bit TIM
SCI 0
6ch. 10-bit ADC + 8 int. Ch.
PAD5 PL3
WL Switches
VBAT
LSGND LS1 VSSX1 VDDA VDDX1 PWM0/PS2 PWM1/PS3 SCK/PS4 SS/PS5 MODC/BKGD
4 HV Inputs
Temp Sense
PL2 PL1 PL0 VSENSE HS1 VSSX2
S12 core
512Bytes EEPROM Win Wdog
48kB / 64kB Flash
Vbat sense 2 HS Drivers VREG Vsup sense

KWP0
Altern. SCI Test Intrface
PWM 2ch 8-bit SPI SCI 1 BDM

RESET TEST
2 kB RAM
RCosc. PLL +/-1.3%
HS0 VSUPHS VSUP
Key Hall Pierce Wakeups Supp Osc.

EXTAL/PE0 KWP3/PP3 VSS XTAL/PE1 KWP4 VDDX2 XIRQ IRQ
PP2
VBAT To Hall Supply GND
VDDX1
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VREG Full Discrete

(8pin)
2+
CAN or LIN phy

(8pin)
2+
MCU or DSC
(48pin)
20+
Gate Driver
(48pin)
4 to 6 cm2 PCB space savings
Op-amps
4cm ~1 in.
Semi Integrated MCU or DSC
(48pin)
ASIC
24+ (GDU+ VREG+ LIN+ Op-amps) (64pin)
2 to 3 cm2 PCB space savings
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VBAT
+11V VSUP VSSB

BKGD
D S
BST
Reset
VDDA
VDDF
VDDX
BCTL
VSS
VDD
VSS
VSS
VLS
EVDD VCP CP
+11V 0V AMRsinAmp AMRcosAmp
XTAL
Ext Osc IRC
EXTAL
IO/ KWP0 IO/ KWP1 IO/ MISO IO/ MOSI IO/ SCLK IO/ SS IO/ RXD0 IO/ TXD0 IO/ RXD1 IO/ TXD1 IO/IOC1 IO/IOC0
BDM PLL KWU RTI Wdog
S12Z core
Vregs (5V VDD, VLS, VDD sensor)
128 kB Flash
Temp Sense
Charge Pump
VBS0 VBS1 VBS2
VHb
G P I O
Hallout
SPI SCI SCI TIM 4ch/16b MSCAN 8 kB RAM 512Bytes EEPROM GDU LIN Physical Interface 3 phase H-Bridge Predriver
HD
HG0 HG1 HG2 HS0 HS1 HS2 LG0 LG1
AMR/ GMR/ Hall Sensor
IO/ AN0_1 IO/ AN1_1 IO/ AN0_0
IO/ AN1_0
Dual 12-bit ADC 5+4ch. Ext.

(Muxd with Op-Amps)
PTU
PMF 6ch PWM
+ 8ch. Int.
Hallout
Current Sense (2 x Op-Amp)
LG2 LS0 LS1 LS2
AMPM1
AMP1
LINGND
AMPM0
AMPP0
AMPP1
LIN
AMRsinAmp AMRcosAmp
Shunt1
The pinout represents functionality. The physical pins location is not correct, and also does not reflect pin multiplexing
Shunt0
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Applications
HVAC Blower (~600W)
Customer Goals
Reduce audible noise Improve efficiency since high currents (100W ~ 0.1l/100km or 0.5mpg) Reliability since high duty-cycle Improve power efficiency
Challenges
Get maximum efficiency and lowest noise to justify extra system cost Tough space constraints
BLDC
Fuel pump (ondemand)
Electric vehicles: - A/C Compressor - Water pump (eng. cooling) DC Wipers
Replace conventional belt Reliability since high duty-cycle Power efficiency
Tough space constraints

High temperature
Drive the 2 blades independently to remove mechanical connections
Need accurate position control to avoid collision
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Key Features:
On chip 12V Vreg with Supplycapability:
LIN-PHY SCI 0 SCI 1 1 SPI 1 IIC

GPIO 1-3# 1# EVDD NGPIO
70mA total (170mA with ext. Ballast)
Pierce Osc. RCosc. PLL +/-1.3% S12Z 25MHz Bus 32KB Flash (ECC) 128B EEPROM HVI 1kB RAM V-SUPSENSE
Temp 10-bit ADC Sense Timer 16b 8ch PWM 8ch 8-bit (or 4ch 16-bit) BDM/BDC VREG for tot. supply:
70mA 170mA with ext. ballast
LIN-PHY, LIN2.1 compliant On chip RC Oscillator; trimmed to +/1,3% tolerance over full temperature range Robust 12V HVI with ADC (wakeupcapable) 1xEVDD (20mA) & 1-3xNGPIO (25mA) strength 10-bit ADC EEPROM 4-Byte-erasable (with ECC)
Other:

S12ZVL
S12ZVL
Application orientation Package Flash Memory (ECC) NGPIO (GPIO with 25mA NMOS) HVI 2nd SCI SPI IIC 10-Bit ADC ASIL generic 48LQFP 32LQFP 32/16/8 kB 32/16/8 kB 3 1 1 1 y y y y y 8ch 6ch A A
TECK
S12ZVLS
small sensors 32QFN 32/16 kB 1 1 y y 6ch A
S12ZVLA
ambient Lighting 32QFN 32/16 kB 3 6ch -
-40C .. +125C Ta 5x5mm footprint 32QFN-package ASIL-A compliancy

Digital Components MCU Core and Memories 5V Analogue Components High-Voltage Components
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Automotive Voltage
Voltage Regulator GPIO
5V Switch Bank
Wakeup
S12Z PWM LIN PHY
Backlight
Dials
LIN BUS
HVI
ADC 12-Bit
12V Switch
Digital Components MCU Core and Memories
5V Analogue Components High-Voltage Components
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Fado/Bolero 90nm Products

Integrated Gateways
MPC5668G/E
z6+z0, 116MHz, Up to 2M Flash, 598k RAM Flex, Ether, MLB, CAN, LIN
Next Generation Products

MPC5748/7/6G
z4+z4+z2, 160MHz, 3M-6M Flash, Flex, Ether, Security, MLB, USB, CAN, LIN
MPC5646/5/4C
z4+z0, 120MHz, Up to 3M Flash, 256k RAM, Flex, Ether, Security, CAN, LIN
Proposal
MPC5748/7C
z4+z2, 160MHz, 4M-6M Flash, Flex, Ether, Security, CAN, LIN
Planning
Execution Production
Triple Core Dual Core
Mid-High BCM
MPC5668E
z6+z0, 116MHz, Up to 2M Flash, 598k RAM Flex, Ether, MLB, CAN, LIN
MPC5646/5/4B
z4, 120MHz, Up to 3M Flash, 192k RAM, Flex, Security, CAN, LIN
MPC5746/5/4C
z4+z2, 160MHz, 1.5M to 3M Flash, Flex, Ether, Security, CAN, LIN
MPC5607/6/5/B
z0, 64MHz, Up to 1.5M Flash, 96k RAM CAN, LIN
MPC5746/5/4B
z4, 160MHz, 1.5M to 3M Flash, Flex, Security, CAN, LIN
Single Core
Security
Entry BCM
MPC5604/3/2/B/C
z0, 64MHz, Up to 512k Flash, 48k RAM CAN, LIN
MPC5602/1D
z0, 48MHz, Up to 256k Flash, 16k RAM CAN, LIN
Bolero Next Gen

Up to 1.5M Flash, CAN, LIN
First Sample Date (left edge)

Product Qualification (right edge)
1H
2H
1H
2H
1H
2H
1H
2H
Past
2012
2013
2014
2015
2016
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Body Control
Gateways
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36
FSL MPC574xG/C family of MCUs offers:
Advanced Communication Peripherals Ethernet, USB, SDHC, FlexRay, MOST, higher quantity of LINs, CANs, etc Improved Performance - Multicore MCUs options, increased MHz Large Flash and RAM to support increased message handling/code requirements New Low Power Unit with improved functionality in low power modes Support of Functional Safety ISO26262 process, targeting ASIL-B Family Concept Scalable HW and SW approach within MPC574xG/C family and migration path from the widely used Bolero/Fado families Availability 55nm products in design, Bolero 90nm can be used for early development today.
37
Fado
MPC5668G/E
Calypso
MPC574xG/C
Bolero
MPC564xB/C
90nm
55nm
TM
TM
HSMv2
e200z0h core @ 80MHz

Crossbar with MPU Interrupt controller (32 x HOST to HSM) Memory
Calypso HSMv2 80MHz
24KByte internal SRAM

Flash

Data: 2x 16KBytes Code: 2x 64 KBytes; 1x 16KBytes
24
Cryptographic Core (C3)

AES-128 Random Number Generator DMA functionality
TM
39
Core/ System Reset
Security Standards Main features CSE Module
Evita Low UID Crypto engine
HIS-SHE NVM is mandatory Fix function set
HIS-Medium (EVIT-Medium) Programmable by customer
EVIT-High PublicKey HASH
supported by MPC564xB/C supported by MPC5746M & Calypso
HSM Module
EVITA Security Modules

High-Level Medium-Level Low-Level UTC Clock AES-PRNG AES-128 EVITA HW-IF Internal RAM 64 KBytes Internal NVM 32+10 KBytes Internal Core 50-250 MHz Sec. Counter ECC-256 NIST FIPS GF(p) WHIRLPOOL AES based HASH
TM
40
Based on widely designed in Bolero 90nm products

Calypso
compatible with Bolero 90nm Minimizes customer development costs same pin out, same/enhanced cores/peripherals, similar tool chain
Compatibility/Scalability within the Calypso family

Like
Bolero 90nm, easy for a customer to move to a higher or lower performance device depending on their application requirements
Features
Wide
range of 55nm body MCUs that address the full range of body applications from low end simple BCMs to highly integrated Gateways Peripherals at the high end that support next gen highly integrated BCM/Gateway applications MLB, USB, SDHC, large Flash and RAM, multi-cores, security modules Devices follow the ISO26262 functional safety process, targeting ASILB systems
TM
41
TM
Security
Publicity around hacking of today's cars Customers want to prevent software from being copied OEMs want to restrict unauthorized aftermarket parts
Hi-Res Color Graphics
Cost WVGA LCD is becoming more economical Fully reconfigurable clusters moving from luxury cars to mainstream Even small cars will have color TFT
Head-Up Displays
HUD attach rates set to grow significantly Current generation systems use mechanical warping Next generation HUDs will require electronic warping in the MCU
TM
43
Safety
Rear-view camera being legislated in US Growth of panoramic camera and vision applications Internal cameras for drowsiness detection More instrument clusters with camera inputs
Graphics Tools & Software
OpenVG1.1 becoming widely used in Cluster applications for needle animation, fonts, textures OpenGL ES2.0 and beyond for high-end 3D effects Sophisticated tools and graphic design capabilities required
TM
44
Motocycle/Basic Cluster One or two gauges Basic segment LCD only Lowest component count and system cost
Low-line Cluster Two to Four Gauges Large segment LCD, or Low resolution dot-matrix LCD Low component count and system cost
Mid-/High-line Cluster Up to six gauges Medium resolution color LCD Video input from rearview camera or from infotainment system Some sophisticated graphics Strong focus on system cost
Premium Cluster Few or no gauges
Very high-resolution color LCD

Dual video inputs Very demanding animation requirements State-of-the-Art Graphics
Motorcycles
Small Cars
Compact Cars
Medium Cars
Large Cars
Luxury & SUV
TM
45
Best possible graphics performance
Premium
i.MX 6Dual i.MX 6Solo/DualLite
ARMv7 ISA
SVFXXX Halo
Optimized Graphics, high integration
High-line
MPC5645S
Low-line Cost Effective Performance

MPC5606S
Color Graphics
Pin Compatible QFPs

Corona
Lumen NG
Lowest System Cost
Basic
S12HY S08LG32
S12XHY
S12ZVH128
S12ZVHY64
2011
S08 S12 Power Cortex-A9 A15/A7 A5 A5/M4 M4
2012
Product Qual Production Proposal Planning Execution Samples Production
2013
2014
TM
46
Legacy Portfolio
Power Architecture, ARM, S12 and S08
New Portfolio
ARM, s12
ARM
i.MX
Bridge, Scale and Unify
Gap and architecture break
Halo
http://www.autosavant.com/wpcontent/uploads/2010/01/11_MyFordTouch_14_Instrument_Cluster_HR-300x192.jpg Power Corona

Architecture
Gap and architecture break
Lumen 4W
8-,16- and 32bit MCUs
32-bit MCU/MPUs based on ARM with GPUs

47
S12, S08
Lumen 2W
TM
Analog / Digital Inputs

Speed Sensor
Main MCU
PWM
Stepper Drive MC33977 Gauges
Fuel level sensor

Oil level / coolant Battery Ignition Voltage
Signal Conditioning MC33972
ADCs GPIO
S08LG
PWM LCD Driver
Audio Amp.
SCI VDD
RST
TPM / I2C
LED Backlight Driver

MC33996
Segment LCD
System Bus Connections
SBC MC33910
LIN
LEDs
TM
48

Speed Sensor
Main MCU
Stepper Drive
Fuel level sensor

Gauges Gauges Driven directly from Micro

Audio Amp.

SBC
S12HY ADCs S12XHY GPIO S12ZVH*

CAN VDD RST
PWM LCD Driver
SPI/I2C

MC33996
Segment LCD

CAN
MC33904
LEDs
TM
49

Camera Sensor(s) Speed Sensor External Memories
Main MCU
Stepper Drive
Fuel level sensor

Gauges Gauges Driven directly from Micro

Audio Amp.
ADCs PWM GPIO MPC5645S Camera input Display Control Unit CAN/LIN PWM
MPC5606S
Segment LCD

MC33996

SBC CAN MC33905 LIN
Colour TFT LCD(s)
LEDs
TM
50

Camera Sensor(s) Speed Sensor External Memories
Main MCU
Fuel level sensor

SVFXXX i.MX5 Camera input i.MX6

CAN SPI/I2C
PWM
Audio Amp.
PWM

CAN COM ICs LIN Ethernet MOST MC33902 MC33662
Power Management IC

MC33996
Colour TFT LCD(s)
Head Up Display
System Micro
S08 S12 MPC5604S
LEDs
TM
51
Performance Over 850 DMIPs Unique dual-core (ARM Cortex-A5 + Cortex-M4) architecture handles MCU + MPU tasks on single chip Rich, Compelling User Interfaces Innovative 2D-ACE and integrated OpenVG hardware acceleration reduces memory requirements for UIs Enabling Safety Features Integrated video ADC for direct connection of one or more analog cameras ensures lowest system cost and easy conformance to mandates requiring rear-view cameras Scalable Solutions Generous 1.5 MB on-chip SRAM and multiple package options scale from lowcost, basic connected radios without external DRAM up to entry-level infotainment systems with dual displays
52
TM
Todays Connected Radio

Collection of discrete ICs
Many external components: MCU, MPU, ADC, DRAM, PMIC Additional assembly steps and compromised reliability
Vybrid Automotive Solutions

Cost-optimized solution integrates: MCU + MPU Video ADC On-chip SRAM Single 3.3V supply Improved reliability, fewer components, and reduced system complexity Simple, cost-effective package
Higher total system cost
TM
53
1.
Value-added analog integration to drive down system cost

Real-Time Clock CAN PHY
Voltage Regulator
2.
Single chip provides all gaugebased basic cluster functions, including segment display capabilities
Ideal for basic segment cluster with mechanical gauges and segment display
TM
54
TM
55
Traditional MCU with Discrete Analog and Power
S12ZVH Family MCUs
Many external components Additional assembly steps Higher total system cost
Single-die solution integrate:

12V direct supply regulator Can PHY Layer Sound Generation Module Real Time Clock LCD Driver Stepper Motor Drivers Simple, low-cost package
TM
56
Ballast Transistor
5V
32 kHz 4-16 MHz
4x40 Segment LCD

OSC Internal RC OSC
LCD drive 4x40 4 x Stepper Motor Drivers (w/ SSD)
Vbat Vreg Vsup Speed Signal Conditioning
RTC
Timer
16bit x 8ch
5V
Speedometer Tachometer Fuel Level
Timer
(Input Capture) 16bit x 8ch
RPM Ignition
SPI SCI IIC
S12ZVH
GPIO
128k Flash (ECC) 4k EEPROM (ECC) 8k RAM (ECC)
Monotonic Sound Generator
Coolant Temp
Amp
12V switches (e.g.L/R/Cancel)
Vsup
PWM_2
Temperature Sensor Fuel Level Input
ADC
10-bit, 8-ch on pins
S12Z CPU
8b,4ch / 16b, 2ch
CAN CAN PHY CAN Bus

TM
57
TM
58
Halo Target Markets

Single or dual high-resolution graphics displays with mechanical gauges Also supports Head-Up displays either standalone or as part of the cluster module Single basic graphics display, dot-matrix or LCD with mechanical gauges. Corona fills in the low-end Hybrid solutions while maintaining code compatibility with 32b solutions 32b ARMv7, A5/M4 hybrid architecture for Halo and M4 for Corona Updated graphics capabilities relative to MPC5645S and MPC5606S Autosar and MQX support available RAM and Flash expansion ports for added flexibility and future-proofing
Corona Target Markets
Key Technical Characteristics

Hardware/Tools

Complete solution designs to show capability of platform quickly after sample availability Partnership with Altia to provide optimized tools for ease of use of 2D-ACE
TM
59
TM
SVFXXX Demo

MPC5606S Demo
New Demo Systems BOM Correct Form Factor Similar to End Product Extensive Use of Graphics Capabilities Portable for Field Demonstrations Easy to Use Plug it in and Go Halo and Corona will have these type of demos available shortly after sampling
TM
S12ZVHY64 Demo S12ZVH128 Demo

61
TM
62
TM
More than 3,500 people die every day in traffic-related incidents 50 million are injured every year Advanced Driver Assistance Systems (ADAS) addressing regulations in developed markets Cost-effective passive safety systems in emerging markets
Safety
TM
64
90% of these casualties occur in developing countries
Country
USA
Germany
Japan
China
India
Population
Car Park Road fatalities Death / 100k people Death / 100k cars Trend in road fatalities
306 million
251 million ~ 40,000 13.9 17.0
83 million
56 million ~ 5,000 6.0 9.0
128 million
91 million ~7,000 5.2 7.3
1,336 million
145 million ~ 90,000 6.7 61.6
1,189 million
72 million ~ 105,000 8.8 145
(*) and 50 million are injured
Source: http://www.who.int/violence_injury_prevention/road_safety_status/2009/en
TM
65
Safety-Critical Functionality
No room for error in critical safety systems
Technology has to work 100% of the time

Functional safety becoming an integral part of development process.
Built-in safety functions like self-testing and monitoring to detect and mitigate random hardware failures
ISO 26262 functional safety standard
TM
Safety
TM
66
Chassis
QorivvaTM
1st Si
Applications
High-end
Apr 13
Racerunner
2xCC & 1xLS @ 266MHz, + ACC (FFT) 2-4MB NVM -1.5MB SRAM Security*, FD CAN* El Mot timers, Ethernet Fray- 8 +4 ADC ASILB to D Mar14 2nd Si
H1/15
High End 40nm

2-4xCC & LS @ 266MHz ~8M, El Mot imers Security - FD CAN ASIL-D
Proposal Planning Execution
ESC highVDM HEV-EV
MPC567xk
280MHz 1M 2M, El Mot ctrl Ethernet- Fray
Gila
Production
Single Core Dual Core Multi Core Multi Core 40nm Dual Core 40nm
Mid-range
MPC564xL
120MHz 512k-1M, El Mot ctrl
2xCC & 1xLS @ 266MHz, 3-4M, el Mot Control Timers Ethernet-Fray-FDCAN*-Security* ASIL-D
H2-15
Mid End 40nm

1-2xCC & LS @ 150-MHz ~4M, Ethernet, F-ray Security &FD CAN ASIL-D
Jul12
Panther
1xCC & 1xLS @ 180MHz 1.5M 2.5M, el Mot Timer Ethernet-Fray ASIL-D
ESC, EPS HEV / EV
MPC560xP
64MHz 512k El Mot cotrl
H1 16
Low end 40nm

1xCC & LS @ 120MHz 1-2M, Timers, FD CAN ASIL-D
Low-end ABS, EPS low
MPC5517
S12 (X)
CC Computation core ACC Accelerator LS Lockstep core * - Proposed
< 2012
2013
2014
2015
67
2016
2017
2018
TM
Panther Airbag, EPS, ESC, VDM
Panther Gila EPS, ESC, VDM
Racerunner RADAR, ICM
Treerunner
Vision, Data Fusion
ASIL-D Dual Core LS 180MHz Mid Power High Tamb > 140C
ASIL-D Dual Core LS 266MHz or Triple Core Mid Power
ASILB & ASIL C/D Multi Core 266MHz High Power FFT Accelerator High End ADC (SD) High Dense Memory AUTOSAR 4.0 + ISO BGA 356
ASIL B & ASIL C Mixed Core 600MHz High Power GPU Video IN & Out Very High Dense Mem AUTOSAR 4.0 + ISO BGA 356 (tbc)
Advanced Mot. Ctrl

AUTOSAR 4.0 + ISO BGA 257 or 144LQFP
Advanced Mot. Ctrl

AUTOSAR 4.0 + ISO BGA 356
TM
68
RADAR / Fusion
Smart Backup
Front View
Surround View
Racerunner
266MHz, SPT FlexRay, ENET 3M 4M
Monitor 2 64MB
300MHz ICP-2 64MByte DRAM*
Caspian Treerunner
500MHz+ ICP-2 4M Flash 64MByte DRAM
64MHz ENET, Phy, MJPEG 512K
Racerunner-Lite Racerunner-Lite
200MHz, SPT-Lite FlexRay, ENET 2M 3M
Monitor 16MB
300MHz ICP-1 16 MByte DRAM
Caspian+
80MHz ENET, Phy, MJPEG, ISP 1M Flash
Adaptive Cruise Control Blind Spot Lane Change Assist Cross Traffic Alert
Distance Measurement Overlay Graphics Object Detection
Traffic Sign Recognition Object Classification Lane Departure Warning / Correction

69
360 / Birds Eye View Auto Parking Object Detection
TM
System Cost
Phase 1 2012 SOP System Optimization

FPGA FFT
Komodo
Tx / Rx
Phase 2 2015 SOP Systems Cost Reduction Through Integration

ASIL B / D FFT, Histogram (SPT) Sig Delta ADC RAM integration Dual core LS Racerunner
SPT FFT ADC DAC LS+Dual Qorivva Data RAM
ASIL-B
DDR Memory
D/A A/D
Phase 3 2017 SOP De-featuring for mass market
Tx / Rx
ASIL B FFT, Histogram (SPT-Lite) RAM integration
1. 2.
Primary focus (phase2): Improved features at lower cost Secondary focus (phase3): De-featured solution for mid range markets
Tx / Rx
System Integration
TM
70
Low Mid Range Mono Front Camera Smart Rear Camera / SVC
Distance Measurement Object Detection Pedestrian Detection Graphic Overlay
TM
High End Front Camera (Mono / Stereo)

Lane Departure Warning Blind Spot Detection Smart Headlamp Control Cross Traffic Alert Forward Collision Warning Forward Collision Mitigation High Value Adaptive Cruise Control Lane Keep Assist Pedestrian Detection (>60kph) Traffic Sign Recognition (Full)
Lane Departure Warning Blind Spot Detection Smart Headlamp Control Cross Traffic Alert Forward Collision Warning Low Cost Adaptive Cruise Control Pedestrian Detection (<60kph) Traffic Sign Recognition (Speed)
71
Treerunner Quad 600MHz

Debug
Image Processing Subsystem
ARM ARM ARM ARM Cortex A7 Cortex A7 Cortex A7 Cortex A7
Treerunner Dual 400MHz

Debug
Image Processing Subsystem
ARM Cortex A7 ARM Cortex A7
H.264 Encoder Image Signal Processor (ISP) Image Cognition CSE+ Processor (APEX-2)
DMA
CSE+ DMA DCU 2xMIPI FlexRay ENET
NEON FPU Cache
NEON FPU Cache
NEON FPU Cache
NEON FPU Cache
Monitor 2 350MHz
Debug
Image Processing Subsystem H.264 Encoder
ARM Cortex A7
H.264 Encoder Image Signal Processor (ISP) Image Cognition Processor (APEX-2)
NEON FPU Cache
NEON FPU Cache
Treerunner
DCU 2xMIPI FlexRay ENET
Cross Bar Fabric AXI
DMA
NEON
Monitor 2 233MHz
Debug
Image Processing Subsystem H.264 Encoder
ARM Cortex A7
Image Cognition Processor (APEX-2)
FPU Cache
DCU MIPI PDI ENET
Ext interfaces
QuadSPI Flash I/F
DDR3L I/F 64M LPDDR2
2M SRAM
I/O Bridge
Ext interfaces
QuadSPI Flash I/F
2M SRAM
I/O Bridge
DMA
x CAN-FD
I/O System
x LINFlex
TSENS
x eTimer
FCCU
NEON
Image Cognition Processor (APEX-2)
x ADC
x dSPI
x IIC
FPU Cache
DCU MIPI PDI ENET
Ext interfaces
QuadSPI Flash I/F
I/O Bridge
x CAN-FD
I/O System
x LINFlex
TSENS
x eTimer
FCCU
x ADC
x dSPI
x IIC

2
x CAN-FD
I/O System
x LINFlex
TSENS
x eTimer
FCCU
3
x IIC
ADC
x dSPI
Ext interfaces
QuadSPI Flash I/F
I/O Bridge
3
x IIC
Low Mid Range Mono Front Camera

Lane Departure Warning Blind Spot Detection Smart Headlamp Control Cross Traffic Alert Forward Collision Warning Low Cost Adaptive Cruise Control Pedestrian Detection (<60kph) Traffic Sign Recognition (Speed)
72
High End Front Camera (Mono / Stereo)

Lane Departure Warning Blind Spot Detection Smart Headlamp Control Cross Traffic Alert Forward Collision Warning Forward Collision Mitigation High Value Adaptive Cruise Control Lane Keep Assist Pedestrian Detection (>60kph) Traffic Sign Recognition (Full)
x CAN-FD
I/O System
x LINFlex
TSENS
x eTimer
FCCU
ADC
Smart Rear Camera / SVC

Distance Measurement Object Detection Pedestrian Detection Graphic Overlay
TM
x dSPI
TM
Freescale and CogniVue have commenced a partnership on development of products for Automotive Vision applications

Smart Rear View Front View Surround View Freescale will exclusively provide existing CV220x (code name Monitor, based on APEX IP) to automotive market Planning underway, samples currently available from CogniVue
Phase 1:
Phase 2:
Freescale have licensed next generation image cognition IP from CogniVue (APEX-2)
Plan to integrate APEX-2 array processor for future processor (Codenames Monitor 2 and Treerunner)
TM
73
Dedicated image processor for Distance Measurement and Object detection 1st generation array controller (Image Cognition Functionality)
Massive Parallelism Revolutionary data movement architecture

Imager
Monitor
ARM 926
Array SIMD
Extra high density Memory (to 16MB) Very low power (<300mW typ use case) SW enablement to provide:
Video In
Video out
16MByte DDR Memory (Stacked)
Object Detection Distance Estimation Dynamic Overlay Perspective and Lens Distortion Correction
TM
MAPBGA Cross Section

SOC 80nm LP
DRAM SOC
DRAM
74
Memory
Memory Memory Memory
CU
CU
CU
CU
CU
Memory Memory Memory CU
Memory
CU
Array Controller
Control Store Sequencer
RISC
Features
Array Processor Unit (APU) Data memory co-located within APUs Multi-channel, Stream-In, and Stream-Out DMAs Multi-ore
Benefits
Scalable and fully-programmable massively parallel SIMD processing core 96 16-bit processors in APEX-1 (up to 34Billion Ops/sec) Minimizes access to off-chip memory to maximize performance efficiency and reduce power Data transfer operations are automatically sequenced to move data in and out of APEX efficiently keeps APU fed Various hardware blocks run in parallel with APU. Bit processing acceleration blocks (not shown) and RISC CPU are used for operations that map best to serial processing.
75
TM
Memory Memory Memory CU
Production backup camera with Korean OEM Within a 1 cube this camera can do:
Perspective
correction Object detection and classification Flexible overlay and display control NTSC/PAL output
TM
76
PDK
Small form factor Low power dissipation Develop, Prototype, Demonstrate
RDK
Reference development kit to support prototype software design & demos
SDK
Differentiated libraries & licensable tool kits patented software algorithms faster TTM
Chips
APEX-based Image Cognition Processors best performance per area per power
Software development is a critical cost and factor in time to market

TM
77
Compilers supported:

GNU ARM (for primary processor) SEL (for APEX/APU) CV220X platform wth additional APEX tools Proprietary compiler (C-99 with extensions) planned for APEX-2 Comes integrated with the Eclipse IDE (Makefiles) Same ACF development environments for both CV220X and next generation Supported debuggers for the ARM are: A professional Lauterbach Trace32 JTAG debugger supported for debugging application code (for ARM debugging CV220X) Amontec JTAGkey2 Segger J-Link debugger APU Instruction Set Simulator (ISS) (Monitor) APU cycle accurate ISS and profiler (Monitor-2)
Development Environment:

Debugging:

APEX Simulation tools (PC Based):

TM
78
Motivation: Eliminate expensive screened LDVS cabling for video-based applications

Replace
with cheaper 2-wire CAN cabling, running time stamped Ethernet protocol Pilot project: Driving Assistance Application in the European OEM platform The application includes 5 / 6 cameras that are connected via Ethernet to a control unit
The project has three main goals:

1. 2.
3.
Prove the technical applicability of automotive series development process Prove the economic feasibility for Ethernet technology in an automotive domain Set up the technological and organizational environment to roll out the Ethernet technology in the automotive domain
TM
79
System Cost
Phase 1 2013 SOP Ethernet Proof of Concept

LVDS Elimination Ethernet proven in mass production Salsa
Phase 2 2015 SOP Systems Cost Reduction Through Integration

BroadRreach phy integrated through SiP (stacked die wire bond) Small low cost package (8x8mm) Cost, size, complexity reduction
Imager
Phy
+ISP
Phase 3 2017 SOP Value Added Features

Image signal processing integrated (monolithic) BroadRreach phy integrated through SiP (stacked die wire bond) MCU + Sensor bundled Caspian+
Imager
Caspian
+ISP
1. 2.
Primary focus (phase2): High level integration to save cost and footprint Secondary focus (phase3): Image signal processing integrated to save cost and power
Imager
+ISP
System Integration
TM
80
Compare the size of the connector and the actual camera !

TM
81
OPEN CL Programming. No proprietary language: Time-to-market Wide Industry Support Easy porting Development Framework (SDK & Matlab toolbox) : Environment to develop proprietary algorithms Library of functions for Radar Graphic overlay capabilities QuickStart Algorithms for Demo and jump start Simple algorithms to demonstrate capability Fast startup for Tier1 and OEM Demo Enablement Vision
OPEN CL as base language Basic function support in SDK Rapid Startup tool
Enablement Surround
Compression algorithms Ethernet driver Image signal Pre-Processing
Enablement Radar
Sign Processing Toolbox support in Matlab Safety MCAL and OS Integration Demo w/ FE sensor
TM
82
QorivvaTM
1st Si
Applications
Nov12
Matterhorn
Nov13
Proposal Cobra55 Planning Execution Production

Single Core Dual Core Multi Core
CC Computation core IOP I/O processor LS Lockstep core
Product Qual Proposal Planning Execution Samples Production
High-end
MPC5676R
2 x 180MHz 6M, eTPU2
2xCC & 1xLS @ 300MHz, 1xIOP @ 200MHz 8M, GTM
>6 Cylinder
2xCC & 1xLS @ 300MHz 8M, eTPU2+
MPC567xF
264MHz 3M 4M, eTPU2
Mar12
McKinley
2xCC & 1xLS @ 200MHz, 1xIOP @ 200MHz 4M, GTM
Apr13
Mid-range
MPC564xA
150MHz 2M 4M, eTPU2
Rainier
2xCC & 1xLS @ 200MHz 2M 4M, eTPU2+
6 Cylinder Transmission HEV / EV
MPC564xL
120MHz 1M, FlexPWM
Sep12
K2
1xCC & 1xLS @ 160MHz, 1xIOP @ 80MHz 2.5M, GTM

Feb14
MPC563xM
80MHz 768K 1.5M, eTPU2
Fuji
1xCC & 1xLS @ Up to 200 MHz Up to 2M, eTPU2+
Low-end <= 4 Cylinder
S12 (X)
50MHz 16 bit, 128k -1M, X-Gate
Mar13
Lavaredo
1xCC @ 80MHz 1.5M, GTM
< 2012
2013
2014
2015
2016
TM
83
TM

Automotive MCU Overview - 2012 Ap

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TM

2011 Market Share

2011 Market Share

Global Auto MCUs1

80% percent of innovation is electronic

Impossible to comply with regulation without electronic systems

Integrated BCM Gateways

AFS Front Light CAN LIN

Front Light AFS

Light / RF LED ctrl Rx

Immobilizer Keyless Entry Preventing hacking and counterfeit modules

Safe and Secure

ECU Vehicle Dynamics & Safety Torque Management

ECU ECU ECU

Driver Interface (HMI)

Body, Security Lighting

Distributed Electronic Control Units

BCM and Gateway Door, Window, Seat, HVAC, Other Body

Product Lines Qorivva

MPC57xxC (Calypso) MPC570xB (Bolero Next) S12ZVM (Carcassonne)

Proposal Planning Execution

S12ZVC (Hearst) S12ZVL (Knox)

S12ZVB (Toledo) 250nm 180nm 130nm 90nm 55nm

S08D S08E S08SG S08SC S08QD 1Q

First Sample Date (left edge) S08RN (with TSI)

128K 96K 60K 48K

DV60 DV48 DV32 LG32 DV16 LG16 MP16

DZ60 DZ48 DZ32 EL32

DZ16 EL16 SL16

Key Features & Benefits:

60kB 48kB 32kB 16kB 8kB 4kB 2kB

EEPROM 4 byte Block (ECC) 256B 128B

Touch Sense Interface

Touch Sense Software Library

Runs with minimal CPU intervention: interrupt

Touch Sensing Module (TSI)

IGT_1 POS_PULSE VRS

Analog Input Conditioning

Manchester Encoded Data

125kHz RF Tag reader

Key with transponder

Enable / Disable Ignition

C S12XE100,768 XGATE, MPU, EE to 50MHz L Up 112,144,208pin C XGATE, MPU, EE Up to 50MHz L 80,112,144pin

CEEPROM 25MHz L32,48,64pin L

16K Flash Size Past

EEPROM 25MHz 20, 32, 48pin

No X-Gate X-Gate Coprocessor

First Sample Date (left edge) Product Qualification (right edge)

1-3 LIN/SCI 0-1 MSCAN

1-3 SPI 0-1 ACMP GPIO

MSCAN SCI SPI

S12GA240 S12G240 S12GA192

Family Member Differences

Note: Not all peripherals are available in all package types.

2H Topology Power Stage

4-poles/2ph BLDC Motor

New feature implemented on GN32

Input / Output blocks

High side drivers

High side drivers

Low beam right

High side drivers

High side drivers

Neutral Clutch Switch Switch