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c
=1x10
-7
O cm
2
n
+
poly gate
Solid : d=100 nm
Open : d=5 nm
Fin Width (nm)
V
d
r
o
p
(
V
)
2000
2200
2400
2600
2800
3000
3200
P
e
a
k
E
l
e
c
t
r
o
n
T
e
m
p
e
r
a
t
u
r
e
(
K
)
Effect of S/D Resistance with Fin Body Width
W
fin
electron temp.
: Ohmic drop across R
sd
(W
fin
less than 50 nm)
R
sd
=R
as
+R
sh
+R
c
22
3-D Spacer Formation
Epi grwoth blocked by the Fin
spacers
Spacers completely removed
allowing for epitaxial raised S/D
formation
- Source: Intel
23
Industry Leading Performance
NMOS
Integrated CMOS tri-gate with:
1.High-k dielectrics & metal gate
2.Strain engineering for NMOS & PMOS
3.Dual epitaxial raised source/drains
PMOS
- Source: Intel
24
25
Introduction
Fundamentals of Bulk FinFETs
Modeling
Applications
Conclusions
Outline
2-D schematic view of symmetric
double-gate MOSFET.
Gate
Gate
Source
(n+)
Drain
(n+)
Fin
Body
L
ov
T
ox
W
fin
L
L
g
V
GS
V
GS
V
DS
Oxide
y
x
0
Bulk FinFET or SOI
FinFET (not shown)
Side-channel
S/D
S/D
T
FOX
A
A
Side-channel of bulk or SOI FinFETs :
DG structure key point
26
Schematic View of DG MOSFETs
27
Short-channel effect
x
m
x
m
S
D
x
ls x
ld
L
c
=L-2x
m
x
rs
=x
cs
x
rd
=x
cd
S
(a) (b)
x
cs
x
hs
G
G
T
ox
W
fin
SiO
2
SiO
2
( )
b dep hs hd
th ,SCE
ox c
qN x x x / 2
V
C L
A
(
+
=
(
(
b dep
th ,SCE FB B
ox
h
c
qN x
V V 2 1
C
x
L
| |
= + +
|
|
\ .
-
-
Charge-sharing length
hs hd
h
x x
x
2
+
=
: V
th
model of the conventional
planar MOSFETs
:DG MOSFETs
fin
0.5W
V
th
Modeling of Side-Channel (1)
28
Narrow-width effect
-
-
S
D
G
x
hs
x
hd
L
g
H
g
L
c
x
df
(a)
SiO2 SiO2
Fin
Body
xdf
H
g
G G
T
gate
T
ox
W
fin
(b)
b dep df
th ,NWE
ox g
qN x x
V
C 4 H
t
A
| |
= |
|
\ .
gate
ox
th ,s
2
dep b
d
ox
f
T
8
V ln 1
x qN
x
T
c
t
| |
= +
|
|
\ .
: an effective width
depleted by gate fringing
field
V
th
Modeling of Side-Channel (2)
V
th
Modeling of Bulk FinFETs
g
MS B
E
2e
u
| |
= +
|
\ .
b dep df
th ,NWE
ox g
qN x x
V
C 4 H
t
A
| |
= |
|
\ .
gate
ox
of
ox
T
2
C ln 1
T
c
t
| |
= +
|
|
\ .
gate
ox
df th ,woc
2
dep b ox
T
8
x V ln 1
x qN T
c
t
| |
= +
|
|
\ .
( )
b dep df
h
th ,woc FB B w
ox m g
qN x x
x
V V 2 1
C L 2 x 4 H
t
o
| |
= + + + + |
|
\ .
( )
b dep
hs hd
th ,SCE
ox m
qN x
x x
V
C 2 L 2 x
A
| |
+
= |
|
\ .
V
th
equations of bulk FinFETs based on 3-D charge sharing
SCE
NWE
: in NMOSFET with n
+
poly gate
The x
df
and the
V
th,woc
are
obtained by
solving these
equations
b dep
h
th ,SCE FB B
ox m
qN x
x
V V 2 1
C L 2 x
| |
= + +
|
|
\ .
- IEEE Trans on Electron Devices, p. 537, 2007
29
0.0 0.2 0.4 0.6 0.8 1.0
0.08
0.12
0.16
0.20
W
B
=15 nm
L=60 nm
g
m,max
Method
Proposed Model
CC Method
L=30 nm
L=190 nm
V
t
h
(
V
)
V
DS
(V)
T
ox
=1.5 nm
N
b
=5x10
18
cm
-3
n
+
poly gate
V
th0
0.0 0.2 0.4 0.6 0.8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Simulation
Proposed Model
CC Method
I
D
(
m
A
/
m
)
V
DS
(V)
n
=200 cm
2
/V-sec n
+
poly gate
W
B
=15 nm
T
ox
=1.5 nm
V
GS
=0.4 V
L=30 nm
N
b
=2x10
18
cm
-3
V
DS,sat
=0.426 V
N
b
=5x10
18
cm
-3
V
DS,sat
=0.271 V
V
th
Model Considering Drain Bias
- Jpn. Journal of Applied Physics
Verification in Double-Gate MOSFETs
30
10 100 1000
-0.25
-0.20
-0.15
-0.10
-0.05
Simulation
Model
V
t
h
(
V
)
L
g
(nm)
x
h
=20 nm N
b
=8x10
17
cm
-3
n
+
poly gate
V
DS
=0.05 V
W
fin
=10 nm
T
ox
=1.5 nm
o
W
=-0.04274 V
o
B
=-0.045 V
20 40 60 80 100 120 140 160 180 200
50
60
70
80
90
100
ideal subthreshold slop
n
+
poly gate
Simulation
Model
S
S
(
m
V
/
d
e
c
.
)
Channel Length (nm)
N
b
=5x10
18
cm
-3
W
fin
=15 nm
V
DS
=0.05 V
T
ox
=1.5 nm
N
b
=8x10
17
cm
-3
, W
fin
=10 nm
V
th
vs L
g
SS vs L
Models show a good agreement with simulation data.
N
b
=5x10
18
cm
-3
, W
fin
=15 nm
31
DC Models of Doped DG MOSFETs (2)
0.0 0.2 0.4 0.6 0.8 1.0
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
V
GS
(V)
I
D
(
A
/
m
)
N
b
=5x10
18
cm
-3
W
fin
=15 nm
T
ox
=1.5 nm
V
DS
=0.05 V
n
=200 cm
2
/V-sec
n
+
poly gate
0.0
0.2
0.4
0.6
0.8
1.0
Simulation
Model
I
D
(
m
A
/
m
)
V
th
=0.1297 V
L=30 nm
L=190 nm
V
th
=0.1899 V
0.0 0.2 0.4 0.6 0.8
0
2
4
6
Simulation
Model
I
D
,
d
r
i
f
t
(
m
A
/
m
)
V
DS
(V)
N
b
=5x10
18
cm
-3
n
+
poly gate
W
fin
=15 nm
V
GS
=0.4 V
T
ox
=1.5 nm
n
=200 cm
2
/V-sec
L=30 nm
V
DS,sat
=0.274 V
V
DS,sat
=0.679 V
V
GS
=0.8 V
N
b
=5x10
18
cm
-3
, W
fin
=15 nm, T
ox
=1.5 nm,
n
=200 cm
2
V
-1
s
-1
I
D
vs V
GS
I
D
vs V
DS
Models show a good agreement with simulation data.
32
DC Models of Doped DG MOSFETs (3)
33
oxide
Si substrate
Gate
Body
Wsc
Ws
Wtc
Wtc
channel
Wsc
Ws
Hg
xh
body
Wfin
Gate
Tox
r
xdep
Wc
(a) (b) (c)
(a) Schematic 3-D view for considering the
corner effect
(b) Cross-sectional view of the fin body
with 90
o
corner
(c) Cross-sectional view of the fin body
with half-circle corner
Schematic Views for Considering Top Corner
Effect
33
h
2 x
1
3 L
( )
,
'
0.5
2
2 1
3
c b fin
h
FB B
ox
th c
q N W
x
V
C
V
L
o
| |
= + +
|
\ .
V
th,s
model for side-channel with a fully depleted fin body
V
th,c
model for corner-channel with a fully depleted fin body
| |
= + + + |
|
\ .
SCE & NWE
Side-channel
SCE NWE
Electric
field
(
(
|
|
.
|
\
|
+
=
b si
b b
t
x
q
kT t x qN
x
|
|
c
2
cos ln cos ln
2
8
) 4 (
) (
2 2
( ). tan
4
2
|
c
|c
c
ox b
ox si
ox
ox b b
fb gs
q t
kT t t t qN
V V +
. 2
2 /
0
) (
} }
c
c
=
d
s
b
f
t
kT
q
i
f
g
n d
e qn d
L
W
I
|
|
|
|
40
Introduction
Fundamentals of Bulk FinFETs
Modeling
Applications
Conclusions
Outline
First SRAM Application of Bulk FinFET
41
Bulk FinFET Control planar FET Nano width planar FET
Inverter
schematic
SNM Comparison
- IEDM, p.27, 2003
SEM
Top
view
- IEEE Trans on Electron Devices, p.481, 2006
Si
SiO
2
S
i
N
G
a
t
e
P
o
l
y
-
S
i
S
i
F
i
n
-1.00 -0.75 -0.50 -0.25 0.00 0.25
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
Gate Voltage (V)
Triple Gate PMOSFET, Vds =-0.1 V
Triple Gate PMOSFET, Vds =-1.1 V
Planar PMOSFET, Vds =-0.1 V
Planar PMOSFET, Vds =-1.1 V
V
BS
= 0 V
-2.5 -2.0 -1.5 -1.0 -0.5 0.0
0.0
-1.0x10
-5
-2.0x10
-5
-3.0x10
-5
-4.0x10
-5
-5.0x10
-5
-6.0x10
-5
-7.0x10
-5
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
Drain Voltage (V)
V
BS
=0 V
Solid : Triple Gate PMOSFET
Dashed : Planar PMOSFET
- IEEE Electron Device Letters, p. 798, 2004
Bulk pFinFET in a SRAM Cell
SEM View and I-V Curves of pMOSFET
SEM view
I
D
-V
GS
curves
I
D
-V
DS
curves
42
World 1
st
Saddle MOSFET for DRAM Cells
Si sub.
S/D
SiO
2
Fin body
Gate A`
A
B
B`
- IEEE Electron Device Letters, p. 690, 2005
A A`
B B`
x
j S /D
Gate
insulator
G
a
t
e
S /D
L
g
Gate
insulator
Gate
S iO
2
S i sub.
W
fin
L
ov_ s ide
Local
doping
-0.3 0.0 0.3 0.6 0.9 1.2 1.5
10
-16
10
-14
10
-12
10
-10
10
-8
10
-6
10
-4
Saddle u
m
= 4.71 V
Recess u
m
= 4.17 V
V
DS
=
0.05 V 1.5 V
Saddle
Recess
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
Gate Voltage (V)
L
g
=12 nm W
fin
=20 nm T
ox
=3.5 nm
Recess depth=50 nm
x
jS/D,LDD
=21 nm
x
jS/D,HDD
=33 nm
Schematic View and Comparison of I-V Curves
Saddle Recess
SS 69.5 132
DIBL 21 170
Schematic view
- Korea/USA patents
43
Summary
Brief introduction
Fundamentals of Bulk FinFET
- Nearly the same scalability and performance as those of SOI
FinFET, and has several advantages
- Body shape, temperature, back-bias, S/D resistance, and speed
- Design guideline on body doping and width
Model explains very well the behavior of V
th
, internal physics, and
I-V of double/tri-gate bulk FinFETs
Bulk FinFETs could be applied to SRAM, low-power logics, and be
modified to DRAM cell
44