DESIGN OF HIGH SPEED DIGITAL FILTERS FOR DSP APPLICATIONS

Dr. D.venkat Reddy, professor,

MGIT, Hyderabad dasari_reddy@yahoo.com

Abstract: Optimized filter design is an area of interest from long time. Due to recursive operation of arithmetic processing, the resource overhead in real-time implementation is a constraint. Though various approaches were developed in past, they are constrained with high resource overhead or slow processing speed. Wherein applications, where speed is more concerned the resource overhead and intern power consumption is rising. To minimize the resource utilization with high speed coding a Multi level logic based processing approach to digital filter design is proposed. The proposed logic is observed to perform relatively faster in processing than the bi-level filter operation.
Keyword: Filter Design, High speed operation, Resource overhead, multi valued logic

I. INTRODUCTION Digital filter Design has been a research area from long time. The optimal design of digital filter wrt. Resource requirement and computational efficiency is the prime requirement of such design. Digital filters are used in the area of Digital signal processing. The area of Digital Signal Processing has experienced tremendous growth over the last two decades primarily due to dramatic improvements in Integrated Circuit (IC) process technology. Many techniques are being developed to find ways to optimize the chip packing densities for efficient design of digital filter. One promising approach is the use of Multiple-Valued Logic (MVL). MVL coding makes use of more than two levels to represent individual signals. Hence a 4level MVL signal line can carry two binary signals while a 8-level MVL signal can carry 3 binary signals. Techniques like this can cut metallization and pin-out requirements to one-third of what would be required in a binary circuit. In the area of Digital Signal Processing considerable demand exists for compact, high-speed real-time digital filters for use in radar, communications, and image processing. However, available real-time digital filters are often too slow, too costly, too complex, or require too much power. Several techniques have been proposed in literature to achieve high performance and low power implementation of digital filters [3]. For the modeling of digital filter for high speed operation in [1] a shared multiplication approach is developed. The approach is focused towards higher speed of operation but at the cost of computation overhead. In [4] a VLSI

architecture focusing on resource consumption overhead on computation is tried to reduce. Though an optimized approach for designing digital filter for low power consumption is suggested, the processing efficiency could be effectively improved if the processing speed is also increased. To achieve the objective of faster processing in this paper a novel methodology of using multi valued processing unit for the constituting elements of a Digital filter is proposed. The rest of the paper is organised with section 2 outlining the approach for defining the concept of digital filter. The digital modeling of such a digital filter is outlined in section 3. A digital modeling approach to the functional unit of a filter unit is presented. The proposed multilevel operational unit for MAC operation is presented in section 4. The observation result obtained for the developed system is outlined in section 5, with the conclusion outlined in section 6. II. DIGITAL FILTER Analog filters are continuous-time systems for which both the input and output are continuous-time signals. Digital filters are discrete-time systems whose input and output are discrete-time signals. Digital filters are implemented using electronic digital circuits that perform the operations of delay, multiplication, and addition. Analog filters are implemented using resistors, inductors, capacitors, and, possibly, amplifiers. The values of these analog components can drift over time and their precision is limited. In addition, especially when filtering takes place at low frequencies, inductors are often large and heavy. The multiplier coefficients of digital filters are established by the circuitry and do not drift. The precision of the multiplier values can be made as large as desired by increasing the complexity of the circuitry. Digital filters can be implemented using integrated circuits so that the per unit cost of digital filter construction is less than a comparable analog filter. Tolerances and accuracy considerations are important factors for both analog and digital signal processing. Digital signal processing provides better control of accuracy requirements. Wide tolerances in analog filters make it extremely difficult for a system designer to control the accuracy of an analog signal processing system. A system designer has much better control of accuracy of digital systems in

terms of word length, floating-point versus fixed-point arithmetic, and other similar factors. These are the major advantages of digital filters. High-level modeling tools provide the ability to build and simulate ideal models. Once proper validation is complete on these ideal models, the user can then migrate to lower levels of abstraction until an actual real world model is designed. High-level modeling tools are the epitome of the top-down design concept in which design first takes place with the basic functional knowledge of a system. With each level of abstraction, validation is performed. High-level modeling tools are just beginning to be used throughout industry and their application is continually growing especially in the DSP area where many modes of communications are expanding. High-level modeling tools and validation significantly address this complex expansion by introducing an ideal representation of a complicated network. A high-productivity environment is needed to support development from system definition and algorithm development to implementation and verification. An important key element deals with high-level modeling and analysis tool sets. Digital filters are discrete-time systems. A discrete-time system is essentially an algorithm for converting an input sequence into an output sequence. The input signal x(n) is transformed by the system into a signal y(n), and is expressed by the general relationship between x(n) and y(n) as follows: y(n) H[x(n)] (1) The symbol H denotes the transformation performed by the system on x(n) to produce y(n). Figure 1 graphically illustrates the mathematical relationship of Equation 1.

evaluate the output coefficients. operation logic is as shown below.

Filter coefficients f(i) Input coefficients x(i) Multiplier Adder

The

recursive

Convolved output y(i) Shifter

Fig 2: realization of recursive MAC operation Before passing the data to filter bank the fifo logic realized stores the data in asynchronous mode of operation, operating on the control signals generated by the controller unit. On a read signal the off-centered data is passed to the buffer logic. The fifo logic realized as shown below.
din rst Rd/wr (16 x 16) float notation Fig 3: realization of 16 x 16 FIFO logic for coefficient interface The obtained detail coefficients are down sampled by a factor of two to reduce the number of computations intern resulting in faster operation. To realize the decimator operation comparator logic with a feedback memory element is designed as shown below. clk rst Index comparator Fifo dout

Index (i)

Memory unit Filtered coefficient

Down sampled coefficients

Figure.1. Block diagram representation of a discretetime system The type of discrete-time system focused upon by this research is linear, time-invariant (LTI). A linear system is defined in the following manner. If x1(n) and x2(n) are specific inputs to a linear system and y1(n) and y2(n1)) are the respective outputs, then if the sequence ax1(n)+bx2(n) is applied to the input, the sequence ay1(n)+by2(n) is obtained at the output, where a and b are arbitrary constants. In a time invariant system, if the input sequence x(n) produces an output sequence y(n), then the input sequence x(n-n0) produces the output sequence y(n-n0) for all n0. III. DIGITAL MODELING The filter logics are realized using MAC (multiply and accumulate) operation where a recursive addition, shifting and multiplication operation is performed to

Fig 4: architecture for decimation by 2 logic The proposed system is realized using VHDL language for its functional definition. The HDL modeling is carried out in top-down approach with user defined package support for floating point operation and structural modeling for recursive implementation of the filter bank logic. For the realization a package is defined with user defined record data type as type real_single is record sign : std_logic; exp: std_logic_vector(3 downto 0); mantissa: std_logic_vector(10 downto 0); end record; The floating notation is implemented using 16 bit IEEE-754 standards as presented below.
Sign. (1) Exp. (4) Mantissa (11)

The floating-point addition, multiplication and shifting operation are implemented as procedures in the user defined package and are repeatedly called in the implementation for recursive operation. The procedures are defined as; procedure shifftl (arg1: std_logic_vector;arg2: integer;arg3 :out std_logic_vector); procedure shifftr (a:in std_logic_vector; b:in integer;result: out std_logic_vector); procedure addfp (op1,op2: in real_single;op3: out real_single) ; procedure fpmult (op1,op2: in real_single;op3: out real_single) ; for performing the convolution operation, filter coefficients are defined as constant in this package and are called by name in filter implementation. lpcof0=('1',"0100","00001001000"); lpcof1=('0',"0100","11001010111"); lpcof2=('0',"0110","10101100010"); lpcof3= ('0',"0101","11101110100"); hpcof0= ('1',"0101","11101110100"); hpcof1=('0',"0110","10101100010"); hpcof2=('1',"0100","11001010111"); hpcof3=('1',"0100","00001001000"); using the above definitions the filters are designed for high pass and low pass operation. The recursive implementation is defined as; for k in 1 downto 0 loop old(k):=shift(k); fpmult(old(k)(0),hpf(k+1),pro(k)(0)); proper(j,k):=pro(k)(0); addfp(acc(k)(0),pro(k)(0),acc(k)(0)); acer(j,k):=acc(k)(0); shift(k+1):=shift(k); end loop; for the evaluation of the implemented design the test vectors are passed through the test bench generated from Matlab tool. The continuous output of secondary side transformer obtained after impulse test are discretized using matlab tool where each coefficient is converted to 16-bit floating notation and passed to the test bench for HDL interface. The coefficients obtained from the filter bank after convolution is then compared with the results obtained from the matlab decomposition for accuracy evaluation. IV. MULTI VALUED LOGIC APPROACH The operational speed can be improvised by the design as in the case of operating of the coefficients for filtration of 2 levels for multilevel operation. In this paper, a unit of multi-level adder and a multiplier is used to achieve this goal. A quaternary addition operator for this operation is developed. Quaternary logic in addition can be done in many ways. The numbers in the quaternary logic may be added directly

or in numbers. Binary results of addition can be displayed in quaternary logic after conversion. Hence quaternary to binary converter is required in the beginning. Binary to quaternary converter is used to display the result in quaternary logic. In [18] modulo-4 addition is introduced, without the hardware for implementation of carry. In this paper proposed half adder has hardware for carry also. Two bit natural representation of binary logic is used for each quaternary number and addition is performed in binary itself with only 4 gates. Figure 5 and 6 explains the logical diagram of quaternary half adder logic. The X and Y are quaternary numbers which are converted to 2 bit binary numbers using quaternary to binary converter [19]. X0, X1 are the two bit binary representation of X, where as Y0 and Y1 are the two bit representation of quaternary number Y. In table 1, S1 and S0 are the result of addition in binary and S is in quaternary because binary to quaternary converter is used for conversion. C1 and C0 are in binary. Sum generator circuit is shown figure 5. X0, X1 are the binary representation of the quaternary number X, and Y0 and Y1 are the two bit representation of quaternary number Y. S0 S1 are the outputs of sum generator block which is in binary. Minimal functions have been obtained from the Karnaugh diagrams for the tables shown in table 1 and then simplified as much as possible using all possible gate types.

Table I: Quaternary table for the multi level adder Minimal functions obtained from the minimal polynomials extracted from the Karnaugh diagrams are shown below.

Sum generator in figure 5 is designed using these two expressions. This circuit uses 3 binary XOR gates and one binary AND gate. Depth of net is maximum of two gates. Depth of net is nothing but the number of gates between input and the output.

Figure 5: Sum generator circuit Carry generator circuit is shown figure 6. X0, X1 and Y0 Y1 are the input to the block. Co C1 are the outputs of the block. This circuit is designed by the expression obtained from the Karnaugh diagrams for the operational results of a half adder logic, and then simplified as much as possible using all possible gate types. C0 = x1 y1 + x0 y0 (x1 + y1) and C1 = 0 The circuit contains two binary OR gates and three binaryAND gates. Depth of the net is three.

Samples Considered 0------------------- - 0000000000000000 -3.0518e-05--------1000110000110101 -3.0518e-05-------1000110000110101 0------------------ - 0000000000000000 -6.1035e-05-------1000010000110110 0------------------ - 0000000000000000 -6.1035e-05-------1000010000110110 -7.1553e-05-------1000011001001111 -6.1035e-05-------1000010000110110 -6.1035e-05-------1000010000110110 -7.1553e-05-------1000011001001111 -7.1553e-05-------1000011001001111 -7.1553e-05-------1000011001001111 0----------------- - 0000000000000000 -7.1553e-05-------1000011001001111 -6.1035e-05------1000010000110110 -7.1553e-05-------1000011001001111 -3.0518e-05------1000110000110101 -6.1035e-05-------1000010000110110 -3.0518e-05------1000110000110101 -6.1035e-05-------1000010000110110 0---------------- 00000000000000000

Figure 6:Carry generator circuit A basic Quaternary to binary converter uses three down literal circuits DLC1, DLC2, DLC3 and 2:1 multiplexer. Q is the quaternary input varying as 0, 1, 2 and 3 which is given to three DLC circuits. The binary out puts thus obtained will be in complemented form and are required to pass through inverters to get actual binary numbers. the observation for a developed system is as outlined below. V. SIMULATION RESULTS For the evaluation of the suggested design methodology a analog signal is taken and processed, the observations obtained are as illustrated below,

figure 8: Plot for the considered input signal sample

Fig 7 Test signal sample for observation

Figure 9 Simulation result for the implemented MVL filter design Figure 9 shows the simulation result obtained for the implemented design on consideration to the signal samples considered as shown above. The simulation result shows signal tdata as the temporary signal used to pass the data from input buffer to the filter bank. Signal fdata carries the data from filter bank to each filter where the input data get convolves with the filter coefficients passed from the package as given above. Control signal c_0,c_1, c_2,c_3,c_4 are the control signal generated from the controller unit for the controlling of the filter bank operation. Signal din shows the input data fed to the module. The signal is defined as a record type with 1st bit as sign bit next 4 bits as exponent bits followed by 11 bits as mantissa

bits. Signal clk shows the system clock fed to the module for the synchronization operation. The signal clock is passed to each filter bank for the synchronous operation

Fig 10 Simulation result for the implemented MVL filter design (cont.fig 9) The simulation result shown above shows the global signal reset rst passed to the system. The system is considered to be active low with the system getting activated in the lower value of the reset signal. On the initialization of the system the system get reset by applying reset as high on the first clock pulse. Under reset condition all the signals get cleared. Control signal start is passed to the system as enable signal making the system enable whenever the signal goes high. Control signal read is used for reading of the data stored into input-buffer. On the rising value of read signal the content of the input buffer is read and passed down to filter bank for further processing. Signal sfac1, sfac2, sfac3, sfac4 shows the scale-factors obtained for the sub-band samples. Signal ebank1, ebank2, ebank3, ebank4 gives the energy content of each sub-band sample obtained after the decomposition. The sub-band sample energy gives the energy spectral of the sub-band samples.

Fig12 Simulation result for the implemented MVL filter design Figure shows the input values passed to the sub-band module. The inputs are passed to the module in Floating point Excess-7 notation. The system is passed with a clock of 100Mhz system application frequency with reset signal low as the system considered being active low. The Signal start and read is fed high for making the system enable and to read the data from the buffer element. The result shows the scale factor obtained for each sub-band. The signal det1,det2,det3 and app3 gives three detailed coefficients and approximate coefficients for the input signal. Each sub-band constitute of 9 sub-samples for every packet of the data burst. The ebanks gives the energy values of each resolution sample.

Fig 11 Simulation result for the implemented MVL filter design (cont.fig 10) Figure 11 shows the simulation result for the implemented design under processing. The figure shows the signal values carried from the input buffer to the filter input via the signal tdata. The proposed design decomposes the signal into four distinct resolution.Thus four unique temporary signals are used for the transfer of data to the filter bank. Signal fdata shows the data transferred to filter module for the processing. Sdata shows the sub-sampled data obtained for each subband.

Fig 13 Simulation result for the implemented MVL filter design Figure 13 shows the overall scale factors, detail coefficients and approximate coefficients for every packet of the signal samples. The scale factors obtained show the maximum values of the sub-band samples obtained under each subband. The energy for the samples are calculated as E=square (Magnitude of each sample). The elements of the detailed coefficient matrix (det1) show the samples lying in the higher frequency range from 8-4KHz. The second sub-band shown by (det2) gives the coefficients lying in the range of 4-2 KHz ranges. Det3 gives the sub-samples with a frequency of 2-1KHz and app3 matrix shows the approximate coefficients lying in the range of 1-0KHz ranges.

Fig 14 simulation result for the reconstructer module Fig 18 logical placement of proposed design targeting to Xc2s50e-ft256-7 Figure shows the logical placement of the implemented design on to the targeted FPGA (Xc2s50e-ft256-7). The figure shows the logical resources used by the Logic implemented for the implemented design for one CLB. The basic elements used for the implementation were LUT and Buffer elements as shown in figure.

Fig15 simulation result for the reconstructer module (cont.) The Decoder performs an in band addition of these segregated subband coefficient to regenerate the processing coefficients. The decoded coefficients are then plotted for a comparative observation of the two signals. The obtained reconstructed signal is shown in figure 16.

Fig 16 Reconstructed signal after decoding It is observed that the retrieved signal after decoding is same as the processing signal. This comparative result illustrates the accuracy of the designed system. For the real time realization of the suggested approach, the defined design is targeted to Xilinx FPGA device. The implementation observations for the designed system are presented below.

Fig 19 Floor planning of the implemented design to the targeted FPGA (Xc2s50e-ft256-7) Figure 19 shows the floor planning of the implemented design on to the targeted FPGA (Xc2s50e-ft256-7). The figure shows the logical net connection between the two CLB and the IO buffer used. The interconnects obtained shows the path covered for the logical mapping of the resources for data transfer for the operation.

Fig 17 Logical routing of the implemented wavelet decomposing module targeting to Xc2s50e-ft256-7 Figure 17 shows the logical routing of the implemented design targeting on to Xc2s50e-ft256-7 FPGA of virtex family. The routing is carried out on Xilinx FPGA editor. The result obtained shows the real time FPGA interconnection of logics connected inside the FPGA.

Fig 20 Bottom Package View after implementation for the Target FPGA (Xc2s50e-ft256-7) Figure 20 shows the bottom view of the targeted Virtex FPGA ((Xc2s50e-ft256-7) this package view is consisting of the power supply pins (VCC), the ground (GND) the dedicated lines used for data transfer and available pins for other applications. Maximum Frequency for 2-Level operation : 177.501MHz Minimum input arrival time before clock: 9.656ns Maximum output required time after clock: 6.366ns Design Statistics # IOs : 105 Cell Usage : # BELS : 1205 Maximum Frequency of operation for MVL-Filter: 354.114MHz Minimum input arrival time before clock: 4.666ns Maximum output required time after clock: 2.126ns

Design Statistics # IOs : 105 Cell Usage : # BELS : 705 a comparative evolution of the developed system on various PLD device is carried out and the observations obtained are as illustrated below,
Device Xc2s50e-ft256-7 Xc2vpx70ff1074-6 Xc2v1500bg575-6 Logical usage 705 689 700 speed 354.114MHz 311.2MHz 378.55MHz Power consumed 22.34mw 21.89mw 33.23mw

Table I: Observations for various PLD devices for the proposed approach VI. CONCLUSION This paper outlines a design methodology for the design process of digital filter for signal processing in digital domain. The process of filter designs approach using Multi level design for an analog data is presented. A filter approach for analog signal is developed to illustrate the usage of proposed design in HDL modeling. The proposed design implements a general purpose FIR filter system which gives rise to accurate decomposition of the signal into resolutions. for the developed approach it is observed that with the usage of Multivalued logic operation n the processing sped of the overall system in real time increases as compared to the conventional 2 level logic.

10]. J.Bhaskar,AVHDL primer Pearson education,2004. [11] F. Keinert, Wavelets and Multiwavelets, Chapman/CRC, 2003. [12] John F.Wakerly Digital Design Pearson Education 2004. [13]. Rafael C. Gonzalez, Richard E. Woods Digital Image Processing Prentice Hall; 2nd edition, 2002. [14] Ali N. Akansu, Paul R. Haddad, Multiresolution Signal Decomposition, Second Edition: Transforms, Subbands, and Wavelets, Academic press 2 edition, 2000 [15] Lokenath Debnath, Wavelet Transforms and Their Applications, Birkhuser; 1st edition , 2001. [16] C. Burus, et al. A Wavelet Tour of Signal Processing, Third Edition: The Sparse WayAcademic Press; 3 edition, 2008. [17] Shoab Ahmed Khan, Digital Design of Signal Processing Systems: A Practical Approach, Wiley, 1st edition, 2011. [18] F. Wakui and M. Tanaka, Comparison of Binary Full Adder and Quaternary Signed-Digit Full Adder using High-Speed ECL, International Symposium on Multiple Valued Logic, pp. 346-355, 1989. [19] Vasundara Patel K.S., K.S. Gurumurthy, Arithmetic operations in multi-valued logic, International journal of VLSI design and communication system (VLSICS), vol.1, no.1, pp. 21-32, March 2010.

ABOUT THE AUTHORS D. Venkat Reddy was born in India in 1966. He received his B.Tech and M.Tech degrees from Nagarjuna University, Guntur, India and J.N.T.U., Hyderabad in 1989 and 1996 respectively. He is currently working as Professor in Department of Electronics & Communication Engineering, Mahatma Gandhi Institute of Technology, Hyderabad. His main research interests are multivalued logic, Digital Design. He is a member of IEEE Signal Processing Society and Computer Society, member of IETE and member of ISTE. He completed his Ph.D recently from JNTU Hyderabad

VII. REFERENCES
[1]. Taher, Mohamed, Esam El-Araby, Abhishek Agarwal, Tarek ElGhazawi, Kris Gaj, Jacqueline Le Moigne, and Nikitas Alexandridis, Effective Implementation of a Generic Wavelet Filter on a Hybrid Reconfigurable Computer, 2003 MAPLD International Conference in Washington, D.C., 2003. [2]. Donoho, D.L.: Interpolating wavelet transforms. Tech. Rep., Dep. Statistics, Stanford Univ. (2002). [3]. Hae Kyung Seong and Kang Hyeon Rhee "Subband image encoder using discrete wavelet transform", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, 2004. [4]. Abdullah Al Muhit, Md. Shabiul Islam and Masuri Othman VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression 2nd International Conference on Autonomous Robots and Agents, 2004. [5]. N. J. Fliege, " Multirate Digital Signal Processing: Multirate Systems - Filter Banks Wavelets ", Wiley , 2000 [6]. A. Nosratinia, G. Davis, Z. Xiong, and R. Rajagopalan, ``Subband image compression,'' Wavelet, subband and block transforms in communications and multimedia, A. Akansu and M. Medley, eds, Kluwer, 1999. [7]. Ali N.Akansu, Mark J.T.Smith, "Subband wavelet transforms design and application", Kluwer academic publishers. 1996. [8]. S. Allen Broughton, Kurt M. Bryan " Discrete Fourier Analysis and Wavelets: Applications to Signal and Image Processing WileyInterscience; 1st edition , 2008 [9]Raguveer M.Rao, Ajit S. Bopatikar Wavelet transforms introduction to theory and application, Addison-Wesley, 2001.