IEEl TRANSACTIONS ON EDUCATION, VOL 36 , NO.

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Noise Margin Criteria for Digital Logic Circuits

John R. Hauser, Fellow, IEEE
,Lbstract-The concept of noise margin is very important in tht design and application of digital logic circuits. Most engineers reiilize that is it in some way related to the transfer characteristics of inverter circuits and most textbooks have some discussion of noise margin as related to different logic families. However, most textbook descriptions of noise margin are very incomplete and in m;i ny cases both contradictory and misleading. This discussion reyiews the noise margin issue, discusses many different criteria wti ich have been used to characterize logic gates and discusses tht- standard treatments of noise margin in typical textbooks. Finally, a noise margin criteria is proposed as a replacement for thv standard textbook approaches.

I. INTRODUCTION HE first detailed publications dealing with noise margin and its relationship to logic gate transfer characteristics appear to be those of Hill in 1967 and 1968 [l], [ 2 ] . His diicussion is very good and should be read by anyone intere.ted in noise margin and noise immunity problems. About 1 [ 1 years after Hills work, a series of papers appeared [3]-[6] dt scribing different approaches to dealing with noise margin atd proposing many methods of defining a noise margin criteria. This work was somewhat unified in 1983 by Lohstroh [;] who showed that most of the newly proposed noise margin criteria were all equivalent. More will be said about this e; rly work later, but it appears to be mainly ignored by ci intemporary textbook authors in favor of more questionable aiid less complete discussions of noise margin concepts. The concept of noise margin for a logic family is simple, blit there are very subtle implications and restrictions. If one h i s a logic gate, an invertor for example, which satisfied the rt lationships

Input Voltage (V)

Fig. I .

Illustration of logic levels 1~ I L I. 1 ~ 1>H . and 1b~ along wit11 one possible inverter transfer characteristic.

the unshaded area, such as the solid curve, will have noist: margins at least as good as given by (4) and (5). For positivi: noise margins, the ordering of the voltages will be as given in the figure, i s . , VOL(output low) < VIL(input low) < VI,[ (input high) < VOH (output high). It is thus relatively easy to determine if a logic family satisfies a given set of logic leve , and noise margin relationships by seeing if all the transfer characteristics fall within the required voltage ranges which would be the unshaded area in Fig. 1. If one wants definitions and noise margins which are valid for some temperature range or statistical variation in transfer characteristics, then all characteristics must fall within the required unshaded area of a id Fig. 1. To accommodate a range of characteristic curves, the VIH > VIL (3) logic levels must typically be shifted at the expense of the stated noise margins. t ien one can define high and low state noise margins by the The inverse of the problems shown in Fig. 1 is less c efinitions straightforward. This is the problem of given a logic family or a transfer characteristic, what is the set of optimum logic11 N M H = VOH - VIH (4) levels and the corresponding optimum or worst-case noise N M L = VIL- VOL. ( 5 ) margins? This is a problem addressed, to some extent, by most 7ltese relationships can be graphically illustrated as in Fig. 1. modern textbooks on digital electronics. It is an important imy invertor transfer characteristic H ( V ) which falls within question and concept since not all logic families have the same noise margins, and the relative magnitudes of the noisie margins are important in many applications.
Manuscript received July 1991. The author is with the Electrical and Computer Engineering Department, IJorth Carolina State University, Raleigh, NC 27695. IEEE Log Number 9211752. At this point the use of the terms optimum and .worst-case ire undefined and therefore somewhat unclear.

0162-8828/93$03,00 0 1993 IEEE

lEEE TRANSACTIONS ON EDUCATION, VOL. 36, NO. 4, NOVEMBER 1953

I
0
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I
VI
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Input Voltage. (a)

Input Voltage fig. 2. Typical inverter characteristic with -1 slope points identified as VJLand V ~ H .

At this point it is important to review and understand the textbook approach to the intrinsic logic levels and I oise margins of a logic family with an invertor characteristic such as shown in Fig. 2. The -1 slope points are typically taken as defining points for VILand V I HThis . leaves VOH and 10~ to be defined and at this point textbook authors seem to tie divided into two camps: a) those who take VOH and VOL to be also given by the -1 slope points and b) those who take the :table logic states of an infinite chain of inverters or a bistable H VOL. These two choices are invertor pair as defining V ~ and illustrated in Fig. 3. The dotted curve in Fig. 3(b) represents I he transfer characteristic with output and input axes reversed ,md the intersection of the two curves represents the two stable ttates of a pair of cross-coupled inverters. Also as pointed out inany years ago [1]-[3], these are also the stable states of an nfinitely long string of inverters. A survey of about a dozen ligital electronics textbooks showed them all using one or the )ther of these definitions to define logic levels and intrinsic ioise margins [8]-[20]. The two definitions of VOHand VOL )bviously give very different answers with regard to intrinsic ioise margin properties. The definition of Fig. 3(b) appears to be more frequently ised in present day textbooks in spite of the fact that the -1 slope definition of Fig. 3(a) has some theoretical justification while there appears to be little or no theoretical justification or using the stable logic states of Fig. 3(b) to define VOH and VOL.The definitions of Fig. 3(b) immediately run into trouble with the very basic and simple concepts discussed in 2onnection with Fig. 1. The transfer characteristic does not lie within the required shaded area of Fig. 1 and thus cannot represent a set of valid logic level definitions from which any meaningful noise margins can be calculated. Thus the approach of Fig. 3(b) must be rejected as a valid noise margin approach in spite of the fact that it is used by several highly respected digital electronics textbooks. Problems with this approach were pointed out by Hill as early as 1967 [l].
5 tandard
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Input VoItage (b) Fig. 3. Typical choices for defining I ~ and H \ b used ~ in most logic circuit textbooks. (a) -1 slope definition. (b) Bistable inverter pair logic state definition.

The -1 slope definitions of Fig. 3(a) pass the simple test of Fig. 1 and thus are possible logic levels and noise margin definitions. In fact there is some theoretical justification Ibr the -1 slope criteria for defining all four logic levels. If one maximizes the sum of the two noise margins, i.e., N M H N M L , then one finds that a maximum sum requires the -1 slope definitions [7]. This appears to place this criteria on a sound theoretical justification. However, there are problems with even simple logic circuits such as MOS inverters with this definition. Since it maximizes the sum and not the individual terms, nothing prevents the maximum sum from occurrj ng at points where one of the noise margins is zero or e\.en negative! In fact, a negative noise margin can be re1ativ:ly easily obtained from otherwise perfectly valid MOS invertor

IEEE rRANSACTlONS ON EDUCATION, VOL. 36, NO. 4, NOVEMBER 1993

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Fii . 4. Illustration of a transfer curve without a unique -1 slope point.

cha +acteristicS.This is probably the reason many authors have abandoned the definition of Fig. 3(a) in favor of that of Fig. 3(h ). In the remainder of this paper the criteria of Fig. 3(a) will be .eferred to as the negative slope criteria (NSC) and that of IGg. 3(b) as the modified negative slope criteria (MNSC). One of the problems with the negative slope criteria is illustrated in Fig. 4.If the region of the transfer curve between A md B has slope -1, the -1 slope point is not uniquely def ned and in fact will jump from point A to point B as the slolie goes through the -1 value. Shown in the figure are the two sets of noise margin values obtained from either point A )r point B. Since it is unrealistic for the noise margins to abiuptly jump from one set of values to the other as the slope between A and B goes through -1, one would suspect that neither set of values is a reasonable set of noise margin values for the given transfer curve. h c e neither of the previous definitions used in modern electronic textbooks provide an acceptable theoretical or practic: 11 definition of logical levels or of intrinsic noise margins, on :must look for other criteria for establishing these levels.
11. BASICDEFINITIONS OF LOGIC

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Input Voltage, A,,, Aovr
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Fig. 5. Illustration of transfer function shifts with high and low state noise sources. (a) Cross-coupled inverter pair. (b) Inverter input-output characteristics.

LEVELS AND NOISE MARGINS

rhe basic concept of noise margin is usually related to the noise voltage at the gate of a long string of inverters which is required to cause an upset in the logic levels after a very lai ge number of inverter stages. The best-case noise margin has been defined as the noise required at a single gate in such an infinite string to cause logic level upset [7]. Although this can be defined and easily evaluated it is of little practical in portance since one is rarely interested in such an ideal case. A second level of interest is that in which all low gates in a logic string have noise sources present or all high gates have nc vise sources. These cases can be referred to as single-sided noise margins, i.e., S S N M H and SSNML. The worst-case noise condition occurs when noise sources ais present at all inputs in a string of gates with all the low g; te and high gate noise sources contributing in such a way

as to cause a maximum tendency to upset the logic levels [l],[ 2 ] ,[ 7 ] . This is the condition under which one is normally interested in the magnitudes of the noise margins. Such infinite strings of logic gates are equivalent, noise wise, to two crosscoupled inverters forming a bistable flip-flop and such a simple circuit can thus be used to establish worst case noise margins. If a flip-flop is not upset by two noise sources in series with the high and low states, then finite strings of inverters will not be upset. The remainder of this work will concentrate on such worst-case noise margins. The operation of a cross-coupled inverter pair can b e discussed with reference to Fig. 5. Since A,,, becomes A,, and Ab,, becomes A I N ,the solid curves A and A represent the two inverter transfer characteristics with points X and E representing the two stable logic states. These values will br: referenced in subsequent figures as VLHand,VLL. A noise voltage associated with Aout or A,, will shift the solid curve A vertically before it becomes the input ,for the A inverter. Similarly a noise voltage associated with Aout or A I ~ J

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TABLE I CALCULATED NOISE MARGINS(V)

Von

WkNMn
I I
VI, lnput Voltage

I
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VI.

Fig. 6. Valid noise margins for a given inverter characteristic, using an area embedded within the transfer curve loop.

will shift the solid curve A' horizontally before it becomes an input back to the A inverter. The dotted curves represent a pair of transfer characteristics shifted due to a high state noise N H and a low state noise N L . The corresponding stable states move to points X' and Y ' . The inverter retains its high and low states as long as the dotted curves continue to intersect in three points. This leads to an easy-to-interpret graphical approach to a valid set of noise margins for a given inverter characteristic. This is illustrated in Fig. 6 where a cross-hatched rectangle has been drawn inside the loop of the inverter characteristic, with one corner of the rectangle touching each solid curve. Any rectangle which can be drawn inside the characteristic loop represents a set of noise voltages (and corresponding VIL. V I H VOL, , VOH) which are at the limit of inverter stability. When the rectangle becomes a square, one has the worse case equal noise margins (i.e., N M H = N M L ) .When the rectangle becomes a vertical ( N M L = 0) or horizontal ( N M H = 0) line, one has the worst case single-sided noise margins. The existence and shape of the open loops in the transfer characteristics determine the noise margin properties. The fitting of a rectangular area within the loop allows one to define a whole range of valid noise margins but not a single set of unique values. This is, however, the nature of noise margins. For a given inverter characteristic, one can, for example, trade a lower low state noise margin for an improved high state noise margin. One must place additional restrictions on the noise margins to obtain a unique set of noise margins. There are several ways in which this can be done. One can insist on equal noise margins ( N M H = N M L ) in which case one maximizes the area of a square inside the inverter characteristic loop. If one maximizes the area of the rectangle, than one has maximized the product of the two noise margins (i.e. made N M H 0 N M L a maximum). These two criterions will be referred to as the maximum equal criteria (MEC) and the maximum product criteria (MPC). For transfer curves which are nearly symmetrical such as Fig. 5(b), these two criteria give very close results.

Several simple transfer curves, as seen in Fig. 7, can be used to illustrate noise margins with the previously discussed criteria. The loops between the transfer curves range fmm highly symmetrical to highly nonsymmetrical. Table I gives the calculated noise margins according to the five difference criteria previously discussed. For a symmetrical transfer cu we such as Fig. 7(a), reasonable noise margin values are obtained for almost all the criteria. An exception is the MNSC which predicts too large a noise margin. This is typical of the MNSC technique for all circuits. All techniques give essentially the same result for the nonsymmetrical transfer curve of Fig. 7(b). By all criteria except the MEC, the low noise margin is considerable larger than the high noise margin (2.60 V versus 1.00 V). By insisting on equal noise margins, one is restricted to a value of 1.00 V for both values. Only the MEC and MPC techniques give well defined values for both transfer curves of Fig. 7(c) and (d). The transfer curve of Fig. 7(c) has no uniquely -1 slope point on the high output range and was discussed in connection with Fig. 3. Only the techniques based upon the area (MEC and MPC) within the transfer function loop give reliable values of noise margin. Fig. 7(d) has only one -1 slope point on the transfer curve and techniques requiring the location of the -1 slope values obviously fail for this case. It could be argued that the tramfer curve is somewhat contrived and doesn't correspond to my real logic family. While this is true, a valid technique for evaluating noise margins should work for any transfer curve which has valid highflow logic states when used in a crosscoupled inverter configuration. Normally the negative s h p e criteria and the maximum sum criteria give identical results. However in the case of Fig. 7(d) one can define the results for the maximum sum criteria even though one cannot ob)ain two - 1 slope points. However, the maximum sum criteria sitill predicts poor values since it predicts a zero value for one of the noise margins. From the previous discussion, it can be seen that only techniques based upon embedding some area within the tran ifer function loop gives reliable noise margin values for a wide range of possible transfer functions. The normal techniques appearing in most modem electronic textbooks do not give reliable calculations of noise margins for a broad range of transfer characteristics and frequently fail for simple NtOS circuits. The area technique goes back to basic definitions of noise margin shifts in the transfer functions and gives the only

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(c) Fig 7. Illustration of noise margin criteria for several transfer curves. (a) Highly symmetric transfer curve. (b) Transfer curve with unequal high and IOW level noise margins. (c) Transfer curve with ambiguous -1 slope point. (d) Transfer curve with only one -1 slope point.

re1 ,able method for evaluating noise margins. This result is no new but was discussed in many of the early papers on no se margin. [n comparing the maximum equal criteria and the maximum pn )duct criteria, it appears unduly restrictive to insist on an ecl la1 high and low noise margin. A transfer characteristic siriilar to that of Fig. 7(b) has a low noise margin which is obviously considerably larger than the high noise margin. Tt is easily results from maximizing the area of a rectangle w thin the transfer function loop. Thus the preferred method f o - evaluating noise margins must be to muximize the urea of U vectangle within the transfer function loop (or the maximum p i qduct criteria). Part of the reason for the use of the -1 slope criteria in 'tbooks is probably the fact that these points can be mather iatically calculated for many logic families. The maximum ai ea technique is easily understood from a graphical approach, bi it is not easily calculated for most real transfer functions. However, an easily calculated value, which is wrong, does not ,ji.stify the continued use of this technique in present day or f l ture textbooks. The maximum product criteria is easily extended in concept t': account for temperature variations in transfer curves or for

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Input Voltage (Volts)

Fig, 8.

Illustration of noise margin definitions for a family of transfer curve3.

effects of parameter variations in transfer curve characteristics. Consider, for example Fig. 8 where the shaded area is used to include a family of transfer function characteristics dui: to parameter variations and/or temperature variations. Th: maximum area between the worst case curves still graphicall-y defines a valid set of worst-case noise margins.

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IEEE TRANSACTIONS ON EDUCATION, VOL. 36. NO. 4, NOVEMBER 1993

111. SUMMARY

Techniques for evaluating the noise margin for families of tigital logic circuits have been discussed and evaluated. It t as been shown that the technique of evaluating the - 1 slope points on the inverter transfer function as used in most modern tzxtbooks is not a valid and reliable approach to evaluating f d s e margin values. It is argued that the most reliable and reasonable criteria is to maximize the product of the two iloise margins. This is equivalent to maximizing the area of : rectangle embedded within the loop formed by the transfer c.urves of an inverter pair. Most of the material presented here is not new but can be found in the early literature on noise margin. However, because of the widespread use of the -1 slope criteria in modern 1 extbooks it appears that a re-look at basic approaches to noise margins are in order. It is hoped that this discussion will dmulate further thought in this area and that future electronic Textbook authors will abandon the present approach in favor 1)f a more realistic and valid treatment of the concept of noise nargin and how it relates to the transfer characteristic of logic ircuits.

[8] V. H. Grinich and H. G. Jackson, Introduction to Intqrated Circuits. New York: McGraw-Hill, 1975, pp. 111-113. (91 D. A. Hodges and H. G. Jackson, Analysis and Design of DigLal Integrated Circuits. New York: McGraw-Hill, 19x3, pp. 68-85. [lo] R. A. Colclaser, D. A. Neamen and C. F. Hawkins, Elcctronic Circarit Analysis. New York: Wiley, 1984, pp. 155-156. [ 111 A. S. Sedra and K. C. Smith, Microelectronic Circuirs. New Yo1 k: Holt, Rinehart and Winston, 1982, pp. 669473. [ 12) M. S. Ghausi, Electronic Devices and Circuits: Discrete and 1ntegratc.d. New York: Holt, Rinehart and Winston, 1985, pp. 608-610. 113) R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Technipes for Analog and Digital Circuits. New York: McGraw-Hill, 1990, pp. 602-607. [14] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits. Reading, MA: Addison-Wesley, 1988, pp. 83-86. [ 151 M. N. Horenstein, Microelectronic Circuits and Dwices. Englewood Cliffs, NJ, Prentice-Hall, 1990, pp. 721-724. 1161 C. A. Holt, Electronic Circuits. New York: Wiley, 1978, pp. 16C-102. [I71 P. R. Belanger, E. L. Adler and N. C. Rumin, Introduction to Circbits with Electronics. New York: Holt, Rinehart and Winston, 1985, pp. 329-331, 353-356. 1181 J. Y. Chen, CMOS Devices and Technology for VLSI. Englewcod Cliffs, NJ: Prentice-Hall, 1990, pp. 94-98. [I91 D. A. Pucknell and K. Eshraghian, Basic VLSI Design . Englewcod Cliffs, NJ: Prentice-Hall, 1988, pp. 244-245. [ZO] P. M. Chirlian, Analysis and Design of Integrated Elertronic Circusts. New York: Harper and Row, 1987, pp. 348-353.

REFERENCES
C. F. Hill, Definitions of noise margin in logic systems, Mullard Tech. Commun, no. 89, pp. 239-245, Sept. 1967. --, Noise margin and noise immunity in logic circuits, Microelectron., vol. 1, pp. 16-21, Apr. 1968. J. Lohstroh, Static and dynamic noise margins of logic circuits, IEEE J . Solid-state Circuits, vol. SC-14, pp. 591-598< June 1979. , Calculation method to obtain worst-case static noise margins of logic circuits, Electron. Lett, vol. 16, pp. 273-274, Apr. 1980. , The punch-through device as a passive exponential load in fast static bipolar RAM cells, IEEE J. Solid-State Circuits, vol. SC-14, pp. 840-844, Oct. 1979. E. Seevinck, Deriving stability criteria for non-linear circuits with application to worst-case noise margin of IL, Electron. Lett., vol. 16, pp. 867-869, Nov. 1980. 1. Lohstroh, E. Seevinck, and J. DeGroot, Worst-case static noise margin criteria for logic circuits and their mathematical equivalence, IEEE J. Solid-state Circuits, vol. SC-18, pp. 803-806, Dec. 1983.
_ .

John R. Hauser (S59-MSO-SM78-F-87) was born near Mocksville, NC, on September 19, 1938. He received the B.S. degree in electrical engineering from North Carolina State University in 1160 and the M.S. and Ph.D. degrees, also in electrical engineering, from Duke University, Durham, NC in 1962 and 1964, respectively. In 1960 and 1961, he was with Bell Telephone Laboratories, Winston-Salem, NC, where he worked on the design of electronic circuits. In June 162 he ioined the Research Triangle Institute. Durhm. where he did research work on semiconductor and microelectronic devices. He joined the faculty at North Carolina State University, Raleigh, in September 1966 where is presently a Professor of electrical engineering and Directoi of the Solid State Electronics Laboratory. His present interests are in the areas of microelectronics and solid-state devices. Dr. Hauser is a member of Eta Kappa Nu, Sigma Xi. and the Ameri:an Physical Society.