Lovely Professional University, Punjab

Course Code ECE419 Course Category Course Title DIGITAL VLSI DESIGN Courses with numerical and conceptual focus Course Planner 16937::Tapsi Singh Lectures 3.0 Tutorials Practicals Credits 1.0 0.0 4.0

TextBooks Sr No T-1 Title Digital Integrated Circuits: A Design Perspective Reference Books Sr No R-1 R-2 Other Reading Sr No OR-1 OR-2 OR-3 OR-4 OR-5 OR-6 OR-7 OR-8 OR-9 OR-10 OR-11 OR-12 OR-13 OR-14 Journals articles as Compulsary reading (specific articles, complete reference) http://airccse.org/journal/vlsi/papers/2311vlsics04.pdf , http://airccse.org/journal/vlsi/papers/2311vlsics06.pdf , http://www.sciencedirect.com/science/article/pii/S0167926011000344 , http://www.ohio.edu/people/starzykj/network/Research/VLSIPapers.html , http://nptel.iitm.ac.in/courses/Webcourse-contents/IIT%20Kharagpur/Embedded%20systems/Pdf/Lesson-20.pdf , http://www.cs.washington.edu/education/courses/cse467/03wi/FPGA.pdf , http://www.xilinx.com/publications/archives/xcell/Xcell32.pdf , http://www.doulos.com/knowhow/verilog_designers_guide/models/8bit_x_8bit_pipelined_multiplier/ , http://www.csun.edu/~ags55111/doc/526/526report.pdf , nptel.iitm.ac.in/syllabus/syllabus.php?subjectId=117101058 , www.csse.monash.edu.au/courseware/cse2303/2006/lectures/lect08.ppt , freepdfdb.org/pdf/asm-charts , http://www.asic-world.com/verilog/memory_fsm1.html , http://www.ele.uri.edu/Courses/ele444/class/pipe_add.pdf , Title Verilog HDL Digital design Author Samir Palnitkar Morris mano Edition 2nd 5th Year 2013 2001 Publisher Name , Pearson Education Publications Prentice Hall of India Author J. Rabaey Edition 2nd Year 1997 Publisher Name Prentice Hall of India

Relevant Websites Sr No RW-1 RW-2 RW-3 (Web address) (only if relevant to the course) http://www.xilinx.com/support/index.htm#nav=sd-nav-link- 156334&tab=tab-sd http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx %20ISE%20WebPACK %20Verilog%20Tutorial.pdf http://www.ece.iit.edu/~pfelber/ccd/project.pdf Salient Features Xilinx support documents Verilog Tutorial Charge-Coupled Devices

LTP week distribution: (LTP Weeks) Weeks before MTE Weeks After MTE Spill Over 7 7 3

Detailed Plan For Lectures

Week Number Lecture Number Broad Topic(Sub Topic) Chapters/Sections of Text/reference books Other Readings, Lecture Description Relevant Websites, Audio Visual Aids, software and Virtual Labs Basic knowledge of MUX based design Learning Outcomes Pedagogical Tool Demonstration/ Case Study / Images / animation / ppt etc. Planned

Week 1

Lecture 1

Review of digital design(MUX based digital design)

R-2:Section 7.2.2 p no. 332

Students will understand the concept of MUX and designing based on mux

Lecture 2

Review of digital design (Programmable Logic Arrays (PLA) and Programmable Array Logic (PAL)) Review of digital design (Programmable Logic Arrays (PLA) and Programmable Array Logic (PAL)) Review of digital design (Sequential circuits and timing)

R-2:Section 7.6 to 7.7 p no. 328 to 332

lec 2 Basic knowledge of students will know the PAL and PLA basics and differences between Programming logic array and Parray logicand its designing lec 2 Basic knowledge of students will know the PAL and PLA basics and differences between Programming logic array and Parray logicand its designing Introduction of students will learn how sequential circuits like to implement the design flipflops, registers and its using sequential circuits timing diagrams Introduction of students will learn how sequential circuits like to implement the design flipflops, registers and its using sequential circuits timing diagrams

Lecture 3

R-2:Section 7.6 to 7.7 p no. 328 to 332

Week 2

Lecture 4

R-2:Section 5.1 to 5.5 p no. 197 to 221

Lecture 5

Review of digital design (Sequential circuits and timing)

R-2:Section 5.1 to 5.5 p no. 197 to 221

Week 2

Lecture 6

Review of digital design(Design of a pattern sequence detector using MUX)

R-2:Section 4.11 p no. 168

OR-10

Design example using MUX like pattern sequence detector

Understanding the Design the basic concepts of pattern circuit and then sequence generator and implement it on Xilinx how to design the circuit Refer flecther for vending machine and its implementation on Xilinx Designing based on Xilinx

Week 3

Lecture 7

Review of digital design(Design of a vending machine controller using PAL)

R-2:Section 7.7 p no.332

OR-9

Programmind array logic Understanding the examples like how to concepts of vending implement the circuit machine using programmable array logic Design example using moore and mealy Verilog Basics and its applications Understanding the concepts of sequential circuit design

Lecture 8

Review of digital design (Sequential circuit design (Moore and Mealy circuits)) Introduction to Verilog coding (Introduction to Verilog)

R-1:Section 14.7.3 p no. 372 R-1:Section 2.1 to 2.8 p no. 53 to 66 and Section 3.1 to 3.5 p no. 69 to 88 R-1:Section 2.1 to 2.8 p no. 53 to 66 and Section 3.1 to 3.5 p no. 69 to 88 R-1:Section 1.3 p no. 47 R-2:Section 4.1 to 4.12 p no. 135 to 195 and section 6.1 to 6.6 p no. 253 to 305 R-2:Section 4.1 to 4.12 p no. 135 to 195 and section 6.1 to 6.6 p no. 253 to 305 R-1:Section 14.4 p no. 353 to 364

OR-11

Lecture 9

Learn basics of Verilog Xilinx Software like different operators ,datatypes etc

Week 4

Lecture 10

Introduction to Verilog coding (Introduction to Verilog)

Verilog Basics and its applications

Learn basics of Verilog Xilinx Software like different operators ,datatypes etc

Lecture 11

Introduction to Verilog coding (Design flow) Introduction to Verilog coding (Realization of combinational and sequential circuits)

Verilog design flow and Know about veriog different steps for design flow and how to designing implement it practically Basics of Combinationsl Learn basics of Designing the circuit and sequential circuits Combinationsl and on Xilinx sequential circuits like flipflops,registers,mux, demux Basics of Combinationsl Learn basics of Designing the circuit and sequential circuits Combinationsl and on Xilinx sequential circuits like flipflops,registers,mux, demux synthesis design flow in Verilog Know about synthesis Xilinx Software design flow like different steps used for designing Learn how to write a testnbench Writing a testbench on Xilinx Software

Lecture 12

Week 5

Lecture 13

Introduction to Verilog coding (Realization of combinational and sequential circuits)

Lecture 14

Introduction to Verilog coding (RTL coding guidelines)

Lecture 15

Introduction to Verilog coding R-1:Section 2.6.2 p (Coding organization and writing a no. 63 test bench) Design using algorithmic state R-2:Section 8.4 p no. machine charts(Derivation of ASM 369 charts)

Writing a testbench

Week 6

Lecture 16 Lecture 17

Term Paper,Test 1 Basics of algorithmic state machine and its applications Learn how to draw ASM chart and its different steps for implementation

Week 6

Lecture 18

Design using algorithmic state machine charts(Design examples such as dice game etc using ASM charts)

T-1:Section 8.4 page no. 369

OR-12

Design examples of ASM charts like Dice game Design examples Design examples based on Verilog like bus arbitrator Design examples Design examples based on Verilog like bus arbitrator Lecture 20 and Lecture 21 are reserved for contingency Lecture 20 and Lecture 21 are reserved for contingency

Understanding the concept how to use ASM Understanding the concept how to use ASM and its implementation Understanding the concept how to use ASM and its implementation Revision of the lectures taught till MTE Revision of the lectures taught till MTE

Its implementation on Xilinx

Week 7

Lecture 19

Design using algorithmic state R-2:Section 8.5 p no. machine charts(Implementation of 376 ASM charts using microprogramming) Design using algorithmic state R-2:Section 8.5 p no. machine charts(Implementation of 376 ASM charts using microprogramming) Design using algorithmic state machine charts(Verilog design of bus arbitrator)

OR-12

Designing the circuit and then its implementation on Xilinx Designing the circuit and then its implementation on Xilinx

Lecture 20

OR-12

Lecture 21

Design using algorithmic state machine charts(Verilog design of bus arbitrator)

MID-TERM
Week 8 Lecture 22 Design of memories(Verilog realization of Read Only Memory (ROM)) T-1:Section 12.2.1 p no. 634 Basics of Read Only Memory and its realization in Verilog Students will learn about the concept of memory ie read only memory and its designing part Students will learn about the concept of memory ie random access memory and its designing Students will learn about the concept of memory and how to access it extrenally students will learn how Designing on Xilinx to optimize the software sequential circuits students will learn how Designing on Xilinx to optimize the software sequential circuits students will learn different examples of pipelining students will learn the concept of multilpiers and its designing students will learn the concept of multilpiers and its designing Designing based on Xilinx software Designing based on Xilinx software

Lecture 23

Design of memories(Verilog realization of Random Access Memory (RAM))

T-1:Section 12.2.3 p no. 657

Verilog realization of RAM

Lecture 24

Design of memories(Verilog coding of controller for accessing external memory) Design of arithmetic functions (Pipelining concept) Design of arithmetic functions (Pipelining concept) Design of arithmetic functions (Verilog design of a pipelined adder/subtractor) Design of arithmetic functions (Design of multipliers) Design of arithmetic functions (Design of multipliers) T-1:Section 7.5 p no. 358 to 360 T-1:Section 7.5 p no. 358 to 360 T-1:Section 7.5 p no. 358 to 360 T-1:Section 11.4 p no. 586 to 594 T-1:Section 11.4 p no. 586 to 594

OR-13

Basics of memory and how to access it externally Pipelining concept

Week 9

Lecture 25

Lecture 26

Pipelining concept

Lecture 27

OR-14

Pipelining concepts and its examples Multipliers like binary multiplier Multipliers like binary multiplier

Week 10

Lecture 28

Lecture 29

Week 10

Lecture 30

Design of arithmetic functions (Verilog design of a pipelined multiplier)

T-1:Section 11.4 p no. 586 to 594

OR-8

Verilog design of multiplier

students will learn Refer tutorials from about the pipelining websites concept and how to implement different circuits with pipelining Students will know the different issues for designing and then for its testing Students will know the different issues for designing and then for its testing Students will learn about testing of different circuits Students will learn about testing of different circuits Students will know how to test different circuits

Week 11

Lecture 31

Design for testability(Design for testability)

T-1:Section H.3.1 to H.3.4 p no. 723 to 729 T-1:Section H.3.1 to H.3.4 p no. 723 to 729 T-1:Section H.4 p no. 734 to 737 T-1:Section H.4 p no. 734 to 737

Issues in design for testability

Lecture 32

Design for testability(Design for testability)

Issues in design for testability

Lecture 33

Design for testability(Testing combinational and sequential logic) Design for testability(Testing combinational and sequential logic) Design for testability(Boundary scan testing and Built-in self test)

Testing of different circuits Testing of different circuits Term Paper,Test 2

Week 12

Lecture 34

Lecture 35 Lecture 36 T-1:Section H.3.4 to H.3.5 p no. 729 to 730 R-2:Section 11.20 p no. 567 OR-6

Built in self test and boundary scan testing

Week 13

Lecture 37

Introduction to FPGA (Configurable logic block (CLB))

Introduction to Students will Configurable logic block understand the concept of configurable logic blocks and its uses and the differences between CLBs and FPGA Introduction to Students will Configurable logic block understand the concept of configurable logic blocks and its uses and the differences between CLBs and FPGA Basics of FPGA,Different Xilinx series like XC4000 series,FPGA based design using Verilog Basics of FPGA,Different Xilinx series like XC4000 series,FPGA based design using Verilog Lecture 41 is reserved for contingency Students will know about the basics of FPGA Design of any circuit on Xilinx and then its implementation on FPGA Design of any circuit on Xilinx and then its implementation on FPGA

Lecture 38

Introduction to FPGA (Configurable logic block (CLB))

R-2:Section 11.20 p no. 567

OR-6

Lecture 39

Introduction to FPGA(FPGA)

R-2:Section 11.20 p no. 567

OR-5

Week 14

Lecture 40

Introduction to FPGA(FPGA)

R-2:Section 11.20 p no. 567

OR-5

Students will know about the basics of FPGA

Lecture 41

Introduction to FPGA(Introduction to Xilinx series)

OR-7

Revision of the lectures taught till ETE

Week 14

Lecture 42

Introduction to FPGA(FPGA based design using Verilog)

lecture 42 is reserved for Revision of the lectures contingency taught till ETE

SPILL OVER
Week 15 Lecture 43 Lecture 44 Lecture 45 Spill Over Spill Over Spill Over

Scheme for CA:

Component Term Paper,Test Frequency 2 Total :Out Of 3 Each Marks Total Marks 10 10 20 20

Details of Academic Task(s)

AT No. Objective Topic of the Academic Task Nature of Academic Task (group/individuals/field work Evaluation Mode Allottment / submission Week 5/6

Test 1

To check the knowledge

MUX based digital design, Programmable Logic Arrays Individual (PLA) and Programmable Array Logic (PAL), Sequential circuits and timing, Design of a pattern sequence detector using MUX, Design of a vending machine controller using PAL, Sequential circuit design (Moore and Mealy circuits),: Introduction to Verilog, Realization of combinational and sequential circuits, RTL coding guidelines, Coding organization and writing a test bench, Design flow,Derivation of ASM charts Verilog realization of Read Only Memory (ROM), Verilog Individual realization of Random Access Memory (RAM), Verilog coding of controller for accessing external memory,Pipelining concept, Verilog design of a pipelined adder/subtractor, Design of multipliers, Verilog design of a pipelined multiplier, Design for testability, Testing combinational and sequential logic, Boundary scan testing and Built-in self test Advanced topics Individual

knowledge

Test 2

To check the knowledge

Based on performance of students

11 / 12

Term Paper 1

Knowledge of students

Knowledge based on topic

3 / 12

List of suggested topics for term paper[at least 15] (Student to spend about 15 hrs on any one specified term paper) Sr. No. Topic 1 MIPS examples of a small system and VGA circuits

2 Comparative analysis of master slave latches and flip flops for high performance and low power systems 3 Reducing cross talk in ALU part of a processor 4 Fault diagnosis in mixed signal low testability system 5 Designing and mapping of a turbo decoder for 3G mobile systems using dynamically reconfigurable architecture 6 Hardware implementation of fast convolution for GPS signal acquisition using FPGA 7 Dynamically re-configurable array architecture for future mobile digital baseband processing 8 A pipelined asynchronus cache system 9 Soft error tolerant asynchronus FPGA 10 Improvisation of Gabor filter design using verilog HDL 11 A new reversible design of BCD adder 12 High speed and ares sufficient vedic multiplier 13 A very fast and low power carry select adder 14 State machine design technique for verilog 15 An entropy based learning hardware organisation using FPGA

Plan for Tutorial: (Please do not use these time slots for syllabus coverage)
Tutorial No. Lecture Topic Type of pedagogical tool(s) planned (case analysis,problem solving test,role play,business game etc)

Tutorial 1 Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Tutorial 6 Tutorial 7

Mux based Desigining Designing sequence detector Moorey and mealy problems Realization of combinational and sequential circuits writing a testbench Test bench examples ASM designing

Problem solving Problem solving Problem solving Problem solving Problem solving Problem solving Problem solving

After Mid-Term
Tutorial 8 Tutorial 9 Tutorial 10 Tutorial 11 Tutorial 12 Pipelined adder/subtractor Multipliers Testing combinational and sequential logic Combinational and sequential logic examples CLB Problem solving Problem solving Problem solving Problem solving Case analysis

Tutorial 13 Tutorial 14

Different Xilinx series FPGA

Case analysis Case analysis