Code No: 07A71006

R07

Set No. 2

IV B.Tech I Semester Examinations,December 2011 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Instrumentation Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What are the main categories of testing? Explain these with examples. (b) Draw the block level implementation of a polarity hold SRL and explain its working. (c) How ROM memories can be tested? 2. (a) What are dierent types of scaling models and scaling factors. (b) Discuss the scaling factors for the following device parameters. i. ii. iii. iv. Gate capacitance Max.operating frequency Current density Power dissipation per gate. [2+2+2+2+2+6] [6+6+4]

(c) Discuss limits of miniaturization.

3. (a) What are the advantages of BICMOS Technology over CMOS Technology? (b) Explain how a bipolar NPN transistor is included in N well CMOS processing. Draw the cross section of BICMOS transistor. [4+12] 4. (a) An n- channel MOSFET operated in the saturation region with the following parameters tox =10m, n =520cm2 /V-S, (W/L) =8, Vtn = 0.7V, Vds =2V, Vgs =2V. Find its device equation and drain source resistance. (b) Discuss body bias eects on the MOS device operation with necessary equation. [8+8] 5. (a) Design a 32 bit parallel adder optimized for speed, single-cycle operation and regularity of layout. (b) Compare the advantages and disadvantages of NAND ROMs and NOR ROMs. [8+8] 6. (a) Explain clocked CMOS logic, domino logic and n-p CMOS logic. (b) In gate logic, compare the geometry aspects between two -input NMOS NAND and CMOS NAND gates. [8+8] 7. (a) Draw the UV erasable EPROM structure for the programming of PAL device and explain how it programmed.

Code No: 07A71006

R07

Set No. 2

(b) Explain how two antifuses are congured to operate I/O pad as in input, output or bidirectional pad. [8+8] 8. (a) Explain how a FSM model is described in VHDL with suitable program. (b) What is the dierence between Design capture tools and design verication tools? Give some examples of each. [8+8]

Code No: 07A71006

R07

Set No. 4

IV B.Tech I Semester Examinations,December 2011 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Instrumentation Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Explain the CMOS system design based on the I/O cells with suitable example. (b) Design a four bit parity generator using only XOR gates and draw the Schematic of it. [8+8] 2. (a) Explain the concept of sheet resistance and apply it to compute the ON resistance (VDD to GND) of an NMOS inverter having pull up to pull down ratio of 4:1, If n channel resistance is Rsn = 104 per square. (b) Calculate the gate capacitance value of 5m technology minimum size transistor with gate to channel capacitance value is 4 104 pF/m2 . [10+6] 3. (a) What is ATPG? Explain a method of generation of test vector. (b) Explain the terms controllability, observability and fault coverage. 4. (a) Explain various regions of CMOS inverter transfer characteristics. (b) For a CMOS inverter, calculate the shift in the transfer characteristic curve when n /p ratio is varied from 1/1 to 10/1. [8+8] 5. Explain the following two oxidation methods in IC fabrication. (a) High pressure oxidation (b) Plasma oxidation. 6. Explain the following: (a) Double metal MOS process rules (b) Design rules for P- well CMOS process. [8+8] [8+8] [8+8]

7. (a) Draw and explain the three-level-metal standard cell strategy used for a threeinput NAND gate. (b) Compare the dynamic PLAs and Pseudo-nMOS PLAs. [8+8]

8. (a) Write a VHDL program for N-bit ripple carry adder can be built from N full adders. (b) Explain how a logic level simulation can verify a complex circuits compared to other simulations. [8+8]

Code No: 07A71006

R07

Set No. 1

IV B.Tech I Semester Examinations,December 2011 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Instrumentation Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain briey about wiring capacitances associated with the layers. Mention typical values of such capacitances. [16] 2. (a) Draw an nMOS transistor model indicating all the components. (b) Explain latch up problem in CMOS circuits. [8+8]

3. (a) What are the dierent data types available in VHDL and how they are indicated? (b) Write a VHDL program for a 4-bit Counter with Asynchronous reset. [8+8] 4. Explain the scan-path design technique used to test sequential circuits in detail. [16] 5. Draw the stick diagram and mask layout for a CMOS two input NOR gate and stick diagram of two input NAND gate. [16] 6. (a) Draw the schematic for Transmission gate adder and explain its operation with truth table. (b) Show the basic one row and one column RAM architecture and explain its operation. [8+8] 7. (a) Explain the function of 4:1 Mux in PAL CMOS device with the help of I/O structure. (b) Explain how the pass transistors are used to connect wire segments for the purpose of FPGA programming. [8+8] 8. With neat sketches explain BICMOS fabrication process in an N well. [16]

Code No: 07A71006

R07

Set No. 3

IV B.Tech I Semester Examinations,December 2011 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Instrumentation Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What are the draw backs of PLAs? How PLAs are used to implement combinational and sequential logic circuits?

(b) Draw the schematic of CPLD and compare it with FPGA.

[8+8]

2. (a) Why is the design process carried out in NMOS although CMOS is the dominant technology?

(b) Sketch the cross sectional view of the following: i. NMOS Enhancement mode transistor. ii. NMOS Depletion mode transistor. iii. PMOS Enhancement mode transistor.

[4+4+4+4]

3. (a) Write a architecture for a 4- bit Counter in both behavioral and structural styles.
(b) Explain with example how mixed mode simulator are more useful for CMOS circuits testing. [8+8]

4. (a) Draw and explain the layout for a combinational adder appropriate for a data path. (b) Draw the Serial/parallel multiplier structure and explain how multiplication is performed. [8+8] 5. Calculate the rise time and fall time of the CMOS inverter (W/L)n = 6 and (W/L)p =8, Kn =150 A/V 2 , Vtn =0.7V,Kp = 62 A/V 2 , Vtp =-0.85V , VDD =3.3V. Total output capacitance =150 pF. [16] 6. (a) Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout. (b) Draw a schematic for a CMOS edge-sensitive scan-register and also draw some circuit level diagrams of its implementation. [8+8] 7. (a) Explain briey about MOS transistor switch. (b) Discuss the square law model of FET. [8+8]

8. Briey discuss limits of scaling. Why scaling is necessary for VLSI circuits? [16]