Code No: 07A6EC03

R07

Set No. 2

III B.Tech II Semester Examinations,December-January, 2011-2012 VLSI DESIGN Common to BME, ETM, E.CONT.E, ECE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Derive the relation between IDS & VDS of MOSFET.

(b) Draw the circuit for NMOS inverter and explain its operation. 2. (a) Draw the circuit for 4 transistor SRAM and explain its working. (b) Draw the one cell dynamic RAM circuit and explain its working. [8+8] [8+8]

3. How Integrated Passive Componoments are fabricated in ICs? Explain.

[16]

4. (a) Draw the logic circuit for Inverter with a transmission gate to provide tri-state output, and explain the same.
(b) Explain about Pass Transistor Logic, with examples. [8+8]

5. (a) Explain about Mapping Process. (b) What is the purpose of constraints in synthesis process? Explain. 6. (a) Explain about: i. Diagnostic Test ii. Functional Test iii. Parametric Test.
(b) Explain about Design strategies for Testing. [6+10]

[8+8]

7. (a) Explain about rules for drawing Sticks Diagram.

(b) Draw the circuit for 2-input NAND gate and draw the layout diagram for the same, giving explanation. [4+12] 8. (a) Explain about various operations involved in a standard cell based design. (b) What are the advantages of cell-based design methodology? Explain. [6+10]

Code No: 07A6EC03

R07

Set No. 4

III B.Tech II Semester Examinations,December-January, 2011-2012 VLSI DESIGN Common to BME, ETM, E.CONT.E, ECE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain about static Timing and Post Layout Timing.

[16]

2. (a) Derive the expressions for Rise-Time R and fall time f in the case of CMOS Inverter.

(b) Express the Area capacitance interms of standard capacitance units. [10+6]
3. Explain about oxidation, Diusion and Ion Implanatation Processes of I C Fabrication. [16] 4. Draw the circuits for n-MOS, p-MOS and C-MOS Inverter and explain about their operation and compare them. [16]

5. What are the circuit design considerations in the case of static adder circuits.
[16]

6. Using block diagrams and schematics explain about Congurable Logic Blocks(CLBs). [16] 7. (a) Explain about system level Testing. (b) Give the Architecture of a boundary scan test and explain the same. [6+10] 8. (a) Explain about the rules for drawing a stick diagram, with colour notation and without colour notation. (b) Draw the circuit for CMOS NOR logic gate and draw its stick diagram giving explanation. [6+10]

Code No: 07A6EC03

R07

Set No. 1

III B.Tech II Semester Examinations,December-January, 2011-2012 VLSI DESIGN Common to BME, ETM, E.CONT.E, ECE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain about Gate level verication and timning Reports pertaining to VLSI Design. [16] 2. (a) Explain about the Stick notation and rules for Stick Diagram. (b) Draw the circuit for 2-input NOR gate and its Stick Diagram, giving explanations. [6+10] 3. Explain about Static, Dynamic and Domino logics with examples. [16]

4. Draw the circuit for nMOS Inverter and explain its operation and characteristics. [16] 5. (a) Explain about bit sliced Data path organization. What is the signicance of Data paths in digital processors? (b) Give the Truth Table for full adder and explain its Boolean expression. [8+8] 6. (a) Explain the principle of Gate Arrays. (b) With the help of sketches explain how NAND gate can be realized using CMOS gate Arrays. [6+10] 7. (a) What are the dierent categories of DFT techniques? Explain. (b) What is meant by signature analysis in Testing? Explain with an example. [8+8] 8. (a) With the help of neat sketches, explain about the fabrication sequence of I.C. (b) Using necessary sketches, explain about photolithography process, in semi conductor device manfacture. [8+8]

Code No: 07A6EC03

R07

Set No. 3

III B.Tech II Semester Examinations,December-January, 2011-2012 VLSI DESIGN Common to BME, ETM, E.CONT.E, ECE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Draw the circuits for n-MOS, p-MOS and C-MOS Inverter and explain about their operation and compare them. [16]
2. Explain about Mapping Processes and constraints. [16]

3. Explain about the notations used the stick diagram for. Draw the Sticks diagram for NMOS Inverter giving explanation. [16] 4. (a) What are the issues involved in driving large capacitive loads in VLSI circuits? Explain.

(b) Derive the expression for SD in the case of a MOSFET.

[8+8]

5. Explain about the principle, operation, salient features and applications of FPGAs. [16] 6. Write notes on any TWO (a) DGT (b) BIST (c) Boundary scan Testing. [82=16]

7. Draw the circuit for Transmission -gate-based full adder with sum and carry delays of same value and explain its working. [16] 8. Explain about the following terms, using necessary theoretical equations, pertaining to MOSFETs.

(a) Thereshold voltage VT h (b) Body eect parameter. [8+8]