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Current and voltage parameters Fan-Out Propagation delays Power requirements Speed-power product Noise immunity Invalid voltage levels Current-sourcing and current-sinking action IC Packages
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
FIGURE 8-9 (a) When the TTL output is in the LOW state, Q4 acts as a current sink, deriving its current from the load. (b) In the output HIGH state, Q3 acts as a current source, providing current to the load gate.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Data sheets contain electrical characteristics, switching characteristics, and recommended operating conditions.
Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 9e
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Copyright 2004 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
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Refer to Table 8-6 on the next page for a comparison between the series characteristics
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FIGURE 8-17
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FIGURE 8-18 A large current spike is drawn from VCC when a totem-pole output switches from LOW to HIGH.
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Drain-toSource Bias
RON()
ROFF()
P-channel
Negative
1000 (typical)
1010
N-channel
Positive
1000 (typical
1010
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CMOS Inverter CMOS NAND gate CMOS NOR gate CMOS SET-CLEAR FF
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4000/1400 series 74C series 74HC/HCT (high speed CMOS) 74AC/ACT (advanced CMOS)
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Unused inputs (tie either high or low dont leave un-terminated) Static sensitivity ESD precautions Latch up (from parasitic PNP and NPN transistors embedded in the
substrate)
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The move toward low voltage systems will continue and the technician must be prepared to operate in an environment where devices may not necessarily operate on 5 volts.
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8-12 Open Collector/Open Drain Outputs Conventional CMOS outputs and TTL totem pole outputs should never be connected to the same point.
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Acts as a single pole, single throw switch Controlled by an input logic level Passes signals in both directions Signals applied to the input can be analog or digital Input must be between 0 and VDD volts.
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FIGURE 8-45 Example 8-12: 74HC4016 bilateral switches used to switch an analog signal to two different outputs.
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8-17 IC Interfacing
Driver provides the output signal. Load receives the signal. Interface circuit connected between driver and load to condition the signal for the load. Interfacing between logic families is common in digital systems. Table 8-12 on the next page summarizes current parameters for standard devices.
Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 9e
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8-17 IC Interfacing
CMOS Parameter IIH(max) IIL(max) IOH(max) IOL(max) 4000B 1 uA 1 uA 0.4 mA 0.4 mA 74HC/HCT 1 uA 1 uA 4 mA 4 mA TTL Parameter IIH(max) IIL(max) IOH(max) IOL(max) 74 40 uA 1.6 mA 0.4 mA 16 mA 74LS 20 uA 0.4 mA 4 mA 8 mA 74AS 20 uA 0.5 mA 2 mA 20 mA 74ALS 20 uA 100 uA 4.0 mA 8 mA 74F 20 uA 0.6 mA 1.0 mA 20 mA
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74AC/ACT 1 uA 1 uA 24 mA 24 mA
74AHC/AHCT 1 uA 1 uA 8 mA 8 mA
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8-21 Troubleshooting
Logic pulser tool that generates a short pulse when actuated
Senses the existing voltage level and produces a pulse in the opposite polarity Output impedance of 2 Ohms or less
Using logic pulser and probe to test a circuit Finding shorted nodes
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FIGURE 8-53 A logic pulser can inject a pulse at any node that is not shorted directly to ground or VCC.
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FIGURE 8-54 A logic pulser and a logic probe can be used to trace shorted nodes.
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