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Books EC3034 Modeling and Testing of Digital Systems

Monsoon 2012
1. J. Bhasker; A VHDL Synthesis Primer, B.S. Publications 2001 2. VHDL for Engineers ,by Kenneth L Short ,Pearson Education ,2006 3. Miron Abramovici et. al. Digital System Testing and Testable Design, Jaico Publishing House, 2001 4. Charles H. Roth Jr; Digital System Design Using VHDL, Thomson Education,2005

EC3034 Modeling and Testing of Digital Systems - Monsoon 2012

Traditional vs Hardware Description Languages

Procedural programming languages provide the how or recipes
for computation for data manipulation for execution on a specific hardware model

Why do we Describe Systems?

Design Specification
unambiguous definition of components and interfaces in a large design

Design Simulation
verify system/subsystem/chip performance prior to design implementation

Hardware description languages describe a system

many different facets behavior structure functional properties physical properties
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Design Synthesis
automated generation of a hardware design
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HDL-Based Design Flow

Describe desired functionality and timing using HDL such as VHDL, Verilog etc. Use high-level synthesis tool to obtain structural level design Using placement and routing tools to obtain physical level design Very popular design approach for standard cell gate array design and FPGA based design
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Why HDLs Instead of Diagrams?

Schematic Diagrams Limited descriptive power State Diagrams and Algorithmic State Machines Limited portability Limited complexity Difficult to describe parallelism HDLs Highly portable (text) Describes multiple levels of abstraction Represents parallelism Provides many descriptive styles Structural Dataflow Behavioral Serves as input for synthesis

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What HDLs can model?

SYSTEM

Execution Models for VHDL Programs

Two classes of execution models govern the application of VHDL programs Simulation
discrete event simulation understanding is invaluable in debugging programs

MODULE + GATE

CIRCUIT

DEVICE G S n+ D n+

Synthesis
inference of hardware a function of the building blocks used for implementation
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The VHDL Language

V Very High Speed Integrated Circuit H Hardware D Description L Language

Interoperability between design tools: standardized portable model of electronic systems Technology independent description Reuse of components described in VHDL
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Outline
Entity Architecture Component Half Adder Full Adder

VHDL Quick Look

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VHDL
Very-High-Speed-Integrated-Circuits Hardware Description Language

VHDL Quick Look

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Entity Declarations
The primary purpose of the entity is to declare the signals in the designs interface
The interface signals are listed in the PORT clause
In this respect, the entity is similar to the schematic symbol for the component Syntax:
entity entity_name is
Port declaration;

Entity
end entity_name;

An entity declaration should starts with entity and ends with end keywords. In Port Out Port Inout Port Buffer Port - can be read - can be written - can be read and written - can be read and written, it can have only one source.
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Entity

Architecture

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Architecture Bodies
Describe the operation of the component Consist of two parts :
Declarative part -- includes necessary declarations
e.g. type declarations, signal declarations, component declarations, subprogram declarations

Syntax:
architecture architecture_name of entity_name is architecture_declarative_part; begin Statements; end architecture_name;

Statement part -- includes statements that describe organisation and/or functional operation of component
e.g. concurrent signal assignment statements, process statements, component instantiation statements

Here we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the begin and end keyword.
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Modelling
The implementation of an entity is done through set of interconnected components. The structural description of a design is simply a textual description of a schematic. It contains: Signal declaration. Component instances Port maps. Wait statements.
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Component

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Component declaration
Syntax:
component component_name List_of_interface ports; end component component_name;

Portmap
Port map is used to connect different components as well as connect components to ports of the entity. Component instantiation is done as follows. Component_label: component_name port map (signal_list); Example A0:and2 portmap(enable, temp, result); Signal_list is the architecture signals which we are connecting to component ports. This can be done in different ways. What we declared above is positional binding. One more type is the named binding. The above can be written as, A0 : and2 PORT MAP (in0 => enable, in1 => temp, out0 => result); A1 : and3 PORT MAP (in0 => x, in1 => y, in2 => enable, out0 => carry); X0 : xor2 PORT MAP (in0 => x, in1 => y, out0 => temp);

Before instantiating the component it should be declared using component declaration. Component declaration declares the name of the entity and interface of a component.

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Concept of signals
A signal is used to carry logic information. In hardware it is a wire. A signal can be in or out ..etc. There are many logic types of signals (wires)
Bit (can only have logic 1 or 0) Std_logic can be 1, 0 , Z ..etc. ( Z=float.) Std_logic_vector is a group of wires (called bus).
a, b: in std_logic_vector(3 downto 0); in VHDL
means a(0), a(1), a(2), a(3) are std_logic signals Same for b.
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VHDL Code For Half Adder

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Full Adder

Full Adder
library IEEE; use IEEE.STD_LOGIC_1164.all; entity FullAdder is port(A,B,Cin:in std_logic; SUM, CARRY:out std_logic); end FullAdder; architecture fa_arc of FullAdder is component HalfAdder port(A,B:in std_logic; S,C:out std_logic); end component; signal C1,C2,S1:std_logic; begin HA1: HalfAdder port map(A,B,S1,C1); HA2: HalfAdder port map(S1,Cin,SUM,C2); CARRY <= C1 or C2; end fa_arc; Library declaration

Entity declaration

Architecture

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Test bench
The test bench is used for generating stimulus for the unit under test(UUT).
entity tb_en is end tb_en;

Test bench
architecture tb_ar of tb_en is signal a_i,b_i,c_i,sum_i,carry_i:bit; begin --Instantiation of Unit Under Test (UUT) uut: FullAdder port map(A=>a_i,B=>b_i,Cin=>c_i,SUM=>sum_i,CARRY=>carry_i); stimulus: process begin a_i<='1';b_i<='1';c_i<='1'; wait for 10ns; a_i<='0';b_i<='1';c_i<='1'; wait for 10ns; a_i<='1';b_i<='0';c_i<='0'; wait for 10ns; wait; end process stimulus; end tb_ar;
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Example Schematic
A A1 B A_IN A B_IN B C_IN A A3 B Z INT3 A2 Z A INT2 B O1 C Z Z_OUT Z INT1

Example Structural VHDL Interface

-- Define the Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT; Z_OUT : out BIT); end MAJORITY;

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Design Entity - Component Relationship

Example VHDL Body

architecture STRUCTURE of MAJORITY is -- Declaration of components and local signals component AND2_OP port (A, B : in BIT; Z : out BIT); end component; component OR3_OP port (A, B, C : in BIT; Z : out BIT); end component; signal INT1, INT2, INT3 : BIT;

A1 A2 A3 O1

Instantiations Design entities Components

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Example VHDL Statement Part

begin -- Define the component connections A1: AND2_OP port map (A_IN, B_IN, INT1); A2: AND2_OP port map (A_IN, C_IN, INT2); A3: AND2_OP port map (B_IN, C_IN, INT3); O1: OR3_OP port map (INT1, INT2, INT3, Z_OUT); end STRUCTURE;

Port Map Associations

Positional association connects port identifiers to port map identifiers in order of occurrence Named association explicitly identifies the connection between port identifiers and port map identifiers
Association is port name => signal name left side: "formals" (port names from component declaration) right side: "actuals" (architecture signals) Associations can appear in any order

Both associations can appear in one port map

Positional before named
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