CONTENTS

TITLE PAGE NO.

Candidates Declaration Certificate Acknowledgement Contents List of Figures List of Tables List of Abbreviations List of Symbols Abstract 1. Introduction
1.1 Motivation 1.2 Objective 1.3 Organization of the Chapter 1.4 Tanner Tool Overview 1.4.1 S-Edit 1.4.2 T-Spice 1.4.3 W-Edit 1.4.4 L-Edit

i v x xi xii 1 2
2 3 4 4 5 5 5 5

2. Literature Survey

3. Basic of Multiplier
3.1 Basic Binary Multiplier 3.1.1 Partial Product Generation Methods 3.1.2 Accumulation 3.2 Multiplier Types 3.3 Array Multiplier 3.4 Wallace/ Dadda Multiplier 3.5 Modified Booth Multiplier 3.5.1 Architecture of Modified Booth Multiplier 3.5.2 Booth Encoder 3.5.3 Booth Decoder 3.5.4 Sign Extension Trick 3.5.5 Carry Lookahead Adder (CLA) 3.6 Hierarchical Array Multiplier
3.7 Vedic Multiplier

17
17 18
19

19 20 21 22 24 25 25 27 27 28 29 30
34

3.7.1 Urdhva Tiryagbhyam Multiplier 3.7.2 Nikhilam Sutra

4. Types of Adder
4.1 Basic Adders 4.2 Parallel Adders 4.2.1 Ripple Carry Adder 4.2.2 Carry Lookahead Adder

37
38 41 41 42

ii

4.2.3 Carry Select Adder 4.1.4 Carry Skip Adders 4.3 What type of adder is to be used?

44 46 48

5. Design and Simulation

5.1 Hierarchical Array Multiplier 5.1.1 2 X 2 bit Multiplier 5.1.2 4 X 4 bit Multiplier 5.1.3 8 X 8 bit Multiplier 5.1.4 16 X 16 bit Multiplier 5.2 Adders 5.2.1 Ripple Carry Adder 5.2.2 Carry Lookahead Adder 5.2.3 Carry Select Adder 5.2.4 Carry Skip Adder 5.3 Modified Booth Multiplier 5.4 Vedic Multiplier using Urdhva Tiryagbhyam (U.T.) Sutra 5.4.1 Design of 4 X 4 and 3 8 X 8 bit U.T. Type 1 Multiplier 5.4.2 Design of 16 X 16 bit U.T. Type 1 Multiplier 5.4.3 Design of 4 X 4 and 8 X 8 bit U.T. Type 2 Multiplier 5.4.4 Design of 16 X 16 bit U.T. Type 2 Multiplier 5.4.5 Design of Half Adder

49
49 50 52 52 53 54 55 57 58 59 60 63 64 65 67 68 69

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5.5 Vedic Multiplier using Nikhilam Sutra 5.5.1Design of 16 bit N.S. Type 1 Multiplier 5.5.2 Design of 16 bit N.S. Type 2 Multiplier 5.5.3 Design of 16 bit N.S. Type 3 Multiplier 5.5.4 Design of 16 bit N.S. Type 4 Multiplier

69 69 71 71 72

6. Result Analysis and Comparison

6.1 Simulation Result of Hierarchical Array Multiplier with different adder 6.1.1 Hierarchical Array Multiplier of 4 X 4 bit 6.1.2 Hierarchical Array Multiplier of 8 X 8 bit 6.1.3 Hierarchical Array Multiplier of 16 X 16 bit 6.2 Comparison of Different Multipliers 6.3 Nikhilam Sutra (N. S.) Multiplier result with Different Adder

73
73 73 77 81 85 89

7. Conclusion and Future Work

7.1 Conclusion 7.2 Future Work

94
94 95

References

xiii

iv

LIST OF FIGURES
FIGURE NO. DESCRIPTION OF FIGURE PAGE NO.

Chapter-3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 Generic multiplier block diagram Binary multiplication of 11 11 Generation logic of partial product Block diagram of 4 4 array multiplier Wallace multiplier Modified booth encoding Modified booth multiplier Gate level diagram of booth encoder Gate level diagram of booth decoder Block diagram of 12 bit CLA A 44 combinational multiplier A 88 combinational multiplier Line diagram for multiplication of two 4 bit numbers Multiplication of 232 323=74936 by U.T. sutra Architecture of 4 4 Vedic multiplier using U.T. Architecture of 16 16 Vedic multiplier using U.T. Different architecture of 16 bits U.T. multiplier Multiplication using Nikhilam sutra Architecture of 16 16 Vedic multiplier using N.S. 17 18 19 20 21 23 24 25 26 27 28 29 31 31 32 33 34 35 36

Chapter-4
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Half adder logic & block diagrams Full adder logic & block diagram Transmission gate based full adder circuit Block diagram of a 4 bit RCA Block diagram of a 4 bit CLA An N bit carry select adder Linear carry select adder Square root carry select adder Simple carry skip adder Adder structure using bypass concept 38 39 40 41 43 45 46 46 47 47

Chapter-5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Schematic block diagram of 22 bit HAM multiplier Schematic block diagram of 44 bit HAM multiplier Schematic block diagram of 88 bit HAM multiplier Schematic block diagram of 1616 bit HAM multiplier Block diagram of a 5 bit RCA Schematic block diagram of 1 bit mirror FA Schematic block diagram of 1 bit FA using T.G type 1 Schematic block diagram of 1 bit FA using T.G type 2 Schematic block diagram of 5 bit CLA Schematic block diagram of 5 bit CSLA 51 52 53 54 55 56 57 57 58 59

vi

5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27

Schematic block diagram of 5 bit CSKA Block diagram of 8 bit MBM Schematic block diagram of booth decoder Schematic block diagram of booth encoder Schematic block diagram of 12 bit CLA Block diagram of 16 bit MBM Block diagram of 4 bit U.T. type 1 multiplier Block diagram of 8 bit U.T. type 1 multiplier Block diagram of 16 bit U.T. type 1 multiplier Block diagram of 16 bit RCA Block diagram of 4 bit U.T. type 2 multiplier Block diagram of 8 bit U.T. type 2 multiplier Block diagram of 16 bit U.T. type 2 multiplier Schematic block diagram of 1 bit HA Block diagram of 16 bit N.S. type 1 multiplier Block diagram of 16 bit 2s complement Block diagram of 16 bit CSLA

59 60 61 62 62 63 64 65 66 66 67 68 68 69 70 70 71

Chapter-6
6.1 6.2 6.3 6.4 Power comparison of 4 bit HAM with different adders Delay comparison of 4 bit HAM with different adders PDP and EDP comparison of 4 bit HAM with adders Simulation time comparison of 4 bit HAM with adders 74 74 75 75

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6.5

Output of 4 4 bit HAM using (a) RCA (b) CLA (c) CSLA (d) CSKA (e) TG type 1 (f) TG type 2 77 78 78 79 79

6.6 6.7 6.8 6.9 6.10

Power comparison of 8 bit HAM with different adders Delay comparison of 8 bit HAM with different adders PDP and EDP comparison of 8 bit HAM with adders Simulation time comparison of 8 bit HAM with adders Output of 8 8 bit HAM using (a) RCA (b) CLA (c) CSLA (d) CSKA (e) TG type 1 (f) TG type 2

80 82 82 82 83 83 83

6.11 6.12 6.13 6.14 6.15 6.16 6.17

Power comparison of 16 bit HAM with different adders Delay comparison of 16 bit HAM with different adders PDP comparison of 16 bit HAM with different adders EDP comparison of 16 bit HAM with different adders Simulation time comparison of 16 bit HAM with adders Comparison of area in terms of transistor for HAM Output of 16 bit HAM using (a) RCA (b) CLA (c) CSLA (d) CSKA (e) TG type 1 (f) TG type 2

85

6.18

Output of 16 16 bit Multiplier (a) Modified Booth (b) U.T. type 1 (c) U.T. type 2 88 88 88 89 89 91

6.19 6.20 6.21 6.22 6.23

Comparison of power in different multiplier Comparison of delay in different multiplier Comparison of PDP in different multiplier Comparison of EDP in different multiplier Power comparison of 16 bit N.S. multiplier

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6.24 6.25 6.26 6.27

Delay comparison of 16 bit N.S. multiplier Comparison of PDP for 16 bit N.S. multiplier Comparison of EDP for 16 bit N.S multiplier Comparison of area in terms of transistor for 16 bit N.S. multiplier

91 91 92

92

6.28

Output of 16 16 bit Nikhilam sutra multiplier (a) type 1 (b) type 2 (c) type 3 (d) type 4 93

ix

LIST OF TABLES
TABLE NO. DESCRIPTION OF TABLE PAGE NO.

Chapter-3
3.1 3.2 3.3 Modified booth decoding scheme Booth encoder truth table Booth decoder truth table 23 25 26

Chapter-4
4.1 4.2 Half adder Full adder 39 40

Chapter-5
5.1 5.2 5.3 Basic parameter Truth table of 22 bit multiplier Truth table of booth encoder 49 50 61

Chapter-6
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Results of 4 bit HAM with different adders Results of 8 bit HAM with different adders Results of 16 bit HAM with different adders Comparison of 4 bit multipliers Comparison of 8 bit multipliers Comparison of 16 bit multipliers Results of 16 bit N.S. multiplier with different adders 73 77 81 85 86 86 90

LIST OF ABBREVIATIONS
ABBREVIATIONS BFA CLA CSKA CSLA DRC DSP EDP FA HA HAM LVS MBM N.S. PDP PP RCA TG U.T. VM DESCRIPTION Bit Full Adder Carry Lookahead Adder Carry Skip Adder Carry Select Adder Design Rule Checks Digital Signal Processing Energy Delay Product Full Adder Half Adder Hierarchical Array Multiplier Layout versus Schematic Modified Booth Multiplier Nikhilam Sutra Power Delay Product Partial Product Ripple Carry Adder Transmission Gate Urdhva Tiryagbhyam Vedic Mathematics

xi

LIST OF SYMBOLS
SYMBOL Cin Cout C0 S G D P V nm ns mW Sec J pJ Js DESCRIPTION Carry Input Carry Output Carry Sum Generate Delete Propagate Voltage Neno Meter Neno Second Mille Watts Second Micro Micro Joule Pico Joule Joule Second XOR

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REFERENCES
[1] Sumit Vaidya, Deepak Dandekar, Delay-Power performance comparison of multipliers in VLSI circuit design, International Journal of Computer Networks &

Communications (IJCNC), Vol.2, No.4, pp. 47-56, Jul. 2010. [2] Abhijit Asati, Chandrashekhar, A High-Speed, Hierarchical 1616 Array of Array Multiplier Design, International Conference on Multimedia, Signal processing and Communication Technologies (IMPACT), pp. 161-164, Mar. 2009. [3] Shamim Akhter, VHDL implementation of fast NN multiplier based on Vedic mathematic, 18th European Conference on Circuit Theory and Design, Sevilla Spain, pp. 472-475, Aug. 2007. [4] Dr. K.S. Gurumurthy, M.S Prahalad, Fast and Power Efficient 1616 Array of Array Multiplier using Vedic Multiplication, International Conference on Computational Intelligence and Multimedia Application, 2006. [5] Manoranjan Pradhan, Rutuparna Panda, Sushanta Kumar Sahu, Speed Comparison of 1616 Vedic Multipliers, International Journal of Computer Applications (0975 8887), Vol. 21, No.6, May 2011. [6] Parth Mehta, Dhanashri Gawali, Conventional versus Vedic mathematical method for Hardware implementation of a multiplier, International Conference on Advances in Computing, Control, and Telecommunication Technologies, Trivandrum Kerala, India, pp. 640-642, Dec. 2009. [7] Issam S. Abu-Khater, Abdellatif Bellaouar and M. I. Elmasry, Circuit Techniques for CMOS Low-Power High-Performance Multipliers, IEEE Journal of Solid-State Circuits, Vol. 31, No. 10, pp. 1535-1546, Oct. 1996. [8] Leandro Z. Pieper, Eduardo A. C. da Costa, Srgio J. M. de Almeida, Sergio Bampi, Jos C. Monteiro, Efficient Dedicated Multiplication Blocks for 2s Complement Radix-2m Array Multipliers, Journal of Computers, Vol. 5, No. 10, pp. 1502-1509, Oct. 2010.

xiii

[9]

Prabha S.Kasliwal, B.P.Patil and D.K.Gautam, Performance Evalution of squaring operation by vedic mathematics, IETE Journal of research, Vol. 57, Issue 1, pp. 39-41, jan-feb 2011.

[10] Jitendra Kumar Das and Dr. K. K. Mahapatra, Design of an Adaptive Hearing Aid Algorithm using Booth-Wallace Tree Multiplier, International Journal of Logic and Computation (IJLP), Vol. 1, Issue 1. [11] A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay, A 1.2-ns1616-Bit Binary Multiplier Using High Speed Compressors, International Journal of Electrical and Electronics Engineering, pp. 234-239, 2010. [12] Kanika Kaur and Arti Noor, Power Estimation Analysis for CMOS Cell Structures, International Journal of Advances in Engineering & Technology (IJAET), Vol. 3, Issue 2, pp. 293-301, May 2012. [13] Usha G.Chavan, Prof.P.P.Rane ,Optimized Multiplier Using Bypass Technique, The International Journal of Computer Science & Applications (TIJCSA), Vol. 1, No. 2, pp. 20-25, Apr. 2012. [14] Fayez Elguibaly, A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm, IEEE Transactions On Circuits And SystemsII: Analog And Digital Signal Processing, Vol. 47, No. 9, pp. 902-908, Sep. 2000. [15] Ramalatha M, Thanushkodi K, Deena Dayalan K, Dharani P, A Novel Time and Energy Efficient Cubing Circuit using Vedic Mathematics for Finite Field Arithmetic, International Conference on Advances in Recent Technologies in Communication and Computing, pp. 873-875, 2009. [16] Harpreet Singh Dhillon, abhijit Mitra, A Reduced Bit Multiplication Algorithm for Digital Arithmetic, International journal of Computational and Mathematical Sciences, spring, pp. 64-69, 2008. [17] Jung-Yup Kang, Jean-Luc Gaudiot, A Simple High-Speed Multiplier Design, IEEE Transactions on Computers, Vol. 55, No. 10, pp. 1253-1258, Oct. 2006.

xiv

[18] Jalil Fadavi-Ardekani, M x N Booth Encoded Multiplier Generator Using Optimizedn Wallace Trees, lEEE Transactions on Very- Large Scale Integration (Msl) Systems, Vol. 1, No. 2, pp. 120-125, Jun. 1993. [19] Aditya Kumar Singh, Bishnu Prasad De and Santanu Maity, Design and Comparison of Multipliers Using Different Logic Styles, International Journal of Soft Computing and Engineering (IJSCE), Vol. 2, Issue 2, pp. 374-379, May 2012. [20] Behnam Amelifard, Farzan Fallah, Massoud Pedram, Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-power High Performance Adders, IEEE International Symposium on Quality Electronic Design (ISQED), pp.148-152, 2005. [21] B. Sathiyabama, S. Malarkkan, Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application, International Journal of Computer Applications (0975 8887), Vol. 46, No.16, pp.16-20, May 2012. [22] Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics, Proceeding of the 2011 IEEE Students Technology Symposium 14-16, lIT Kharagpur, pp. 237-241,Jan. 2011. [23] Yuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang, Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias, IEEE Journal on Emerging and selected topics in circuits and systems, Vol. 1, No. 3, pp. 277- 288, Sep. 2011. [24] C.S. Wallace, A Suggestion for a Fast Multiplier, IEE Transactions on Electronic Computers, EC-13, p.14-17, 1964. [25] L. Dadda, Some Schemes for Parallel Multipliers, Alta Frequenza, Vol.34, p.349356, Mar. 1965. [26] A. D. Booth, "A Signed Binary Multiplication Technique", Qarterly J. Mechan. Appl. Math., Vol. 4, 1951.

xv

[27] Hanumantharaju M.C, Jayalaxmi .H, Renuka R.K, Ravishankar .M, A High Speed Block Convolution using Ancient Indian Vedic Mathematics, International Conference on Computational Intelligence and Multimedia Applications 2007, pp. 169173, 2007. [28] M. Ramalatha, K. Deena Dayalan, S. Deborah Priya, High Speed Energy Efficient ALU Design using Vedic Multiplication Techniques, ACTEA 2009, pp. 600-603, Jul. 15-17, 2009. [29] Sree Nivas A, Kayalvizhi N, Implementation of Power Efficient Vedic Multiplier, International Journal of Computer Applications (0975 8887), Vol. 43, No.16, pp. 2124, Apr. 2012. [30] Dr. Ravi Shankar Mishra, Prof. Puran Gour, Braj Bihari Soni, Design and Implements of Booth and Robertsons multipliers algorithm on FPGA, International Journal of Engineering Research and Applications (IJERA), ISSN: 2248-9622, Vol. 1, Issue 3, pp. 905-910. [31] Pushpalata Verma, Design of 4x4 bit Vedic Multiplier using EDA Tool, International Journal of Computer Applications (0975 888), Vol. 48 No.20, pp. 32-35, Jun. 2012. [32] Shiann-Rong Kuang, Jiun-Ping Wang, Design of Power-Efficient Configurable Booth Multiplier, IEEE Transactions On Circuits And SystemsI: Regular Papers, Vol. 57, No. 3, pp. 568-580, Mar. 2010. [33] Harpreet Singh Dhillon and Abhijit Mitra, A Digital Multiplier Architecture using Urdhva Tiryakbhyam Sutra of Vedic Mathematics, Indian Institute of Technology, Guwahati, Mar. 2010. [34] Divya Gupta, Ravindra Prakash Gupta, B.S.N.Raju, Analysis of Different CMOS Adders for Power, Speed and Area, IJECT (2230-9543), Vol. 2, Issue 4, pp.120-124, Oct.-Dec. 2011. [35] Anvesh kumar, Ashish raman, Dr.R.K.sarin, Dr.Arun Khosla, Small area Reconfigurable FFT Design by Vedic Mathematics, IEEE, Vol. 5, pp. 836-838, 2010.

xvi

[36] Akanksha Mandowara, Mukesh Maheshwari, Performance Analysis of Different Parallel CMOS Adders and Effect of Channel Width at 0.18um, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET),Vol.1, Issue 8, October 2012. [37] P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya, Vedic Mathematics Based 32Bit Multiplier Design for High Speed Low Power Processors, International Journal on Smart Sensing and Intelligent Systems, Vol. 4, No. 2, pp. 268-284, Jun. 2011. [38] Himanshu Thapliyal, Hamid R. Arabnia, A Time-Area- Power Efficient Multiplier and Square Architecture Based On Ancient Indian Vedic Mathematics, Department of Computer Science, The University of Georgia, 415 Graduate Studies Research Center Athens, U.S.A, pp. 434-439, Jun. 2004. [39] Ashish Raman, Anvesh Kumar and R.K.Sarin, High Speed Reconfigurable FFT Design by Vedic Mathematics, Journal of Computer Science and Engineering, Vol.1, Issue 1, pp. 59-63, May 2010. [40] Ramesh Pushpangadan, Vineeth Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundar High Speed Vedic Multiplier for Digital Signal Processors, IETE journal, Vol.55, Issue 6, pp. 282-286, Nov.-Dec. 2009. [41] Navdeep Goel, Lalit Garg, Comparative Analysis of 4-bit CMOS Multipliers, International Conference on VLSI, Communication & Instrumentation, pp. 33-37, 2011. [42] S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, Implementation of Vedic Multiplier for Digital Signal Processing, International Conference on VLSI Communication & Instrumentation (ICVCI), pp. 1-6, 2011. [43] V.Vamshi Krishna, S. Naveen Kumar, High Speed, Power and Area efficient Algorithms for ALU using Vedic Mathematics, International Journal of Scientific and Research Publications, Vol. 2, Issue 7, pp.1-6, Jul. 2012. [44] G.Ganesh Kumar, V.Charishma, Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques, International Journal of Scientific and Research Publications, Vol. 2, Issue 3, pp.1-5, Mar. 2012.

xvii

[45] D.G. Crawley, G.A.J. Amaratunga, 8 8 bit pipelined Dadda multiplier in CMOS, IEE Proceedings, Vol. 135, No. 6, pp. 231-240, Dec. 1988. [46] Addanki Purna Ramesh, Implementation of Dadda and Array Multiplier Architectures Using Tanner Tool, International Journal of Computer Science & Engineering Technology (IJCSET), Vol. 2, No. 2, pp. 28-41. [47] Dhireesha Kudithipudi and Eugene John, Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks, Journal of Low Power Electronics, Vol.1, No.3, pp.111, 2005. [48] Padma Devi, Ashima Girdher, Balwinder Singh, Improved Carry Select Adder with Reduced Area and Low Power Consumption, International Journal of Computer Applications (0975 8887), Vol. 3, No.4, pp. 14-18, Jun. 2010. [49] Abhijit Asati, Chandrashekhar, An Improved High Speed fully pipelined 500 MHz 8.8 Baugh Wooley Multiplier design using 0.6 m CMOS TSPC Logic Design Style, IEEE Region 10 Colloquium and the Third ICIIS, Kharagpur, INDIA, pp.1-6, Dec. 810. [50] Manoranjan Pradhan, Rutuparna Panda, Sushanta Kumar Sahu, MAC Implementation using Vedic Multiplication Algorithm, International Journal of Computer Applications (0975 8887), Vol. 21 No.7, pp. 26-28, May 2011. [51] Razaidi Hussin, Ali Yeon Md. Shakaff, Norina Idris, Zaliman Sauli, Rizalafande Che Ismail and Afzan Kamarudin, An Efficient Modified Booth Multiplier Architecture, International Conference on Electronic Design, Penang, Malaysia, pp. 1-4, Dec. 2008. [52] Kiamal Z. Pekmestzi, Multiplexer-Based Array Multipliers, IEEE Transactions on Computers, Vol. 48, No.1, pp.15-23, Jan. 1999. [53] Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho, Multiplier design based on ancient Indian Vedic Mathematics, International SoC Design Conference, pp. 65-68, 2008.

xviii

[54] Ramachandran.S, Kirti.S.Pande, Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture, International Journal of Computational Engineering Research (IJCER), Vol. 2, Issue No.3, pp.697-703, May-June 2012. [55] V. Chandramouli,Erik Bmnvand and Kent F. Smith, Self-Timed Design in GaAs Case Study of a High-speed, Parallel Multiplier, IEEE Transactions on VLSI Systems, Vol. 4, No.1, Mar. 1996. [56] M.E.Paramasivam, Dr.R.S.Sabeenian, An Efficient Bit Reduction Binary

Multiplication Algorithm using Vedic Methods, IEEE 2nd International Advance Computing Conference, pp.25-28, 2010. [57] V Jayaprakasan, S Vijayakumar, V S Kanchana Bhaaskaran, Evaluation of the Conventional vs. Ancient Computation methodology for Energy Efficient Arithmetic Architecture, IEEE, 2011. [58] Laxman P.Thakre, Suresh Balpande, Umesh Akare, Sudhir Lande, Performance Evaluation and Synthesis of Multiplier used in FFT operation using Conventional and Vedic algorithms, Third International Conference on Emerging Trends in Engineering and Technology, pp. 614-619, 2010. [59] S.Saravanan, M.Madheswaran, Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme, International Journal of Computer Science and Information Security (IJCSIS), Vol. 6, No. 3, pp.73-78, 2009.

[60] Umesh Akare, T. V. More, R. S. Lonkar, Performance Evaluation and Synthesis of Vedic Multiplier, Proceedings published by International Journal of Computer Applications (IJCA), pp. 20-23, 2012. [61] N.Ravi, Dr.T.S.Rao, Dr.T.J.Prasad, Performance Evaluation of Bypassing Array Multiplier with Optimized Design, International Journal of Computer Applications (0975 8887), Vol. 28, No.5, pp.1-5, Aug. 2011.

xix

[62] Ravi Nirlakalla, Thota Subba Rao, Talari Jayachandra Prasad, Performance Evaluation of High Speed Compressors for High Speed Multipliers, Serbian Journal Of Electrical Engineering, Vol. 8, No. 3, pp. 293-306, Nov. 2011. [63] G. Bewick, Fast Multiplication: Algorithm and Implementation, PhD. Thesis, Stanford University, 1994. [64] Gensuke Goto, Atsuki Inoue, Ryoichi Ohe, Shoichiro Kashiwakura, Shin Mitarai, Takayuki Tsuru, and Tetsuo Izawa, A 4.1-ns Compact 54 54-b Multiplier Utilizing Sign-Select Booth Encoders, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1676-1682, Nov. 1997. [65] Rizwan Mudassir, Mohab Anis and Javid Jaffari, Switching Activity Reduction in Low Power Booth Multiplier, IEEE, pp. 3306-3309, 2008. [66] Sudhanshu Mishra, Manoranjan Pradhan, Synthesis Comparison of Karatsuba Multiplier using Polynomial Multiplication, Vedic Multiplier and Classical Multiplier, International Journal of Computer Applications (0975 8887), Vol. 41, No. 9, pp.1317, Mar. 2012. [67] Hesham A. Al-Twaijry, Michael J. Flynn, Technology Scaling Effects on Multipliers, IEEE Transactions on Computers, Vol. 47, No. 11, pp.1201-1215, Nov. 1998. [68] A. R. Fridi, Partial multiplication: A low-power approach for parallel multiplier, ECE729 Course Project, Dept. Electrical and Computer Eng., Univ. Waterloo, Apr.1994. Books [69] Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, Digital integrated circuits: a design perspective, Pearson Education, 2003 [70] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic mathematics, Motilal Banarsidass Publishers Pvt Ltd, Delhi, 2009 [71] Israel Koren, Computer Arithmetic Algorithms, Prentice Hall, 2001.

xx

[72] B. Parhami, Computer Arithmetic, Algorithm and Hardware Design, Oxford University Press, New York, pp.91-119, 2000. [73] M. Morris Mano, Digital Design, Pearson Education Asia, 2002. [74] Peter Pirsch, Architectures for digital signal processing, John Wiley & Sons, 1998. [75] Neil H.E.Weste, David Harris, Ayan Banerjee, CMOS VLSI Design- A Circuits and Systems Perspective, Pearson Education, 2006. [76] John P.Uyemura, CMOS Logic Circuit Design, Kluwer Academic publishers, Dordrecht, 1992. Paper Published [77] Arushi Somani, Dheeraj Jain, Sanjay Jaiswal, Kumkum Verma, Swati Kasht, Compare Vedic Multipliers with Conventional Hierarchical array of array multiplier, International Journal of Computer Technology and Electronics Engineering (IJCTEE), Vol. 2, Issue 6, pp. 52-55, Dec. 2012.

xxi