1. Implement the following using CMOS logic.

For PUN(Top) P-MOSS (with circle at input) AND Parallel OR - series For PDN(bottom) N-MOSS(no circle) And series OR - parallel 2. Using Boolean algebra or otherwise prove the consensus theorem. (i) XY + YZ +XZ = XY + XZ LHS = XY +XZ + (X+X)YZ = XY+XZ +XYZ +XYZ = XY(1+Z)+XZ(1+Y) = XY+XZ = RHS (ii) (X+Y)(Y+Z)(X+Z)=(X+Y)(X+Z) (XY) + (YZ) + (XZ) = (XY) + (XZ) XY + YZ +XZ = XY + XZ then follow above. 3. Mealy Machine Design. make mealy state diagram (circles with states and arrows for Input/output) present state/next state/ output chart Guidelines (I) States with same next state for a given input, (II)States that are next states of the same state, (III) States that have the same output for a given input. Assignment map transition table K maps for JKFFs and output eqns. Ex.(use 1s for output k map.)

4. Clocked D flip flop, triggered on the rising edge of CLK using transparent D latches & necessary gates. Complete the following timing diagram etc.

5. Describe the design flow of modern digital system design and discuss the scope of VHDL in the CAD/Design automation industry Requirements RTL model synthesizeGate-level Model place and route timing model/ ASIC or FPGA while simulating and testing with test bench in between each step to ensure proper behavior. 6.VHDL module for JK flip flop with (i) 2 inputs J and K, (ii) 2 synchronous preset(S) and Clear(R) inputs , (iii)2 outputs Q and QN. entity JKFF is Process(S, R, CLK) port (S, R, J, K, CLK: in bit; begin Q, QN: out bit); if R = 0 then Qint <= 0 after 8 ns; end JKFF; elsif S = 0 then Qint <= 1 after 8ns; architecture JKFF1 of JKFF is elsif CLKevent and CLK = 1 then signal Qint: bit; Qint <= (J and not Qint) or (not K and Qint) after 10 ns; begin end if; Q <= Qint; end process; QN <= not Qint; end JKFF1; 7. Inertial Delays are intended to model gates and other devices that do not propagate short pulses from the input to the output. Transparent Delays are intended to model the delay introduced by wiring, simply delays an input signal by specified time.

8.What are the different predefined data types in VHDL? - bit 0 or 1 -boolean TRUE or FALSE -Integer An integer in the range (2E31 1) to +(2E31 1) -Real floating point number in the range -1.0E38 to +1.0E38 9.What are the different predefined operators in VHDL? - Binary logical operators and, or, nand, nor, xor, xnor - Relational operators - =, /=, <, <=, >, >= - Shift Operators sll, srl, sla, rol, ror - Adding operators - +, -, &(concatenation)

-Character Any legal VHDL character including upper and lower case letters, digits, and special characters (each must be enclosed in single quotes eg d or 7) -time an integer with units fs, ps, ns, us, ms, sec, min, or hr

- Unary sign operatos - +, - Multiplying operators - *, /, mod, rem - Miscellaneous operators not, abs, **

10. In the following VHDL code A, B, C, and D are all integers that are 0 at time 10 ns. If D changes to 1 at 20 ns specify the times at which A, B, and C will change and the values they will take. process(D) B<= A + 1; ---executes before A changes. begin C <= B after 10 ns; ---executes before B changes. A <= 1 after 5ns; end process; C does not change, B = 1 at 20 + delta ns, A = 1 at 25ns. 11. A DD flip flop except the flip flop can change state (Q+ = D) on both the rising edge and the falling edge of the clock input. The flip flop has a direct reset input, R, and R = 0 resets the flip flop to Q = 0 independent of the clock. Similarly it has a direct set input, S, that sets the flip flop to 1 independent of the clock. Write a VHDL description of a DD flip-flop. Entity DDFF is process(Clk, R, S) elsif Clkevent port (R, S, D, Clk: in bit; begin then Q <= D; Q: out bit); if R = 0 then endif; end DDFF Q <= 0; end process; architecture Behav of DDFF is elsif S = 0 end Behav; begin then Q <= 1; 12. Assuming B is driven by the simulator command Draw a timing diagram illustrating A, B and C if the following concurrent statements are executed.

Force B 0 0, 1 10, 0 15, 1 20, 0 30, 1 35 A <= transport B after 5ns; C <= B after 8 ns; 14.(a)If gate delays are 5ns, what is the delay of the fastest 4 bit ripple carry adder explain calculations. (b)Fastest 4 bit adder (using gates). (a) 1 bit adder = 2(5) = 10ns. 4 bit ripple carry adder delay = 4(10) = 40ns.(b) = 2(5) = 10ns. This is a 2 level sum of products adder that just uses combinational logic. 15. 16 bit carry look ahead adder utilizing the 4-bit adder from fig 4-10 as a component entity CLA16 is signal C: bit_vector (3 downto 1); port(A, B: in bit_vector (15 downto 0); Ci: in bit; alias A0: bit_vector(3 downto 0) is A(3 downto 0); S: out bit_vector(15 downto 0); Co, PG, GG: out bit); alias A1: bit_vector(3 downto 0) is A(7 downto 4); end CLA16; alias A2: bit_vector(3 downto 0) is A(11 downto 8); archetecture Structure of CLA16 is alias A3: bit_vector(3 downto 0) is A(15 downto 12); component CLA4 is alias B0: bit_vector(3 downto 0) is B(3 downto 0); port(A, B: in bit_vector (3 downto 0); Ci: in bit; alias B1: bit_vector(3 downto 0) is B(7 downto 4); S: out bit_vector(3 downto 0); Co, PG, GG: out bit); alias B2: bit_vector(3 downto 0) is B(11 downto 8); end component; alias B3: bit_vector(3 downto 0) is B(15 downto 12); component GPFullAdder begin port(X, Y, Cin: in bit; CaryLogic: CLALogic port map (G, P, Ci, C, Co, PG, GG); G, P, Sum: out bit); CLAa: CLA4 port map(A0, B0, Ci, S0, open, P(0), G(0)); end component CLAb: CLA4 port map(A1, B1, C(1), S1, open, P(1), G(1)); component CLALogic is CLAc: CLA4 port map(A2, B2, C(2), S2, open, P(2), G(2)); port(G, P:in bit_vector(3 downto 0); Ci: in bit; CLAd: CLA4 port map(A3, B3, C(3), S3, open, P(3), G(3)); C: out bit_vector(3 downto 1); Co, PG, GG: out bit); S <= S3 & S2 & S1 & S0; end component; end Structure; signal s0, s1, s2, s3, G, P: bit_vector(3 downto 0); 16.Derive the generates, propogates, the final sum and carry out for a 4 bit CLA. Generates for any bit position i carry will be generated if Ai = 1, Bi = 1 therefore Gi = AiBi Propogates there is a carry in to that bit and at least one of Ai and Bi are 1. Therefore Pi = (AiBi) Carry out - Ci +1 = Gi+PiC i Sum = AiBi Ci 17. 16x16 array multiplier. For any (m x n) array multiplier # and gates = n^2

# Full adders = n(n-2)

# half adders = n
Clk 0 1 1 D X 0 1 Q Q No change No Change 0 1 1 0

18.Explain the idea behind the working of the D latch. Show truith table & circuit implementation. - Level sensitive and transparent. Output depends on clock Clk high: Input passes to output. Clk low: Latch holds its output.

19.Discuss different delays relevant in a sequential circuit. Propagation Time that elapses from the time the clock changes to the time the Q output changes. tphl The propagation delay from high to low tplh The propagation delay from low to high - setup time(tsu) time input D must be stable before the active edge of the clock. - Hold time(th) Time input D must be stable after the active edge of the clock. 20. Implement the following using only NAND gates. ------NAND logic

21. Describe the different levels of abstraction in digital design using a suitable example. -Behavioral Algorithmic, Dataflow. -Structural components interconnections -Physical Implementation 22. Write a complete VHDL module for 4 1 MUX using WHEN statement. Library IEEE; bitout : out std_logic); use IEEE.STD_LOGIC_1164.ALL; end multiplexer4_1; entity multiplexer 4_1 is architecture Behavioral of multiplexer 4_1 is port( i0 : in std_logic; begin i1 : in std_logic; process (i0, i1, i2, i3, sel) i2 : in std_logic; begin i3 : in std_logic; case sel is sel : in std_logic_vector (1 downto 0); when 00 => bitout <= i0; 23.Write a complete VHDL module for a 4 bit unsigned Number Comparator. entity compare is begin port( num1 : in std_logic_vector (3 downto 0); if (num1 > num2) then num2: in std_logic_vector (3 downto 0); less <= 0; less, equal, greater : out std_logic); equal <= 0; end compare; greater <= 1; architecture Behavioral of compare is elsif (num1 < num2) then begin less <= 1; process (num1, num2) equal <= 0;

when 01 => bitout <= i1; when 10 => bitout <= i2; when 11 => bitout <= i3; end case; end process; end Behavioral;

greater <= 0; else less <= 0; equal <= 1; greater <= 0; end if; end process; end Behavioral;