CISC vs RISC By Armin Gerritsen - Which one is better? RISC vs CISC is a topic quite popular on the Net.

Everytime Intel (CISC) or Apple (RISC) introduces a new CP ! the topic pops up a"ain. #ut what are CISC and RISC e$actly! and is one o% them really &etter' (his article tries to e$plain in simple terms what RISC and CISC are and what the %uture mi"ht &rin" %or the &oth o% them. (his article is &y no means intended as an article pro)RISC or pro) CISC. *ou draw your own conclusions + CISC Pronounced sisk, and stands %or Comple$ Instruction Set Computer. ,ost PC-s use CP &ased on this architecture. .or instance Intel and A,/ CP -s are &ased on CISC architectures. (ypically CISC chips have a lar"e amount o% di%%erent and comple$ instructions. (he philosophy &ehind it is that hardware is always %aster than so%tware! there%ore one should ma0e a power%ul instructionset! which provides pro"rammers with assem&ly instructions to do a lot with short pro"rams. In common CISC chips are relatively slow (compared to RISC chips) per instruction! &ut use little (less than RISC) instructions. RISC Pronounced risk, and stands %or Reduced Instruction Set Computer. RISC chips evolved around the mid)1234 as a reaction at CISC chips. (he philosophy &ehind it is that almost no one uses comple$ assem&ly lan"ua"e instructions as used &y CISC! and people mostly use compilers which never use comple$ instructions. Apple %or instance uses RISC chips. (here%ore %ewer! simpler and %aster instructions would &e &etter! than the lar"e! comple$ and slower CISC instructions. 5owever! more instructions are needed to accomplish a tas0. An other advanta"e o% RISC is that ) in theory ) &ecause o% the more simple instructions! RISC chips require %ewer transistors! which ma0es them easier to desi"n and cheaper to produce. .inally! it-s easier to write power%ul optimised compilers! since %ewer instructions e$ist.

RISC vs CISC (here is still considera&le controversy amon" e$perts a&out which architecture is &etter. Some say that RISC is cheaper and %aster and there%or the architecture o% the %uture. 6thers note that &y ma0in" the hardware simpler! RISC puts a "reater &urden on the so%tware. So%tware needs to &ecome more comple$. So%tware developers need to write more lines %or the same tas0s.

(here%ore they ar"ue that RISC is not the architecture o% the %uture! since conventional CISC chips are &ecomin" %aster and cheaper anyway. RISC has now e$isted more than 14 years and hasn-t &een a&le to 0ic0 CISC out o% the mar0et. I% we %or"et a&out the em&edded mar0et and mainly loo0 at the mar0et %or PC-s! wor0stations and servers I "uess a least 789 o% the processors are &ased on the CISC architecture. ,ost o% them the $3: standard (Intel! A,/! etc.)! &ut even in the main%rame territory CISC is dominant via the I#,;<24 chip. =oo0s li0e CISC is here to stay + Is RISC than really not &etter' (he answer isn-t quite that simple. RISC and CISC architectures are &ecomin" more and more ali0e. ,any o% today-s RISC chips support >ust as many instructions as yesterday-s CISC chips. (he PowerPC :41! %or e$ample! supports more instructions than the Pentium. *et the :41 is considered a RISC chip! while the Pentium is de%initely CISC. .urther more today-s CISC chips use many techniques %ormerly associated with RISC chips. So simply said? RISC and CISC are "rowin" to each other. x86 An important %actor is also that the $3: standard! as used &y %or instance Intel and A,/! is &ased on CISC architecture. @3: is thA standard %or home &ased PC-s. Bindows 28 and 23 won-t run at any other plat%orm. (here%ore companies li0e A,/ an Intel will not a&andonin" the $3: mar0et >ust overni"ht even i% RISC was more power%ul. Chan"in" their chips in such a way that on the outside they stay compati&le with the CISC $3: standard! &ut use a RISC architecture inside is di%%icult and "ives all 0inds o% overhead which could undo all the possi&le "ains. Nevertheless Intel and A,/ are doin" this more or less with their current CP -s. ,ost acceleration mechanisms availa&le to RISC CP s are now availa&le to the $3: CP -s as well. Since in the $3: the competition is 0illin"! prices are low! even lower than %or most RISC CP -s. Althou"h RISC prices are droppin" also a! %or instance! S N ltraSPARC is still more e$pensive than an equal per%ormin" PII wor0station is. Equal that is in terms o% inte"er per%ormance. In the %loatin" point)area RISC still holds the crown. 5owever CISC-s 7th "eneration $3: chips li0e the C7 will catch up with that. (he one e$ception to this mi"ht &e the Alpha ED):. (hose machines are overall a&out twice as %ast as the %astest $3: CP availa&le. 5owever this Alpha chip costs a&out EF4444! not somethin" you-re willin" to pay %or a home PC. ,ay&e interestin" to mention is that it-s no coincidence that A,/-s C7 is developed in co) operation with Alpha and is %or al lar"e part &ased on the same Alpha ED): technolo"y. EPIC (he &i""est threat %or CISC and RISC mi"ht not &e eachother! &ut a new technolo"y called EPIC. EPIC stands %or E$plicitly Parallel Instruction Computin". =i0e the word parallel already says EPIC can do many instruction e$ecutions in parallel to one another. EPIC is a created &y Intel and is in a way a com&ination o% &oth CISC and RISC. (his will in theory allow the processin" o% Bindows)&ased as well as NI@)&ased applications &y the same CP .

It will not &e until F444 &e%ore we can see an EPIC chip. Intel is wor0in" on it under code)name Merced. ,icroso%t is already developin" their Bin:G standard %or it. =i0e the name says! ,erced will &e a :G)&it chip. I% Intel-s EPIC architecture is success%ul! it mi"ht &e the &i""est thread %or RISC. All o% the &i" CP manu%actures &ut Sun and ,otorola are now sellin" $3:)&ased products! and some are >ust waitin" %or ,erced to come out (5P! SHI). #ecause o% the $3: mar0et it is not li0ely that CISC will die soon! &ut RISC may. So the %uture mi"ht &rin" EPIC processors and more CISC processors! while the RISC processors are &ecomin" e$tinct. Conclusion (he di%%erence &etween RISC and CISC chips is "ettin" smaller and smaller. Bhat counts is how %ast a chip can e$ecute the instructions it is "iven and how well it runs e$istin" so%tware. (oday! &oth RISC and CISC manu%acturers are doin" everythin" to "et an ed"e on the competition. (he %uture mi"ht not &rin" victory to one o% them! &ut ma0es &oth e$tinct. EPIC mi"ht ma0e %irst RISC o&solete and later CISC too. Written by A.A.Herritsen for the CPU Site March '99