Acer Aspire 5517 5532 Compal La 5481p

A
Compal Confidential
NCWG0/H0 Schematics Document

AMD S1g1 / RS780MN/ SB710
2009 / 06 / 24
LA-5481
Rev:1.0
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Wednesday, June 24, 2009
Rev
C
401743
Sheet
E
of
47
Compal confidential
Project Code: NCWG0/H0
File Name : LA-5481P
Clock Generator
SLG8SP626
ICS9LPRS488BKLFT
Thermal Sensor
ADM1032ARM
page 8
AMD S1g1 CPU

638P PGA
DDRII 533/667/800
DDRII-SO-DIMM X2
page 10,11
page 6,7,8,9
Dual Channel
page 17
H_A#(3..31)
H_D#(0..63)
HT 16x16 1000MHZ
CRT
ATI-RS780MN
page 24
465 BGA
LCD CONN
page 12,13,14,15,16
page 25
A-Link Express
4 x PCIE
PCIE X1
USB 2.0
C
Mini card
WLAN
ATI-SB710
10/100 LAN
AR8114 / AR8132
page 31
Camera
USB conn
X2
CardReader
RTS5159
549 BGA
page 26
HD Audio
HDA Codec
ALC272
page 18,19,20,21,22
page 39
AMP & Audio Jack
TPA6017
page 40
MDC Conn.
page 41
RJ45 CONN
HeadPhone
Out
page 27
SATA0
HDD Conn.
page 23
LPC BUS
MIC In
SATA2
ODD Conn.
page 23
ENE KB926
Ver:D3
Power On/Off CKT / LID switch / Power OK CKT
page 28
page 37
Second HDD/ODD
DC/DC Interface CKT.
CIR/LED
RTC CKT.
page 41
page 38
page 18
Int. KBD
page 29
Touch Pad
CONN. page
Power Circuit DC/DC
29
SPI BIOS
SATA1
HDD Conn.
SATA3
ODD Conn.
page 30
page 42~48
2009/03/08
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
of
47
SIGNAL
STATE
Voltage Rails
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Full ON
VIN
Adapter power supply (19V)
B+
AC or battery power rail for power circuit.
+CPU_CORE
Core voltage for CPU
+0.9V
0.9V switched power rail for DDR terminator
+1.2V_HT
1.2V switched power rail
ON
OFF
OFF
+1.5VS
ON
+1.8V
1.8V power rail for DDR
ON
OFF
+1.8VS
+2.5VS
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Board ID / SKU ID Table for AD channel
ON*
Vcc
Ra/Rc/Re
OFF
Board ID
0
1
2
3
4
5
6
7
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
External PCI Devices

Device
IDSEL#
REQ#/GNT#
Interrupts
PCB Revision
No Support VaryBright
Support VaryBright
BTO Option Table

BTO Item
10/100 Lan
GIGA Lan
17" ID
15" ID
Support VaryBright
BOM Structure
8114@
8132@
17@
15@
VARY@
EC SM Bus1 address
Device
Address
Smart Battery
0001 011X b
Device
ADM1032
SB600 SM Bus 1 address
EC SM Bus2 address
Device
Address
Clock Generator
1101 001Xb
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
PROJECT ID Table
Address
SKU ID
0
1
2
3
4
5
6
7
1001 100X b
SB600 SM Bus 2 address

Device
SKU
NCWG0
NAL00
NCWH0
Address
New Card
A
Wireless Lan
2009/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
of
47
DIMMA
DDR_A_CLK[1..2]
CPU
S1G1
SOCKET
200MHZ
H_CLKI[1:0]
DIMMB
CPU CLK
DDR_B_CLK[1..2]
Host Bus
H_CLKO[1:0]
SBLINK_CLK
100MHZ
NBSRC_CLK
14.31818MHz
ATI
NB
RS780MN
100MHZ
EXTERNAL
CLK GEN.
SLG8SP626 / ICS9LPRS488
HTREFCLK
66MHZ
NB_OSC
14.318MHZ
CLK_14M_SB
14.318MHZ
SB_OSCIN
CLK_PCIE_LAN
100MHZ
100MHZ
CLK_PCIE_MINI
14.318MHZ
ATI
SB
SB710
SBSRC_CLKP
100MHZ
CLK_PCI_LPC
CLK_48M_USB
EC
ENE
KB926D3
33MHZ
48MHZ
RTC
Mini PCI Socket

Mini card
A
SATA
32.768K Hz
LAN
Atheros
AR8114/AR8132
32.768K Hz
25M Hz
A
2005/10/10
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
of
47
AMD CPU
S1G1 socket
+2.5VS
PU21
APL5915KAI
AC ADAPTOR
19V 65W
BATTERY
11.1V
2.2Ah/6-cell
PU12
ISL6264CRZ-T
VIN
+CPU_CORE
BATT+
+1.2VALW
U46
AO4430
+1.2V_HT
VDDA
2.5V
250 mA
VDD
0.9V
0.95V
24.5 A
VDDIO
1.8V
3.6 A
VTT
0.9V
1.75 A
VLDT
1.2V
500 mA
+NB_CORE
PU17
BATTERY CHARGER
BQ24751ARHDR
PU18
ISL6228HRTZ-T
B+
DDRII SODIMMX2
+1.2VALW
+1.8V
+0.9V
PU22
APL5331KAC
VDD_MEM
1.8V
6.08 A
VTT_MEM
0.9V
500 mA
NB
RS780MN
VDDC
+1.2VALW
+1.8V
PU19
TPS51117RGYR
+3VS
1.0-1.1V
680 mA
PLLVDD
1.1V
VDDPCIE
2.5 A
VDDHTTX
+3VALW
PU16
ISL6237IRZ-T
U37
AO4430
VDDA18PCIE
+5VS
15 mA
3.3V
SB
+1.2V_HT
110 mA
60 mA
SB710
VDD
510mA
S5_1.2V
113 mA
USB_PHY_1.2V
197 mA
EC
ENE KB926
+3.3VALW 30mA
+3.3VS 3mA
+3.3VS 300mA
LAN
Atheros AR8114
Mini Card
ICS9LPRS488B
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
+3.3VALW 201mA
Audio Codec
ALC272
+5V 25mA
+5V 45mA
+5V 3A
+3.3VS 25mA
+3.3V
PCIE_PVDD
43 mA
PCIE_VDDR
600 mA
AVDD_SATA
567 mA
PLLVDD_SATA_1
93 mA
S5_3.3V
32 mA
AVDDC
17 mA
658 mA
3.3V
VDDQ
+1.2V
131 mA
VDD33_18
71 mA
AVDDCK_3.3V
47 mA
XTLVDD_SATA
RTC
Bettary
Audio AMP
TPA6017A2
62 mA
AVDD TX/RX
+3.3V 400mA
6 mA
VBAT
3V
SATA
Compal Secret Data

2009/3/8
Issued Date
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
1.2V
CKVDD_1.2
Realtek
RTS5159
+5VS 500mA
hexainf@hotmail.com
GRATIS - FOR FREE
300 mA
AVDD
AVDDCK_1.2V
FAN Control
APL5607
+3.3 350mA
10 mA
VDD33
B+ 300mA
120 mA
VDDLTP18
LCD panel
15.6"
700 mA
VDDLT18
+3VS
+5V
Dual
1.5A
20 mA
VDD18
+USB_VCCA
USB X2
20 mA
1.8V
VDDA18PCIEPLL
+3VS
U7
AO4468
20 mA
VDDA18HTPLL
+1.5VS
+5VS
4 mA
PLLVDD18
U41
AO4468
400 mA
AVDDDI
+5VALW
U4
TPS2061DRG4
680 mA
1.2V
AVDDQ
+1.8VS
PU23
APL5915KAI
65 mA
VDDHTRX
+1.2VALW
+1.8V
10 A
VDD_HT
PU20
+1.1VS
APL5912
KAC-TRL
of
47
<12> H_CADIP[0..15]
<12> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
H_CADOP[0..15]
<12>
H_CADON[0..15]
<12>
+1.2V_HT
JCPU1A
check AMD
<12>
<12>
H_CTLIP1
H_CTLIN1
<12>
<12>
2
20_0402_5%
0_0402_5%
2
4.7U_0805_10V4Z
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
H_CTLIP1_R P3
H_CTLIN1_R P4
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H1
L0_CTLOUT_L1
T5 H_CTLOP1_R
R5 H_CTLON1_R
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLOUT_H0
L0_CTLOUT_L0
R2
R3
N1
P1
FAN1 Conn
+5VS
1
R733
D13
1SS355_SOD323-2
2
@
U1
1
2
3
4
+VCC_FAN1
<28> EN_DFAN1
10U_0805_10V4Z
1
2
<BOM Structure>
R247
0_0603_5%
@
2
0_0402_5% 1
C760
EN
VIN
VOUT
VSET
8
7
6
5
GND
GND
GND
GND
+3VS
0.01U_0402_25V4Z
R37
10K_0402_5%
2
40mil
JP12
+VCC_FAN1
1
2
3
<28> FAN_SPEED1
1
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
1
R41 1
R44
H_CTLOP0
H_CTLON0
CONN@
ACES_85205-03001
C91
1000P_0402_50V7K
<12>
<12>
<12>
<12>
LDO FAN
+3VS
2
2 0_0402_5%
0_0402_5%
R40
10K_0402_5%
@
H_CTLOP1 <12>
H_CTLON1 <12>
<28> FANPWM
JP38
+VCC_FAN1
1
2
3
4
FANPWN
H_CTLOP0 <12>
H_CTLON0 <12>
1
2
3
4
CONN@
ACES_85205-0400
FOX_PZ63823-284S-41F
CONN@
Athlon 64 S1
Processor Socket
C96
1000P_0402_50V7K
1
2
<BOM Structure>
@D4
@
D4 BAS16_SOT23-3
1
2
C97
10U_0805_10V4Z
1
2
APL5607KI-TRG_SO8
Reserve when PVT

for cos down
+5VS
C92
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
Y4
Y3
Y1
W1
H_CTLIP0
H_CTLIN0
H_CTLIP0
H_CTLIN0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
C84
J5
K5
J3
J2
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
1
R45 1
R46
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
AE5
AE4
AE3
AE2
<12>
<12>
<12>
<12>
N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
D4
D3
D2
D1
HTT Interface
VLDT=500mA
PWM FAN
+1.2V_HT
R2
R3
@
@
2
2
1 51_0402_1%
1 51_0402_1%
H_CTLIP1_R
H_CTLIN1_R
AMD : 49.9 1%
ATI : 51 1%
+1.2V_HT
VLDT CAP.
250 mil
C86
4.7U_0805_10V4Z
2
<BOM Structure>
C82
4.7U_0805_10V4Z
C90
0.22U_0603_16V4Z
C89
0.22U_0603_16V4Z
C83
180P_0402_50V8J
<BOM Structure>
C85
180P_0402_50V8J
<BOM Structure>
<BOM Structure>
Near CPU Socket

A
Compal Secret Data
2007/5/18
Issued Date
2010/03/12
Deciphered Date
Title

SCHEMATIC, MB A5481
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
Rev
C
401743
Sheet

1
of
46
Processor DDR2 Memory Interface

<11> DDR_B_D[63..0]
2
R4
1K_0402_1%
(15/20, <6")
C100
1000P_0402_50V7K
R5
1K_0402_1%
C16
0.1U_0402_16V4Z
+CPU_M_VREF
+CPU_M_VREF
JCPU1B
VTT_SENSE
TP1
+1.8V
<10>
<10>
<10>
<10>
<11>
<11>
<11>
<11>
(10/10, <1")
R7
R6
1
2
2
1 39.2_0402_1%
39.2_0402_1%
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
<11> DDR_CKE1_DIMMB
<11> DDR_CKE0_DIMMB
<10> DDR_CKE1_DIMMA
<10> DDR_CKE0_DIMMA
<10> DDR_A_MA[15..0]
Y10
M_ZN AE10
M_ZP AF10
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
V19
J22
V22
T19
+0.9V
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
Y16
AA16
E16
F16
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
AF18
AF17
A17
A18
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0
W23
W26
V20
U19
DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0
M_VREF
VTT_SENSE
M_ZN
M_ZP
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
DDRII Cmd/Ctrl//Clk
W17
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
<10>
<10>
<10>
<10>
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
<11>
<11>
<11>
<11>
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
Y26
J24
W24
U23
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
H26
J23
J20
J21
MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
K22
R20
T22
MA_BANK2
MA_BANK1
MA_BANK0
MB_BANK2
MB_BANK1
MB_BANK0
K26 DDR_B_BS#2
T26 DDR_B_BS#1
U26 DDR_B_BS#0
DDR_B_BS#2 <11>
DDR_B_BS#1 <11>
DDR_B_BS#0 <11>
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
T20
U20
U21
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U24 DDR_B_RAS#
V26 DDR_B_CAS#
U22 DDR_B_WE#
DDR_B_RAS# <11>
DDR_B_CAS# <11>
DDR_B_WE# <11>
<10> DDR_A_BS#2
<10> DDR_A_BS#1
<10> DDR_A_BS#0
<10> DDR_A_RAS#
<10> DDR_A_CAS#
<10> DDR_A_WE#
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
DDR_B_ODT1 <11>
DDR_B_ODT0 <11>
DDR_A_ODT1 <10>
DDR_A_ODT0 <10>
DDR_B_MA[15..0]
<11>
<11> DDR_B_DM[7..0]
CONN@ FOX_PZ63823-284S-41F
Athlon 64 S1
Processor
Socket
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH
DDR_A_CLK2
DDR_B_CLK2
1
DDR_A_CLK#2
1
C102
1.5P_0402_50V8C
DDR_B_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0
AD12
AC16
AE22
AB26
E25
A22
B16
A12
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
Y13
AB16
Y19
AC24
F24
E19
C15
E12
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D[63..0]
<10>
4
DDR_A_DM[7..0]
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
Athlon 64 S1
Processor Socket
DDR_B_CLK#1
C105
1.5P_0402_50V8C
1
Compal Secret Data

2007/5/18
Issued Date
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
1
C104
1.5P_0402_50V8C
hexainf@hotmail.com
GRATIS - FOR FREE
AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
CONN@ FOX_PZ63823-284S-41F
DDR_B_CLK1
1
C17
1.5P_0402_50V8C
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
JCPU1C
DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDRII Data
+1.8V
4
2010/03/12
Deciphered Date
Title

SCHEMATIC, MB A5481
Date:
Rev
0.1
401743
Sheet

E
of
46
+1.8VS
C116
2
C118
2
2
2
4.7U_0805_10V4Z
<BOM Structure>
C22
0.22U_0603_16V4Z
+1.8V
F8
F9
<BOM Structure>
+1.8VS
2
LDT_RST#
H_PWRGD
LDT_STOP#
R346
300_0402_5%
R13
+1.2V_HT
H_PWRGD
<17> H_PWRGD
R61
R16
B7
A7
F10
CPU_SIC
1
300_0402_5%
(5/10, >1")
1
C720
0.01U_0402_25V4Z
@
F6
E6
<45> CPU_VCC_SENSE
<45> CPU_VSS_SENSE
(10/5/5/5/10)
TP26
W9
Y9
TP3
+1.8VS
2 3900P_0402_50V7K
1
C109
<16> CLK_CPU_BCLK
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
R22
169_0402_1%
R342
300_0402_5%
<16> CLK_CPU_BCLK#
C23
2
3900P_0402_50V7K
LDT_STOP#
<13,17> LDT_STOP#
1
A9
A8
C119
0.1U_0402_16V4Z
1
2
VDD
CPU_THERMDA
CPU_THERMDC
2
2200P_0402_50V7K
D-
THERM#
D+
SCLK
SDATA
ALERT#
GND
CPU_PRESENT_L
VDD_FB_H
VDD_FB_L
E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
C3
AA6
W7
W8
Y6
AB6
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
P20
P19
N20
N19
RSVD0
RSVD1
RSVD2
RSVD3
EC_SMB_CK2 <28>
EC_SMB_DA2 <28>
ADM1032ARMZ-2REEL_MSOP8
<BOM Structure>
F75383M_MSOP8
R26
R25
P22
R22
SMBus Address: 1001110X (b)
CPU_VID1
CPU_PRESENT#
PSI_L
A5
C6
A6
A4
C5
B5
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
<45>
<45>
<45>
<45>
<45>
<45>
CPU_TEST21_SCANEN
VID1: For compatibility

with future processors
2
300_0402_5%
<BOM Structure>
2
1K_0402_5%
<BOM Structure>
2
300_0402_5%
1
R47
2
300_0402_5%
PSI_L
RSVD4
RSVD5
RSVD6
RSVD7
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
TEST29_H
TEST29_L
AC6 CPU_PRESENT#
A3
<45>
+1.8V
CLKIN_H
CLKIN_L
TMS
TCK
TRST_L
TDI
CPU_THERMDC
CPU_THERMDA
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
VDDIO_FB_H
VDDIO_FB_L
AA9
AC9
AD9
AF9
U3
1
HTREF1
HTREF0
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
(10/10)
AF6
AC7
CPU_TEST26_BURNIN#
VID5
VID4
VID3
VID2
VID1
VID0
SIC
SID
DBRDY
TP5
TP30
TP8
TP28
TP31
THERMTRIP_L
PROCHOT_L
RESET_L
PWROK
LDTSTOP_L
G10
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
C719
0.01U_0402_25V4Z
@
VDDA2
VDDA1
CPU_DBRDY
+3VS
1
C120
AF4
AF5
2 44.2_0402_1% CPU_HTREF1 P6
2 44.2_0402_1% CPU_HTREF0 R6
1
1
1
R24
1
R64
1
R27
JCPU1D
C9
C8
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
2
R65
CPU_TEST25_H_BYPASSCLK_H
1
510_0402_5%
2
R68
2
R69
2
R66
CPU_TEST25_L_BYPASSCLK_L
1
510_0402_5%
CPU_TEST19_PLLTEST0
1
300_0402_5%
CPU_TEST18_PLLTEST1
1
300_0402_5%
R53
80.6_0402_1%
1
2
<BOM Structure>
ROUTE AS 80 Ohm DIFFERENTIAL PAIR

PLACE IT CLOSE TO CPU WITHIN 1"
TEST24
TEST23
TEST22
TEST21
TEST20
AE7
AD7
AE8
AB8
AF7
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
J7
H8
AF8
AE6
K8
C4
RSVD8
RSVD9
H16
B18
RSVD10
RSVD11
B3
C1
RSVD12
RSVD13
RSVD14
H6
G6
D5
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
R24
W18
R23
AA8
H18
H19
TP6
TP7
TP9
CPU_TEST21_SCANEN
TP29
CPU_TEST26_BURNIN#
+1.8V
+3VALW
+1.8V
+3VALW
1
C113
150U_D2_6.3VM
R18
1K_0402_5%
R8
300_0402_5%
R25
@ 1K_0402_5%
B
Q2
MMBT3904_NL_SOT23-3
1
MAINPWON <39,41>
C
Q3
1H_THERMTRIP#
2
CPU_THERMTRIP#_R
FOX_PZ63823-284S-41F
CONN@
10K_0402_5%
R17
2 2
C721
0.01U_0402_25V4Z
@
<15/20>
1
1
+2.5VDDA
VDDA=300mA
L4
3300P_0402_50V7K
1
2
FCM2012CF-800T06_2P
1
1
1
+2.5VS
LDT_RST#
LDT_RST#
<17>
MISC
R344
300_0402_5%
MMBT3904_NL_SOT23-3
H_THERMTRIP# <18>
NOTE: HDT TERMINATION IS REQUIRED

FOR REV. Ax SILICON ONLY.
JP3
@ SAMTEC_ASP-68200-07
R20
300_0402_5%
CPU_PROCHOT#_1.8
+3VS
1
R52
2
0_0402_5%
HDT_RST#
A
U51
NC7SZ08P5X_NL_SC70-5
<BOM Structure>
2
1
LDT_RST#
SB_PWRGD <18,33>
Compal Secret Data
2007/5/18
Issued Date
2010/03/12
Deciphered Date
Title

SCHEMATIC, MB A5481
Date:
H_PROCHOT_R# <17>
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
17
19
21
23
+1.8V
HDT Connector
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
AMD: suggest DBREQ need pull high
2
1
@ 220_0402_5% R33
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R34
2
1
@ 220_0402_5% R35
2
1
220_0402_5% R36
+1.8V
Rev
C
401743
Sheet

1
of
46
JCPU1E
C26
330U_D2E_2.5VM_R9M
C32
330U_D2E_2.5VM_R9M
@
C27
330U_D2E_2.5VM_R9M
+ C28
330U_D2E_2.5VM_R9M
2
C29
330U_D2E_2.5VM_R9M
Near CPU Socket

+CPU_CORE
C33
22U_0805_6.3V6M
C36
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
+CPU_CORE
C35
22U_0805_6.3V6M
<BOM Structure> 2
C178
22U_0805_6.3V6M
+CPU_CORE
C41
22U_0805_6.3V6M
C190
22U_0805_6.3V6M
C39
22U_0805_6.3V6M
C128
22U_0805_6.3V6M
+CPU_CORE
<BOM Structure>
1
C129
0.22U_0603_16V4Z
C151
0.22U_0603_16V4Z
C122
0.01U_0402_25V7K
C47
180P_0402_50V8J
Under CPU Socket
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
Power
VDD(+CPU_CORE) decoupling.
AC4
AD2
G4
H2
J9
J11
J13
K6
K10
K12
K14
L4
L7
L9
L11
L13
M2
M6
M8
M10
N7
N9
N11
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
V6
V8
V10
+CPU_CORE
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+CPU_CORE
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
+1.8V
FOX_PZ63823-284S-41F
CONN@
VDDIO decoupling.
Athlon 64 S1
Processor Socket
+1.8V
+1.8V
C170
22U_0805_6.3V6M
C181
22U_0805_6.3V6M
C124
0.22U_0603_16V4Z
C147
0.22U_0603_16V4Z
<BOM Structure>
+1.8V
150U_D2_6.3VM
C157
0.22U_0603_16V4Z
C182
0.22U_0603_16V4Z
C68
0.22U_0603_16V4Z
C188
0.22U_0603_16V4Z
+1.8V
C175
0.01U_0402_25V7K
C159
0.01U_0402_25V7K
<BOM Structure>
180PF Qt'y follow the distance between

CPU socket and DIMM0. <2.5inch>
1
C189
180P_0402_50V8J
C136
180P_0402_50V8J
<BOM Structure>
C156
180P_0402_50V8J
<BOM Structure>
+1.8V
C76
4.7U_0805_10V4Z
<BOM Structure> 2
C158
180P_0402_50V8J
C155
4.7U_0805_10V4Z
<BOM Structure>
1
C167
4.7U_0805_10V4Z
1
C187
4.7U_0805_10V4Z
+
C132
4.7U_0805_10V4Z
2
<BOM Structure>
C146
4.7U_0805_10V4Z
<BOM Structure>
<BOM Structure>
C184
0.22U_0603_16V4Z
C173
0.22U_0603_16V4Z
C72
1000P_0402_50V7K
<BOM Structure>
C145
1000P_0402_50V7K
<BOM Structure>
C180
180P_0402_50V8J
C121
180P_0402_50V8J
<BOM Structure>
<BOM Structure>
C73
4.7U_0805_10V4Z
C70
4.7U_0805_10V4Z
C127
0.22U_0603_16V4Z
C185
0.22U_0603_16V4Z
C164
1000P_0402_50V7K
C163
1000P_0402_50V7K
C152
180P_0402_50V8J
C179
180P_0402_50V8J
C162
220U_D2_4VM_R15
<BOM Structure>
<BOM Structure>
<BOM Structure>
Near CPU Socket Left side.
Compal Secret Data

2007/5/18
2010/03/12
Deciphered Date
Title

SCHEMATIC, MB A5481
Date:
Near CPU Socket Right side.
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
+0.9V
1
1
C: Change to NBO CAP
+0.9V
2
1
2
<BOM Structure>
+1.8V
Near Power Supply

1
C66 +
Between CPU Socket and DIMM

1
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
Athlon 64 S1
Processor Socket
+0.9V
VTT decoupling.
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
FOX_PZ63823-284S-41F
CONN@
Under CPU Socket
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
Ground
JCPU1F
+CPU_CORE
Rev
C
401743
Sheet

1
of
46
+DIMM_VREF
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
C
DDR_A_DM3
DDR_A_D26
DDR_A_D27
<7> DDR_CKE0_DIMMA
<7> DDR_CS2_DIMMA#
<7> DDR_A_BS#2
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
<7> DDR_A_BS#0
<7> DDR_A_WE#
<7> DDR_A_CAS#
<7> DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
<7> DDR_A_ODT1
DDR_A_D32
DDR_A_D33
B
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
A
DDR_A_D58
DDR_A_D59
<11,16,18,31> SB_CK_SDAT
<11,16,18,31> SB_CK_SCLK
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C448
0.1U_0402_16V4Z
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_CLK1
DDR_A_CLK#1
1K_0402_1%
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
R397
DDR_A_MA4
DDR_A_MA0
DDR_A_BS#1
DDR_CS0_DIMMA#
DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_D[0..63]
<7> DDR_A_D[0..63]
DDR_A_DQS[0..7]
<7> DDR_A_DQS[0..7]
<7> DDR_A_MA[0..15]
DDR_A_D28
DDR_A_D29
<7> DDR_A_DQS#[0..7]
DDR_A_MA[0..15]
DDR_CKE1_DIMMA <7>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C117
1
C144
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<BOM Structure>
47_0804_8P4R_5%
RP3
8
1
7
2
6
3
5
4
47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4
<BOM Structure>
1
C114
1
C95
47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4
1
C103
1
C99
DDR_A_RAS#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
47_0804_8P4R_5%
RP7
8
1
7
2
6
3
5
4
1
C107
1
C98
47_0804_8P4R_5%
RP8
8
1
7
2
6
3
5
4
1
C101
1
C191
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<BOM Structure>
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<BOM Structure>
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<BOM Structure>
<BOM Structure>
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<BOM Structure>
<BOM Structure>
47_0804_8P4R_5%
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
1
C192
1
C88
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
1
C139
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C81
1
C193
1
C125
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
1
2
3
4
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_DQS#[0..7]
DDR_A_DQS#3
DDR_A_DQS3
8
7
6
5
47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4
DDR_A_DM[0..7]
<7> DDR_A_DM[0..7]
DDR_A_D22
DDR_A_D23
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
<BOM Structure>
DDR_A_BS#1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
DDR_A_ODT0 <7>
<BOM Structure>
DDR_CS3_DIMMA# <7>
DDR_A_D36
DDR_A_D37
B
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK2 <7>
DDR_A_CLK#2 <7>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R12
R10
1
1
2 10K_0402_5%
2 10K_0402_5%
Compal Secret Data
Issued Date
FOX_AS0A426-M2RN-7F
CONN@
RP1
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA2
1K_0402_1%
DDR_A_DM1
DIMM2 REV H:5.2mm (BOT)

5
+1.8V
+0.9V
R398
DDR_A_DQS#0
DDR_A_DQS0
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
4.7U_0805_10V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
C503
DDR_A_D0
DDR_A_D1
C507
0.1U_0402_16V4Z
JDIMM2
+1.8V
+1.8V
+1.8V
2005/10/11
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Date:
Rev
C
401743
Sheet

1
10
of
46
+1.8V
+1.8V
+DIMM_VREF
+1.8V
+0.9V
RP9
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
C198
DDR_B_D2
DDR_B_D3
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C202
DDR_B_DQS#0
DDR_B_DQS0
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
4.7U_0805_10V4Z
JDIMM1
DDR_B_D0
DDR_B_D1
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
8
7
6
5
1
2
3
4
2
C196
1
C209
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C197
1
C211
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C205
1
C213
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C199
1
C200
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C206
1
C201
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP10
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_D12
DDR_B_D13
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_DM1
RP11
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_D14
DDR_B_D15
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
RP12
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
C
DDR_B_DM3
DDR_B_D26
DDR_B_D27
<7> DDR_CKE0_DIMMB
<7> DDR_CS2_DIMMB#
<7> DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
<7> DDR_B_BS#0
<7> DDR_B_WE#
<7> DDR_B_CAS#
<7> DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
<7> DDR_B_ODT1
DDR_B_D32
DDR_B_D33
B
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
A
DDR_B_D58
DDR_B_D59
<10,16,18,31> SB_CK_SDAT
<10,16,18,31> SB_CK_SCLK
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C21
0.1U_0402_16V4Z
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_D20
DDR_B_D21
DDR_B_DM2
<7> DDR_B_DM[0..7]
DDR_B_D28
DDR_B_D29
<7> DDR_B_DQS[0..7]
<7> DDR_B_MA[0..15]
DDR_B_DQS#3
DDR_B_DQS3
<7> DDR_B_DQS#[0..7]
hexainf@hotmail.com
GRATIS - FOR FREE
47_0804_8P4R_5%
DDR_B_DM[0..7]
RP13
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#
DDR_CKE1_DIMMB <7>
DDR_B_MA15
DDR_B_MA14
8
7
6
5
1
2
3
4
2
C210
1
C208
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C194
1
C207
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C212
1
C195
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
47_0804_8P4R_5%
RP15
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
RP16
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_BS#1 <7>
DDR_B_RAS# <7>
DDR_CS0_DIMMB# <7>
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_ODT0 <7>
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_CS3_DIMMB# <7>
DDR_B_D36
DDR_B_D37
B
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK2 <7>
DDR_B_CLK#2 <7>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R11
R9
1
1
2 10K_0402_5%
2 10K_0402_5%
+3VS
FOX_AS0A426-MARG-7F
CONN@
1
2
3
4
RP14
DIMM1 REV H:9.2mm (BOT)

5
DDR_B_D[0..63]
<7> DDR_B_D[0..63]
DDR_B_D22
DDR_B_D23
8
7
6
5
Issued Date
Compal Secret Data
2005/10/11
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Date:
Rev
C
401743
Sheet

1
11
of
46
U22B
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
PART 2 OF 6
PCIE I/F GPP
PCIE I/F SB
Check SW Routing
AN_RS780MN1, Only suggest pair0~3 can
usage for power save.
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
C600 1
C601
1
C602 1
C605
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
2
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
<31>
<31>
<25>
<25>
WLAN
LAN
<6> H_CADOP[0..15]
<6> H_CADON[0..15]
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R29
R32
C259
C272
C254
C252
C168
C261
C248
C275
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1.27K_0402_1%
2K_0402_1%
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
+1.1VS
RS780MN-SA00002DR30 Ver:A13
HT Link
When tune trace length, must
keep 1:4 on self-trace
GFX_TX0,TX1,TX2 and TX3

DP0
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
DP1
AUX1 and HPD1
Check AMD
H_CADIP[0..15]
H_CADON[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
<6>
H_CADIN[0..15]
<6>
U22A
RS780M_FCBGA528
RS780M Display Port Support (muxed on GFX)
H_CADOP[0..15]
<6>
<6>
<6>
<6>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<6>
<6>
<6>
<6>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
M22
M23
R21
R20
C23
A24
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
R67
301_0402_1%~D
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HYPER TRANSPORT CPU I/F
<31>
<31>
<25>
<25>
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
PCIE I/F GFX
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
RS780M_FCBGA528
Place within 1"

layout 4/8
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
1
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
<6>
<6>
<6>
<6>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<6>
<6>
<6>
<6>
R79
301_0402_1%~D
Place within 1"

layout 4/8
2005/03/08
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
12
of
47
+3VS
L8
1
2 +AVDD1 <110mA>
MBK2012170YZF_0805
C40
1
22U_0805_6.3V6M
U22C
+AVDDQ
+1.8VS
+VDDA18HTPLL
L24
1
2
MBK2012221YZF 0805 1
C266
2.2U_0603_6.3V4Z
+1.8VS
<20mA>
GMCH_CRT_R
<23> GMCH_CRT_R
GMCH_CRT_G
<23> GMCH_CRT_G
2
1
R55
1
R60
1
R62
+VDDA18PCIEPLL
GMCH_CRT_R
2
140_0402_1%
GMCH_CRT_G
2
150_0402_1%
GMCH_CRT_B
2
150_0402_1%
GMCH_CRT_B
<23> GMCH_CRT_B
R59
R319
1
<15,17,25,28,31> PLT_RST#
<18> NB_PWRGD
VDDA18HTPLL
+VDDA18PCIEPLL
D7
E7
VDDA18PCIEPLL1
VDDA18PCIEPLL2
D8
A10
C10
C12
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
C25
C24
HT_REFCLKP
HT_REFCLKN
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
NB_RESET#
2
300_0402_5%
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
CLK_NB_14.318M
@
2
C691
22P_0402_50V8J
+1.1VS
1
2
R58
4.7K_0402_5%
1
2
R43
4.7K_0402_5%
<16> CLK_NBGFX
<16> CLK_NBGFX#
R637
10_0402_5%
For EMI
<16> CLK_SBLINK_BCLK
<16> CLK_SBLINK_BCLK#
<24> GMCH_LCD_CLK
<24> GMCH_LCD_DATA
+3VS
GMCH_LCD_CLK
GMCH_LCD_DATA
R323 1
2 4.7K_0402_5%
GMCH_LCD_CLK
R322 1
2 4.7K_0402_5%
GMCH_LCD_DATA
R488 1
2 4.7K_0402_5%
GMCH_CRT_CLK
R493 1
2 4.7K_0402_5%
@
2
1
R327
10K_0402_5%
+3VS
1
R552
POWER_SEL
<42> POWER_SEL
2
2K_0402_1%
1
R320
2
0_0402_5%
T2
T1
GFX_REFCLKP
GFX_REFCLKN
U1
U2
GPP_REFCLKP
GPP_REFCLKN
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
B10
POWER_SEL
LOW
1.1V
HIGH
1.0V
<15>
<24>
<24>
<24>
<24>
<24>
<24>
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
GMCH_TZOUT0+
GMCH_TZOUT0GMCH_TZOUT1+
GMCH_TZOUT1GMCH_TZOUT2+
GMCH_TZOUT2-
<24>
<24>
<24>
<24>
<24>
<24>
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLK-
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
<15mA>
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
<300mA> +VDDLT18
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
E9
F7
G12
TMDS_HPD(NC)
HPD(NC)
D9
D10
SUS_STAT#(PWM_GPIO5)
D12
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
D13
AUX_CAL(NC)
<24>
<24>
<24>
<24>
+VDDLTP18
L51
1
2
1 MBC1608121YZF_0603
+VDDLTP18
C115
0.1U_0402_16V4Z
VARY_ENBKL
R54
+1.8VS
C449
2.2U_0603_6.3V4Z
+VDDLT18
R15
MIS.
RSVD
C8
AUX_CAL
Strap pin
GMCH_TXOUT0+
GMCH_TXOUT0GMCH_TXOUT1+
GMCH_TXOUT1GMCH_TXOUT2+
GMCH_TXOUT2-
STRP_DATA
G11
GMCH_CRT_DATA
A22
B22
A21
B21
B20
A20
A19
B19
DAC_RSET(PWM_GPIO1)
H17
<16> CLK_NBHT
<16> CLK_NBHT#
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
+VDDA18HTPLL
CLK_NB_14.318M
<16> CLK_NB_14.318M
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
0_0402_5%
2
1
R326
+1.8VS
NB_PGRGD (SB)
Output, OD
G18
G17
E18
F18
E19
F19
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
A12
D14
B12
C400
2.2U_0603_6.3V4Z
+NB_PLLVDD
+NB_HTPVDD
+NB_PLLVDD
+NB_HTPVDD
+NB_PLLVDD
L50
1
2
<120mA>
MBK2012221YZF 0805 1
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
2 715_0402_1% G14
Close to U22 Ball
+1.1VS
E17
F17
F15
GMCH_CRT_HSYNC A11
GMCH_CRT_VSYNC B11
GMCH_CRT_CLK
F8
GMCH_CRT_DATA E8
<15,23> GMCH_CRT_HSYNC
<15,23> GMCH_CRT_VSYNC
<23> GMCH_CRT_CLK
<23> GMCH_CRT_DATA
<20mA>
1
2
MBK2012221YZF 0805 1
C267
2.2U_0603_6.3V4Z
L5
C31
2.2U_0603_6.3V4Z
<4mA>
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
2 VARY@ 1
4.7K_0402_5%
<20mA>
F12
E12
F14
G15
H15
H14
2
1
4.7K_0402_5%
L25
1
2
MBK2012170YZF_0805
2
1
4.7K_0402_5%
C265
2.2U_0603_6.3V4Z
+1.8VS
2
+AVDD2
1
CRT/TVOUT
L23
1
2
MBK2012170YZF_0805
PLL PWR
LVTM
C78
2.2U_0603_6.3V4Z
+1.8VS
PM
+NB_HTPVDD
L10
1
2
<65mA>
MBK2012221YZF 0805 1
CLOCKs
+1.8VS
L49
1
2
MBC1608121YZF_0603
+1.8VS
C455
4.7U_0805_10V4Z
R49 1
2 0_0402_5%
GMCH_ENVDD <24>
R50 1
2 0_0402_5%
ENBKL <28>
R57 1 VARY@ 2 0_0402_5%
GMCH_INVT_PWM <24>
R51 1 VARY@ 2 0_0402_5%
R56
@
2
1
R328
10K_0402_5%
1
2
R48
0_0402_5%
SUS_STAT# <18>
SUS_STAT_R# <15>
Strap Pin
B
1
2
R343
1.8K_0402_5%
RS780M_FCBGA528
+1.8VS
R28
<8,17> LDT_STOP#
LDT_STP# (SB)
Output, OD
0_0402_5%
2
300_0402_5%
R85
1
NB_LDTSTOP#
<17> ALLOW_LDTSTOP
LDTSTOP# (NB)
In Lagcy mode: Input, 1.8V signal can be used
In CLMC mode: Output, OD
SB: I/ OD
R553
1
0_0402_5%
NB_ALLOW_LDTSTOP
2
ALLOW_LDTSTOP (NB)
In Lagcy mode: Output,OD
In CLMC mode: Input, 1.8Vsignal can be used
Compal Secret Data
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
2010/03/12
Deciphered Date
Title
Size
Custom
Date:

SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

1
13
of
47
U22F
2
0.1U_0402_16V4Z
C52
22U_0805_6.3V6M
C53
22U_0805_6.3V6M
1
C37
1
C55
1
C58
1
C56
<700mA>
1
C62
2
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<10mA>
+1.8VS
C398
1U_0402_6.3V4Z
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
F9
G9
<25mA> AE11
+1.8VS
AD11
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
<7.6A>
1
2
+
2
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
H11
H12
<60mA>
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780M_FCBGA528
+3VS
1
C93
0.1U_0402_16V4Z
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
AE10
AA11
Y11
AD10
AB10
AC10
RS780M_FCBGA528
+NB_CORE
330U_D2E_2.5VM_R9M
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE
+1.1VS
C10
L9
2
1
FBMA-L11-201209-221LMA30T_0805
+1.8VS
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
C20
2
2
0.1U_0402_16V4Z
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
C18
1
C255
22U_0805_6.3V6M
1
C171
C251
2
22U_0805_6.3V6M
1
C258
@ L7
2
1
FBMA-L11-201209-221LMA30T_0805
2
1
FBMA-L11-201209-221LMA30T_0805
@ L6
0.1U_0402_16V4Z
1
C130
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
22U_0805_6.3V6M
1
C262
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
C80
FBMA-L11-201209-221LMA30T_0805
<680mA> AE25
2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
C218
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX
1
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
C51
C43
2
2
2
2
C256
L21
+1.2V_HT
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
1
1
1
1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C42
C59
C44
C38
C215
C273
2
2
0.1U_0402_16V4Z
H18
G19
F20
E21
D22
B23
A23
<680mA>
2
2 22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_16V4Z
C264
0.68A
1
1
0.1U_0402_16V4Z
C219
2
C57
C257
2
22U_0805_6.3V6M
C19
C15
C123
C154
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
0.1U_0402_16V4Z
PART 5/6
+VDDA11PCIE
C112
0.1U_0402_16V4Z +VDDHTRX
0.1U_0402_16V4Z
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
+1.1VS
<1.1A>
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
0.1U_0402_16V4Z
J17
K16
L16
M16
P16
R16
T16
PART 6/6
1
C61
U22D
0.1U_0402_16V4Z
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
W12
Y12
AD18
AB13
AB18
V14
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
V15
W14
MEM_CKP(NC)
MEM_CKN(NC)
AE12
AD12
SBD_MEM/DVO_I/F
U22E
2
0.1U_0402_16V4Z
L22
FBMA-L11-201209-221LMA30T_0805
L16
2
1
FBMA-L11-201209-221LMA30T_0805
C126
C110
C253
0.1U_0402_16V4Z
C249
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C131
2
22U_0805_6.3V6M
POWER
C108
D
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
GROUND
L14
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDHT
2
1
FBMA-L11-201209-221LMA30T_0805
1
1
1
1
1
+1.1VS
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
IOPLLVDD18(NC)
IOPLLVDD(NC)
AE23
AE24
+1.8VS
+1.1VS
AD23
IOPLLVSS(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
AE18 1
R351
MEM_VREF(NC)
2
0_0402_5%
RS780M_FCBGA528
A
Compal Secret Data
2005/03/08
Issued Date
2010/03/12
Deciphered Date
Title

SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
14
of
47
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
2
R341
2
R337 @
D
1
3K_0402_5%
1
3K_0402_5%
Enables the Test Debug Bus using GPIO. (VSYNC)

1 : Disable (RS780)
0 : Enable (Rs780)
+3VS
DFT_GPIO1: LOAD_EEPROM_STRAPS
1
@ R315
<13> AUX_CAL
Selects Loading of STRAPS from EPROM

1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
2
150_0402_1%
@
RS780 DFT_GPIO1
<13> SUS_STAT_R#
D22
PLT_RST# <13,17,25,28,31>
CH751H-40PT_SOD323-2
RS780 use HSYNC to enable SIDE PORT

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0.
Enable (RS780)
1 : Disable(RS780)
RS780 use HSYNC to enable SIDE PORT

2
R332
@
2
R331
1
3K_0402_5%
1
3K_0402_5%
+3VS
Compal Secret Data
2005/10/10
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
2010/03/12
Deciphered Date
Title
Size
Custom
Date:

SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

1
15
of
47
+VDDCLK_IO
+1.2V_HT
+3VS_CLK
+3VS
L31
L30
1
2
1
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
1
C142
C260
0.1U_0402_16V4Z
1
C293
C298
0.1U_0402_16V4Z
1
C135
C280
0.1U_0402_16V4Z
1
C263
FBMA-L11-201209-221LMA30T_0805
2
2
22U_0805_6.3V6M
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C367
C138
0.1U_0402_16V4Z
1
C278
22U_0805_6.3V6M
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C295
C404
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C160
C274
2
0.1U_0402_16V4Z
C140
0.1U_0402_16V4Z
1
C268
2
0.1U_0402_16V4Z
C294
2
0.1U_0402_16V4Z
C297
1U_0402_6.3V4Z
1U CLOSE PIN 69
L36
1
+3VS_CLK
+3VS_CLKVDDA
FBMA-L11-201209-221LMA30T_0805
+VDDCLK_IO
8.2K_0402_5%
R182
8.2K_0402_5%
+3VS_CLK
R188
R495 8.2K_0402_5%
1
2
8.2K_0402_5%
MiniCard1 request
R490 8.2K_0402_5%
1
2
LAN request
VDDREF
GNDREF
SB_SRC_SLOW#
12
18
28
37
53
VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO
CPUKG0T_LPRS
CPUKG0C_LPRS
56
55
CLK_CPU
CLK_CPU#
1
R170 1
R168
2
2 47.5_0402_1%
47.5_0402_1%
HTT0T_LPRS / 66 M
HTT0C_LPRS / 66 M
60
59
CLK_HTT
CLK_HTT#
1
R175 1
R172
2
2 0_0402_5%
0_0402_5%
SB_SRC0T_LPRS
SB_SRC0C_LPRS
40
39
SB_SRC1T_LPRS
SB_SRC1C_LPRS
35
34
+3VS_CLK
SEL_SATA
SEL_HT66
62
66
1
0.1U_0402_16V4Z
+3VS
L35
1
2
FBM-L11-160808-800LMT_0603
1
2
C282 @
2.2U_0603_6.3V4Z
1
2
C281
0.1U_0402_16V4Z
<25> LAN_CLKREQ#
<31> MINI1_CLKREQ#
External 14MHz CLK

for SB710
R109
1
<17> CLK_14M_SB
<13> CLK_NB_14.318M
1
R178
<27> CLK_48M_SD
<18> CLK_48M_USB
3
17
29
38
44
54
61
69
24
VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDD48
51
CLKREQ1#
50
CLKREQ2#
43
CLKREQ3#
42
CLKREQ4#
63
REF2/SEL_27
64
REF1/SEL_SATA
SEL_HT66
1
2
R179
158_0402_1%
2
90.9_0402_1%
CLK_48M_0
2
1
R194
33_0402_5%
CLK_48M_1
2
1
R193
33_0402_5%
65
REF0/SEL_HTT66
71
48MHz_0
70
48MHz_1
CLK_XTAL_IN
67
X1
CLK_XTAL_OUT
68
X2
CLK_XTAL_OUT
CLK_XTAL_IN
6
11
19
27
36
47
52
58
72
73
Y4
2
FUJICOM
14.31818MHZ_20P_6X1430004201
1
1
C290
C288
33P_0402_50V8J
GNDDOT
GNDSRC
GNDSRC
GNDATIG
GNDSB_SRC
GNDSATA
GNDCPU
GNDHTT
GND48
GNDPAD
1
2
SB_CK_SCLK <10,11,18,31>
SB_CK_SDAT <10,11,18,31>
SRC_SLOW
41
ATIG0T_LPRS
ATIG0C_LPRS
33
32
ATIG1T_LPRS
ATIG1C_LPRS
31
30
ATIG2T_LPRS
ATIG2C_LPRS
26
25
SRC0T_LPRS
SRC0C_LPRS
23
22
SRC1T_LPRS
SRC1C_LPRS
21
20
SRC2T_LPRS
SRC2C_LPRS
16
15
SRC3T_LPRS
SRC3C_LPRS
14
13
SRC4T_LPRS
SRC4C_LPRS
10
9
SRC5T_LPRS
SRC5C_LPRS
8
7
CLKREQ0 #
SEL_SATA
33_0402_5%
2
SMBCLK
SMBDAT
<8>
CPU
CLK_CPU_BCLK#
CLK_NBHT <13>
CLK_NBHT# <13>
<8>
+3VS_CLK
NB HTT
R161
8.2K_0402_5%
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
SRC7T_LPRS/27MHz_SS
SRC7C_LPRS/27MHz_NS
SRC_SLOW
C
CLK_ATIG0
CLK_ATIG0#
1
R174 1
R176
2
2 0_0402_5%
0_0402_5%
CLK_NBGFX <13>
CLK_NBGFX# <13>
CLK_SRC0
CLK_SRC0#
1
R189 1
R190
2
2 0_0402_5%
0_0402_5%
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
CLK_SRC2
CLK_SRC2#
1
R197 1
R196
2
2 0_0402_5%
0_0402_5%
CLK_SRC4
CLK_SRC4#
1
R200 1
R199
2
2 0_0402_5%
0_0402_5%
NB GFX
R111
8.2K_0402_5%
CLK_PCIE_MINI1 <31>
CLK_PCIE_MINI1# <31>
LAN
MiniCard
SRC 0
CLK_SRC6
CLK_SRC6#
46
45
1
R163 1
R164
2
2 0_0402_5%
0_0402_5%
CLK_SBLINK_BCLK <13>
CLK_SBLINK_BCLK# <13> NB
CLK_SBSRC_BCLK <17>
CLK_SBSRC_BCLK# <17>
LAN
B
SRC 1
A LINK
SRC 2
MINI1 (WLAN)
SRC 3
NEW CARD
SRC 4
NB-Alink
SRC 5
SB RCLK
SRC 6
SB-Alink
5
4
NB CLOCK INPUT TABLE

PD#
57
2
R173
1
33P_0402_50V8J
CLK_CPU_BCLK
R169
261_0402_1%
C277 2
R187
VDDA
GNDA
+3VS_CLK
R112
8.2K_0402_5% @
ICS 9LPRS488
49
48
C141
0.1U_0402_16V4Z
U15
22U_0805_6.3V6M
C161
1
+3VS_CLK
1
8.2K_0402_5%
NB CLOCKS
+3VS_CLK
C299
Main--SLG8SP626VTR-SA00001Z310
RS780
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
REFCLK_N
14M SE (3.3V)
NC
14M SE (1.8V)
NC
14M SE (1.1V)
vref
GFX_REFCLK
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
GPP_REFCLK
NC
100M DIFF
NC
100M DIFF
100M DIFF
HT_REFCLKN
2
RX780
66M SE(SINGLE END)
ICS9LPRS488AKLFT_MLF72_10x10
RS740
HT_REFCLKP
1U_0402_6.3V4Z
REFCLK_P
Second--ICS9LPRS488CKLFT-SA000023H10
GPPSB_REFCLK 100M DIFF
configure as single-ended 66MHz output
0*
configure as differential 100MHz output
1*
SS 100M SATA SRC6 output
SS 100M SATA SRC6 output
SEL_HTT66
SEL_27M
No used
configure as 27M and 27M_SS output
configure as SRC_7 output
Compal Secret Data
2005/03/08
Issued Date
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
SEL_SATA
* default
Date:
Rev
C
401743
Sheet

1
16
of
47
U10A
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
C172
C246
C402
C176
C183
C186
C204
C214
1
1
1
1
1
1
1
1
R127
R131
+PCIE_VDDR
+1.2V_HT
1
R135
2
2
1
1
2 A_RST#
8.2K_0402_5%
C468
1
2
2.2U_0402_6.3V6M
U22
U21
U19
V19
R20
R21
R18
R17
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
Part 1 of 5
PCIE_CALRP
PCIE_CALRN
<43mA> P24
PCIE_PVDD
P25
PCIE_PVSS
PLT_RST# <13,15,25,28,31>
NC7SZ08P5X_NL_SC70-5
R293
100K_0402_5%
1
33_0402_5%
2
R134 @
External 14MHz for SB710

@ R101 20M_0402_5%
1
2
<16> CLK_14M_SB
SB_32KHI
R635
@ 10_0402_5%
Y2
NB_HT_CLKP
NB_HT_CLKN
P17
M18
CPU_HT_CLKP
CPU_HT_CLKN
M23
M22
SLT_GFX_CLKP
SLT_GFX_CLKN
J19
J18
GPP_CLK0P
GPP_CLK0N
L20
L19
GPP_CLK1P
GPP_CLK1N
M19
M20
GPP_CLK2P
GPP_CLK2N
N22
P22
GPP_CLK3P
GPP_CLK3N
L18
25M_48M_66M_OSC
J21
25M_X1
OUT
IN
NC
NC
R91
20M_0603_5%
C403
M24
M25
18P_0402_50V8J
B
NB_DISP_CLKP
NB_DISP_CLKN
C203
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
K23
K22
PCI INTERFACE
PLT_RST#
N25
N24
CLOCK GENERATOR
5
Y
A
<16> CLK_SBSRC_BCLK
<16> CLK_SBSRC_BCLK#
U11
C690
@ 22P_0402_50V8J
32.768KHZ_12.5P_MC-306
SB_32KHO
J20
25M_X2
2
SB_32KHI
A3
X1
SB_32KHO
B3
X2
ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
PCIRST#
N1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
<21>
<21>
<21>
<21>
Strap pin
LPC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
AD3
AC4
AE2
AE3
RTCCLK
INTRUDER_ALERT#
VBAT
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
1
R149
<21>
<21>
<21>
<21>
<21>
<21>
2
0_0402_5%
PM_CLKRUN# <28>
G22 CLK_LPC_EC
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15
C3
C2
B2
R108 1
2 22_0402_5%
CLK_PCI_EC
2
1M_0402_5%
RTC_CLK <21>
+RTCVCC
STRAP PIN
+RTCVCC
SB710 Ver:A14 <SA000030740>

A
1
R385
C405 1
+RTCBATT
R556
2
2
510_0402_5%
W=20mils
@
D5
1K_0402_5%
1
R379
0_0603_5%
for Clear CMOS
C339
3
1
2
2005/03/08
Deciphered Date
2010/03/12
+CHGRTC
Title
Size
Custom
Date:
hexainf@hotmail.com
GRATIS - FOR FREE
BAS40-04_SOT23-3
Compal Secret Data
Issued Date
1 C134
1U_0402_6.3V4Z
218S7EALA11FG_BGA528_SB700
STRAP PIN
SERIRQ <28>
1
R107
0.1U_0402_16V4Z
LDT_PG: OD pin
CLK_PCI_EC <21,28>
LPCCLK1 <21>
LPC_AD0 <28>
LPC_AD1 <28>
LPC_AD2 <28>
LPC_AD3 <28>
LPC_FRAME# <28>
RTC
F23
F24
F22
G25
G24
P4
P3
P1
P2
T4
T3
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
CPU
<13> ALLOW_LDTSTOP
<8> H_PROCHOT_R#
<8> H_PWRGD
<8,13> LDT_STOP#
<8>
LDT_RST#
RTC XTAL
18P_0402_50V8J
Close to SB
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41
1U_0402_6.3V4Z
A_RST#
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
0.1U_0402_16V4Z
2
SB700
A_RST#
V23
V22
V24
V25
U25
U24
T23
T22
562_0402_1% T25
2.05K_0402_1% T24
+SB_PCIEVDD
1
C472
L59
MBC1608121YZF_0603
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
+3VALW
C177
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
2
2
2
2
2
PCI CLKS
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
0.1U_0402_16V4Z
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
N2
PCI EXPRESS INTERFACE
A_RST#

SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
1
17
of
47
U10D
H_THERMTRIP#
NB_PWRGD
<8> H_THERMTRIP#
<13> NB_PWRGD
<28>
RSMRST#
RSMRST#
RSMRST#
2
2.2K_0402_5%
1
R389
1
2
R404 @ 2.2K_0402_5%
1
2
R410
2.2K_0402_5%
+3VS
SKU ID: UMA

Combine NAL00 SW code
<35> SB_SPKR
<10,11,16,31> SB_CK_SCLK
SB_CK_SCLK
SB_CK_SDAT
CLK Gen, WLAN, DDR

<10,11,16,31> SB_CK_SDAT
C
SKUID
+3VS
R409
2 2.2K_0402_5%
SB_CK_SCLK
R399
2 2.2K_0402_5%
SB_CK_SDAT
<28> EC_LID_OUT#
MDC: option
<35>
<34>
<34>
<35>
<35>
<34>
R119
R118
R121
R120
HDA_BITCLK_AUDIO
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_AUDIO
HDA_SDIN0
HDA_SDIN1
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
<34> HDA_SYNC_MDC
<35> HDA_SYNC_AUDIO
B
<35> HDA_RST_AUDIO#
<34> HDA_RST_MDC#
STRAP PIN<21>
1
1 @
1
1
2
2
2
2
R123
R125
R117
R122
<32>
<32>
HDA_BITCLK
USB_OC#1
USB_OC#0
USB_OC#1
USB_OC#0
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
1
1
HDA_SYNC
2
2
1
1
D3
AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5
F7
E8
USB_HSD11P
USB_HSD11N
H11
J10
USB_HSD10P
USB_HSD10N
E11
F11
USB_HSD9P
USB_HSD9N
A11
B11
USB_HSD8P
USB_HSD8N
C10
D10
USB_HSD7P
USB_HSD7N
G11
H12
USB_HSD6P
USB_HSD6N
E12
E14
USB_HSD5P
USB_HSD5N
C12
D12
USB20_P5
USB20_N5
USB_HSD4P
USB_HSD4N
B12
A12
USB20_P4
USB20_N4
USB_HSD3P
USB_HSD3N
G12
G14
USB20_P3
USB20_N3
USB_HSD2P
USB_HSD2N
H14
H15
USB_HSD1P
USB_HSD1N
A13
B13
USB20_P1
USB20_N1
USB_HSD0P
USB_HSD0N
B14
A14
USB20_P0
USB20_N0
IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17
A18
B18
F21
D21
F19
E20
E21
E19
D19
E18
IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25
G20
G21
D25
D24
C25
C24
B25
C23
IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41
B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18
USB MISC
SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#
B9
B8
A8
A9
E5
F8
E4
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#
M1
M2
J7
J8
L8
M3
L6
M4
L5
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#
HDARST#
10K_0402_5%
1
HDA_SDIN0
R391 2
10K_0402_5%
1
HDA_SDIN1
R116 2
10K_0402_5%
1
HDA_BITCLK
1
R126
+3VALW
R525
R415
2
2.2K_0402_5%
H19
H20
H21
F25
IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3
D22
E24
E25
D23
IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7
INTEGRATED uC
+3VS
R393 2
CLK_48M_USB <16>
USB_RCOMP 1
R390
2
11.8K_0402_1%
D
RSMRST#
HDARST#
2
2
USB_FSD12P
USB_FSD12N
OHCI4 Disable
EHCI1 Disable
USB20_P5 <31>
USB20_N5 <31>
MiniCard1(WLAN)
USB20_P4 <27>
USB20_N4 <27>
Card Reader
USB20_P3 <24>
USB20_N3 <24>
Camera
USB20_P1 <32>
USB20_N1 <32>
M/B conn
USB20_P0 <32>
USB20_N0 <32>
M/B conn
EC_LID_OUT#
2 10K_0402_5%
SB_PCIE_WAKE#
SB710 Ver:A14 <SA000030740>
S3 Power off
S3 Wake Up
STRAP PIN
STRAP PIN
GPIO16 <21>
GPIO17 <21>
+3VALW
SB Power Domain :S5

High: CRT Plugged
R413
100K_0402_5%
CRT_DET
<23> CRT_DET#
2 100K_0402_5%
@
1
2
C269
22P_0402_50V8J
<31> SB_PCIE_WAKE#
USB_FSD13P
USB_FSD13N
E6
E7
2
33_0402_5%
<28> EC_GA20
<28> EC_KBRST#
<28> EC_SCI#
<28> EC_SMI#
G8
USB 1.1
SUS_STAT#_L
C8
USB_RCOMP
USB 2.0
<13> SUS_STAT#
USBCLK/14M_25M_48M_OSC
GPIO
2 SUS_STAT#_L
4.7K_0402_5%
1
R395
+3VS
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD
ACPI / WAKE UP EVENTS
E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W15
K4
K24
F1
J2
H6
F2
J6
W14
INTEGRATED uC
CRT_DET_R
USB OC
EC_SWI#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
2
0_0402_5% TP10
TP11
TP12
HD AUDIO
<28>
<28>
<28>
<28>
<8,33>
SUS_STAT#
1
R555
@
1
R124
Part 4 of 5
SB700
2
Q40 G
2N7002_SOT23
@
1
R558
2 CRT_DET_R
0_0402_5%
2005/03/08
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
18
of
47
Pri/SEC,Mas/Slave assignment
SATA drive controlled by
Port 0
Primary master
SATA controler
Port 1
Secondary master
SATA controler
Port 2
Primary slave
SATA controler
Port 3
Secondary slave
SATA controler
Port 4
Primary (Secondary) master
PATA controler
Port 5
Primary (Secondary) slave
PATA controler
Port Number
U10B
<22> SATA_DTX_C_SRX_N2
<22> SATA_DTX_C_SRX_P2
SATA_RX2N
SATA_RX2P
<22> SATA_STX_DRX_P3
<22> SATA_STX_DRX_N3
AD13
AE13
SATA_TX3P
SATA_TX3N
AB14
AC14
SATA_RX3N
SATA_RX3P
AE14
AD14
SATA_TX4P
SATA_TX4N
AD15
AE15
SATA_RX4N
SATA_RX4P
AB16
AC16
SATA_TX5P
SATA_TX5N
1
R150
10M_0402_5%
2 C279
2
R400
SATA_X2
+3VS R401 1
<34> SATA_LED#
+1.2V_HT
L64
2
1
BLM18PG121SN1D_0603
1
SATA_CAL
Y12
SATA_X1
SATA_X2
AA12
SATA_X2
2 10K_0402_5%
W11
C530
+3VS
V12
+PLLVDD_SATA
C497
2.2U_0603_6.3V4Z
SATA_RX5N
SATA_RX5P
SATA_CAL
1
1K_0402_1%
SATA_X1
SATA_ACT#/GPIO67
<93mA> AA11
PLLVDD_SATA
<6mA> W12
XTLVDD_SATA
0.1U_0402_16V4Z
HW MONITOR
27P_0402_50V8J 1
AE16
AD16
Y3
2
25MHZ_20P
L62
2
1
BLM18PG121SN1D_0603
C493
1U_0402_6.3V4Z
+XTLVDD_SATA
2
1
C496
IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30
AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32
LAN_RST#/GPIO13
ROM_RST#/GPIO14
G6
D2
D1
F4
F3
FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
P5
P8
R8
TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64
C6
B6
A6
A5
B5
VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60
A4
B4
C4
D4
D5
D6
A7
B7
AVDD
F6
AVSS
G7
SA00001S570 Ver:A12
+3VALW
1
@ R557
C677 @ 0.1U_0402_16V4Z
1
2
0_0603_5%
+SB_SPI_VCC
R549
1K_0402_5%
@
SB_SI_SPI_SO
SB_SO_SPI_SI
SB_SPICLK
SB_HOLD#
SB_SPICS#
R554
@
SB_SPICS#
SB_HOLD#
@
1
R551
R559
10K_0402_5%
10K_0402_5% U40
1 CE#
3 WP#
7 HOLD#
4 VSS
2
0_0402_5%
VDD
SCK
SI
SO
8
6
5
2
SB_SPICLK
SB_SO_SPI_SI
SB_SI_SPI_SO
MX25L8005M2C-15G_SOP8
@
Reserve For Debug
EC_THERM# <28>
2
D25
<5mA>
+SB_AVDD
1
1
2
C456
0.1U_0402_16V4Z
D36
2
@
U15
J1
M8
M5
M7
0.1U_0402_16V4Z
+3VALW
SATA_TX2P
SATA_TX2N
AE12
AD12
AB12
AC12
SATA_RX1N
SATA_RX1P
SATA_TX1P
SATA_TX1N
AD11
AE11
AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24
AE10
AD10
SATA_X1
2 C276
1
27P_0402_50V8J 1
ATA 66/100/133
2nd
ODD
SATA_RX0N
SATA_RX0P
IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#
Part 2 of 5
SPI ROM
Main
ODD
SATA_TX0P
SATA_TX0N
AB10
AC10
SERIAL ATA
2nd
HDD
AD9
AE9
SATA PWR
Main
HDD
SB700
1
R377
R378
ACIN
100K_0402_5%
+3VS
100K_0402_5%
+3VALW
<28,37,38,40>
for ACIN level issue
+3VALW
L55
2
1
BLM18PG121SN1D_0603
C457
2.2U_0603_6.3V4Z
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
19
of
47
U10E
U10C
<131mA>
C604
C603
C508
C489
C512
C529
C490
C465
1
1
1
1
1
1
1
1
1
22U_0805_6.3V6M
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
Y20
AA21
AA22
AE25
VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
L15
M12
M14
N13
P12
P14
R11
R15
T16
+SB_VDD
CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4
L21
L22
L24
L25
+1.2V_CKVDD
Part 3 of 5
CORE S0
C524
<510mA>
SB700
L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21
PCI/GPIO I/O
+3VS
C528
C484
C487
C475
C471
C492
C485
+PCIE_VDDR
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
+1.2V_HT
AA14
AB18
AA15
AA17
AC18
AD17
AE17
AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
+1.2V_SATA
L63
2
1
FBMA-L11-201209-221LMA30T_0805
1
C526
C517 1
C527 1
C509 1
C511 1
<32mA>
<567mA>
2
22U_0805_6.3V6M
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7
A17
A24
B17
J4
J5
L1
L2
S5_1.2V_1
S5_1.2V_2
G2
G4
<113mA>
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2 1U_0402_6.3V4Z
C521 2
1 0.1U_0402_16V4Z
C523 2
1 0.1U_0402_16V4Z
C284 1
2 10U_0805_10V4Z
A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5
2
0_0805_5%
2
22U_0805_6.3V6M
2
2.2U_0603_6.3V4Z
2
1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.2VALW
R528
+1.2VALW
L29
2
1
FBMA-L11-160808-221LMT 0603
1
2
C271
22U_0805_6.3V6M
C286 2
1 0.1U_0402_16V4Z
C270 2
1 0.1U_0402_16V4Z
R419 2
1 1K_0402_5%
A10
B10
V5_VREF
AE7
<1mA> +V5_VREF
AVDDCK_3.3V
J16
<47mA> +AVDDCK_3.3V
AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVDDCK_1.2V
K17
<62mA> +AVDDCK_1.2V
E9
<17mA> +AVDDC
AVDDC
0.1U_0402_16V4Z 1
1
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 1K_0402_5%
+5VS
+3VS
2
1
C519
1U_0603_10V4Z
1
D27
L54
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
Reserve for SB700 leakage voltage issue

R417 2
2
C513
0_0603_5%
2
C460 2
C461
+1.2_USB
<658mA>
PLL
C217
C216
C458
C459
C466
C494
C469
C285 1
T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8
+1.2V_HT
+S5_1.2V
<197mA>
USB_PHY_1.2V_1
USB_PHY_1.2V_2
USB I/O
L26
2
1
FBMA-L11-201209-221LMA30T_0805
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L28
2
1
FBMA-L11-160808-221LMT 0603
C515 1
2 1U_0402_6.3V4Z
+S5_3V
1
R416
1
C481
1
C483
1
C525 2
C510 2
C470 2
C504
+AVDD_USB
+3VALW
SB700
+1.2V_HT
+3VALW
3.3V_S5 I/O
P18
P19
P20
P21
R22
R24
R25
CORE S5
C247 1
C514 1
1
1
1
1
1
1
POWER
1
2
C250
22U_0805_6.3V6M
1
2
C520 4.7U_0805_10V4Z
C467 1
2 1U_0402_6.3V4Z
2
2
2
2
2
2
2
0_0805_5%
<600mA>
A-LINK I/O
L65
2
1
FBMA-L11-201209-221LMA30T_0805
SATA I/O
+1.2V_HT
CLKGEN I/O
1 @ 2
C516
22U_0805_6.3V6M
C495
1 @ 2 0.1U_0402_16V4Z
C518
1 @ 2 0.1U_0402_16V4Z
C522
1
2 0.1U_0402_16V4Z
@
IDE/FLSH I/O
<71mA>
+3VS
1
R418
1
2
H18
J17
J22
K25
M16
M17
M21
P16
F9
+3VALW
PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC
GROUND
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
Part 5 of 5
AVSSCK
A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24
P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
L17
C463
C462
SB710 Ver:A14 <SA000030740>
SB710 Ver:A14 <SA000030740>
+AVDDCK_1.2V
L56
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
+AVDDCK_3.3V
C491
L58
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
+3VS
1 C498
1 C499
Compal Secret Data
2005/03/08
Issued Date
+1.2V_HT
C464
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
20
of
47
REQUIRED STRAPS
PCI_CLK3
PCI_CLK4
LPC_CLK0
PCI_CLK5 CLK_PCI_EC LPC_CLK1
BOOTFAIL
TIMER
ENABLED
USE
DEBUG
STRAPS
RESERVED
RESERVED
ENABLE PCI
MEM BOOT
CLKGEN
ENABLED
RTC_CLK AZ_RST_CD#
INTERNAL
RTC
EC
ENABLED
IGNORE
DEBUG
STRAPS
DISABLE PCI CLKGEN

MEM BOOT
DISABLED
DEFAULT
DEFAULT
DEFAULT
Internal pull up
H,H = Reserved
L,H = LPC ROM (Default L,NC)

L,L = FWH ROM
R394
10K_0402_5%
2
1
R142
10K_0402_5%
2
1
+3VALW
R89
10K_0402_5%
2
1
+3VALW
R136
10K_0402_5%
2
1
+3VALW
R146
10K_0402_5%
2
1
+3VALW
R144
10K_0402_5%
2
1
+3VS
DEFAULT
R138
10K_0402_5%
2
1
+3VS
GP16
H,L = SPI ROM

EC
DISABLED
R145
10K_0402_5%
2
1
C
+3VS
DEFAULT
EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)
GP17
+3VALW
R87
2.2K_0402_5%
2
1
BOOTFAIL
TIMER
DISABLED
+3VS
+3VALW
R494
2.2K_0402_5%
2
1
PCI_CLK2
DEFAULT
PULL
LOW
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
PULL
HIGH
<17>
PCI_CLK2
<17>
PCI_CLK3
<17> PCI_CLK4
<17> PCI_CLK5
<17,28> CLK_PCI_EC
<17> LPCCLK1
<17> RTC_CLK
<18> HDARST#
<18> GPIO17
<18> GPIO16
DEBUG STRAPS
R94
2.2K_0402_5%
2
1
R137
2.2K_0402_5%
2
1
R130
10K_0402_5%
2
1
R386
2.2K_0402_5%
2
1
R96
10K_0402_5%
2
1
R129
10K_0402_5%
2
1
R132
10K_0402_5%
2
1
R141
10K_0402_5%
2
1
R133
10K_0402_5%
2
1
R143
10K_0402_5%
2
1
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
PCI_AD28
PULL
HIGH
PULL
LOW
DEBUG STRAPS
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
USE
LONG
RESET
USE PCI
PLL
USE ACPI
BCLK
USE IDE
PLL
USE DEFAULT
PCIE STRAPS
RESERVED
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
USE
SHORT
RESET
BYPASS
PCI PLL
BYPASS
ACPI
BCLK
BYPASS IDE
PLL
USE EEPROM
PCIE STRAPS
R159
2.2K_0402_5%
2
1
R147
2.2K_0402_5%
2
1
R157
2.2K_0402_5%
2
1
R158
2.2K_0402_5%
2
1
R148
2.2K_0402_5%
2
1
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R156
2.2K_0402_5%
2
1
<17>
<17>
<17>
<17>
<17>
<17>
Compal Secret Data
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
2010/03/12
Deciphered Date
Title
Size
Custom
Date:

SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

1
21
of
47
+5VS
+3VS
+5VS
0.1U_0402_16V4Z
Placea caps. near ODD CONN.
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C360
10U_0805_10V4Z
D
C363
C366
C351
C349
C347
C346
1
1
C368
0.1U_0402_16V4Z
10U_0805_10V4Z
C150
10U_0805_10V4Z
2
1U_0402_6.3V4Z
1000P_0402_50V7K
1
C148
C153
0.1U_0402_16V4Z
1000P_0402_50V7K
C149
D
2
1000P_0402_50V7K
SATA ODD CONN
SATA HDD CONN

JSATA2
JSATA1
C289 1
C291 1
2 0.01U_0402_25V7K SATA_STX_C_DRX_P0
2 0.01U_0402_25V7K SATA_STX_C_DRX_N0
C302 1
C305 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
1
2
3
4
5
6
7
GND
HTX+
HTXGND
HRXHRX+
GND
+5VS
C308 1
C307 1
C311 1
C312 1
C370
+
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_STX_C_DRX_P2
SATA_STX_C_DRX_N2
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_SRX_N2
SATA_DTX_SRX_P2
@
R544
+3VS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
0_0805_5%
R545
+5VS
0_0805_5%
150U_D2_6.3VM
VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
GND
VCC12
GND
1
R617
2
@ 1K_0402_1%
+5VS
Close to SATA HDD
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
GND
GND
15
14
SANTA_206401-1_13P
CONN@
KALA0 used
24
23
OCTEK_SAT-22SU1G_NR
CONN@
KALA0 used
JP2
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
C316 1
C315 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
C318 1
C317 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_STX_C_DRX_P3
SATA_STX_C_DRX_N3
C320 1
C319 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_DTX_SRX_N3
SATA_DTX_SRX_P3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
31
32
33
34
35
36
Second ODD
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
GND
GND
GND
GND
GND
GND
Second HDD
B
C314 1
C313 1
+5VS
+3VS
ACES_88018-304G
CONN@
+5VS
+3VS
0.1U_0402_16V4Z
C574
C577
1000P_0402_50V7K
0.1U_0402_16V4Z
C579
C580
10U_0805_10V4Z
0.1U_0402_16V4Z
C572
2
1000P_0402_50V7K
C573
C571
2
10U_0805_10V4Z
Compal Secret Data
2005/03/08
Issued Date
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
1
22
of
47
+5VS
+R_CRT_VCC
1.1A_6VDC_FUSE
1
C407
0.1U_0402_16V4Z
W=40mils
RB491D_SC59-3
+CRT_VCC
W=40mils
F1
D17
CRT Connector
D18
D19
D20
@
@
@
DAN217_SC59 DAN217_SC59 DAN217_SC59
+5VS
L32
1
2 CRT_R_L
FCM2012CF-800T06_2P
L34
1
2 CRT_G_L
FCM2012CF-800T06_2P
L33
1
2 CRT_B_L
FCM2012CF-800T06_2P
2
R339
R338
R340
140_0402_1%
C408
C412
C414
C413
150_0402_1% 2 8P_0402_50V8D 2 8P_0402_50V8D 2 8P_0402_50V8D
1
C410
6P_0402_50V8D
2
6P_0402_50V8D
2
C409
6P_0402_50V8D
C406
100P_0402_50V8J
+CRT_VCC
0_0402_5%
1
L37
2
MBC1608121YZF_0603
VSYNC_L
C411
1
D_CRT_HSYNC
C424
2
74AHCT1G125GW_SOT353-5
+CRT_VCC
2
0.1U_0402_16V4Z
CRT_VSYNC
0_0402_5%
CRT_DET# <18>
68P_0402_50V8J
2
D_DDC_CLK
1
5
2
R636
100K_0402_5%
C422
68P_0402_50V8J
U35
Y
D_CRT_VSYNC
+CRT_VCC
1
R356
1
C423
2
P
1
C433
OE#
CONN@
D_DDC_DATA
U36
CRT_HSYNC
1
R354
HSYNC_L
10P_0402_50V8J
1
10K_0402_5%
2
MBC1608121YZF_0603
10P_0402_50V8J
2
R360
1
2
0.1U_0402_16V4Z
OE#
1
C434
1
L38
16
150_0402_1%
KAW60 used
SUYIN_070549FR015S208CR
17
CRT_B
<13> GMCH_CRT_B
CRT_G
<13> GMCH_CRT_G
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
CRT_R
<13> GMCH_CRT_R
74AHCT1G125GW_SOT353-5
Close to Conn side

+CRT_VCC
+3VS
R77
R72
3
S
D_DDC_DATA
2
G
6.8K_0402_5%
2
6.8K_0402_5%
3
S
1
D
D_DDC_CLK
GMCH_CRT_DATA <13>
2
G
Q50
BSH111 1N_SOT23-3
GMCH_CRT_CLK <13>
Q51
BSH111 1N_SOT23-3
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Secret Data
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Date:
Rev
C
401743
Sheet

E
23
of
47
+3VS
INVT_PWM
LCD POWER CIRCUIT
D21
BAS16_SOT23-3
@
C426
@ 0.1U_0402_16V4Z
C416
1U_0402_6.3V4Z
@
D
+3VS
+LCDVDD
+3VALW
2
R274
300_0603_5%
W=60mils
R347
Q23
JLVDS1
AO3413_SOT23-3
1
1K_0402_5%
1
W=60mils
C431
2 0.047U_0402_16V7K
@ 100K_0402_5%
C415
4.7U_0805_10V4Z
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
+INVPWR_B+
+LCDVDD
+3VS
<13> GMCH_LCD_CLK
<13> GMCH_LCD_DATA
+LCDVDD
3
Q22B
1
2
LCD/PANEL CONN.
R345
10K_0402_5%
@ 4.7U_0805_10V4Z
100K_0402_5%
2
R278
GMCH_ENVDD 5
<13> GMCH_ENVDD
C77
R348
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Q22A
1
6 2
EDID_LCD_CLK
EDID_LCD_DAT
<13> GMCH_TZOUT0<13> GMCH_TZOUT0+
C420
0.1U_0402_16V4Z
<13> GMCH_TZOUT1+
<13> GMCH_TZOUT1<13> GMCH_TZOUT2+
<13> GMCH_TZOUT2<13> GMCH_TZCLK<13> GMCH_TZCLK+
<18>
<18>
R759 1
R760 1
USB20_N3
USB20_P3
2 0_0402_5%
2 0_0402_5%
USB20_CMOS_N3
USB20_CMOS_P3
L77
4
1
@
EC_INVT_PWM
<28> EC_INVT_PWM
<13> GMCH_INVT_PWM
GMCH_INVT_PWM
1
R764
4
1
GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DAC_BRIG
INVT_PWM
DISPOFF#
+LCDVDD
GMCH_TXOUT0- <13>
GMCH_TXOUT0+ <13>
GMCH_TXOUT1- <13>
GMCH_TXOUT1+ <13>
GMCH_TXCLK- <13>
GMCH_TXCLK+ <13>
R761 1
R762 1
ACES_88242-4001
CONN@
C768 0.1U_0402_16V4Z
2
WCM2012F2S-900T04_0805
+INVPWR_B+
1
2
4.7K_0402_5%
2
1
1
D2
@
INVT_PWM
2
0_0402_5%
C362
680P_0402_50V7K 68P_0402_50V8J
2
2
R414
@
+LCDVDD
100K_0402_5%
D
Q69
2N7002_SOT23-3
DAC_BRIG
C371 1
2 220P_0402_50V7K
INVT_PWM
C372 1
2 220P_0402_50V7K
Q52B
2N7002DW-T/R7_SOT363-6
DISPOFF#
C377 1
2 220P_0402_50V7K
C379
DISPOFF#
2
RB751V_SOD323
@
1
R768
2
G
3
1
R23
BKOFF#
4.7K_0402_5%
Q52A
2N7002DW-T/R7_SOT363-6
BKOFF#
4.7K_0402_5%
1
2
@
4.7K_0402_5%
GMCH_INVT_PWM
R770
0_0402_5%
@
2
1
<28>
2
0_0402_5%
B+
L15 2
1
FBMA-L11-201209-221LMA30T_0805
1
R763
R39
L20 2
1
FBMA-L11-201209-221LMA30T_0805
W=40mils
R1
+3VS
R30
+3VS
+3VALW
1 VARY@ 2
R767
0_0402_5%
R769
0_0402_5%
@
2
1
2
4.7K_0402_5%
2 0_0603_5%
2 0_0603_5%
INVT_PWM
2
0_0402_5%
+3VS
1
R21
KALA0 used
+3VS
EC_INVT_PWM
GMCH_TXOUT2+ <13>
GMCH_TXOUT2- <13>
VARYBRIGHT FUNCTION
DAC_BRIG <28>
C383
C382
10U_0805_10V4Z
0.1U_0402_16V4Z
Compal Secret Data
2005/03/08
Issued Date
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet
1
24
of
47
+3V_LAN
1
L88 8132@
C932
2
4.7UH_1008HC-472EJFS-A_5%_1008
0.1U_0402_16V4Z
R821
Place Close to Chip
R822
4.7K_0402_5%
+AVDD_CEN
+1.8_VDD/LX
4.7K_0402_5%
1 8114@ 2
R820
0_0603_5%
U84
R8441
2 0_0603_5%
C933
4.7U_0805_10V4Z
8132@
+3V_LAN
+2.5V_VDDH/VDD17 1
+2.5V_VDDH
1
2
2
R824 8132@ 0_0603_5%
R825 8114@ 0_0603_5%
C934
1
2
3
4
0.1U_0402_16V4Z
2 8132@
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
TWSI_SCL
TWSI_SDA
LAN_MIDI0+ R843 2
1 49.9_0402_1%
LAN_MIDI0-
R845 2
1 49.9_0402_1%
LAN_MIDI1+ R846 2
1 49.9_0402_1%
LAN_MIDI1-
1 49.9_0402_1%
R847 2
C978 1
2 0.1U_0402_16V4Z
C979 1
2 0.1U_0402_16V4Z
D
AT24C02BN-SH-T_SO8
@
U85
VDD18O
VDD33
1 0.1U_0402_16V7K
+2.5V_VDDH/VDD17
VDDHO
CTR12
CTR12
3
4
PERSTn
WAKEn
<13,15,17,28,31> PLT_RST#
<28> EC_PME#
1
R829
+3V_LAN
2
4.7K_0402_5%
<16> CLK_PCIE_LAN
<16> CLK_PCIE_LAN#
RX_P
RX_N
PCIE_PTX_IRX_P1
38
TX_P
PCIE_PTX_IRX_N1
37
TX_N
9
10
XTLO
XTLI
31
33
SMCLK
SMDATA
12
34
RBIAS
TESTMODE
49
GND
2
C940
2
C943
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
LAN_X1
LAN_X2
LAN_X2
25MHZ_20P
2
1
R831 2.37K_0402_1%
C946
27P_0402_50V8J
REFCLKN
44
Y8
40
<12> PCIE_ITX_C_PRX_P1
Place Close to Chip
REFCLKP
<12> PCIE_ITX_C_PRX_N1
<12> PCIE_PTX_C_IRX_N1
VBG1P18V
43
<12> PCIE_PTX_C_IRX_P1
LAN_X1
7
41
C947
27P_0402_50V8J
29
30
LED_ACTn
LED_10_100n
47
48
LED_DUPLEXn
27
TRXP0
TRXN0
TRXP1
TRXN1
13
14
17
18
AVDDL_REG
AVDDL/AVDDL_REG
11
42
TWSI_SCL
TWSI_SDA
LAN_ACTIVITY#
LAN_LINK#
1
R261
LAN_ACTIVITY# <26>
LAN_LINK# <26>
2
0_0402_5%
LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1-
LAN_CLKREQ# <16>
LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1-
<26>
<26>
<26>
<26>
Layout Notice : Close to chip
AVDDVCO1
AVDDVCO2
+3V_LAN
s
o
r
e
h
t
A
8114@
2
1
C937
1000P_0402_50V7K
2
1
C938
0.1U_0402_16V7K
2
1
C939
0.1U_0402_16V7K
TWSI_CLK
TWSI_DATA
AR8114A 10/100 LAN
DVDDL0
DVDDL1
DVDDL2
DVDDL3
28
32
45
46
+1.2_DVDDL
AVDDL0
AVDDL1
AVDDL2
AVDDL3
AVDDL4
8
16
22
36
39
+1.2_AVDDL
AVDDH0
AVDDH1
AVDDH2
15
19
25
+2.5V_VDDH
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
20
21
23
24
26
35
1
R830
+3VALW
0.1U_0402_16V4Z
2
0_1206_5%
C944
C941
4.7U_0805_10V4Z
C942
C945
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3V_LAN
1
C948
0.1U_0402_16V4Z
8114@
R832
10K_0402_1%
8114@
Q73
1 8132@ 2+2.5V_VDDH
R833
0_0402_5%
AR8114-AL1E_QFN48_6X6
CTR12
change to AR8132L-AL1E
1
4
2
NJT4030PT1G_SOT223
8114@
+1.2_AVDDL
1
1
C950
C951
10U_0805_10V4Z
0.1U_0402_16V4Z
8114@
8114@
2
2
Place Close to Pin 28324546
+1.2_AVDDL
L89
FBMA-L11-201209-221LMA30T_0805
1
2
8114@
+1.2_DVDDL
+1.2_DVDDL
C953
C955
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
1
1
1
8132@
1
2
R834
0_0603_5%
R835
1
0_0603_5%
2
1
1
C956
1000P_0402_50V7K
C957
1U_0603_10V4Z
2
2
8114@
2
2
2
2
C983
C954
1U_0603_10V4Z 0.1U_0402_16V4Z
AVDDVCO1
C949
0.1U_0402_16V4Z
8132@
B
C952
0.1U_0402_16V4Z
Place Close to Pin151925

R546 1
2 0_0805_5%
AVDDVCO2
+2.5V_VDDH
2
A
C982 2
8132@
+3V_LAN
8114@
C935 2
1 1U_0603_10V4Z
WAKEn
8114: Internal PU
8132: OD
+1.8_VDD/LX
1
8114@ 1U_0603_10V4Z
2
C936
C958
0.1U_0402_16V4Z
C960
0.1U_0402_16V4Z
1
1
1
Place Close to Pin816223639

C984
C963
C965
+1.2_AVDDL 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
1
1
1
1
8132@
2
2
C959
1U_0603_10V4Z
C966
C961
0.1U_0402_16V4Z
8114@
2
2
2
2
C962
C964
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
8114: R546 need change to bead
2005/07/29
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
1
25
of
47
+AVDD_CEN
C967
1
2
220P_0402_50V7K
R836
0_0603_5%
JRJ1
LAN_MIDI0+
LAN_MIDI0-
<25> LAN_MIDI0+
<25> LAN_MIDI0-
1
2
3
4
5
6
7
8
LAN_MIDI1+
LAN_MIDI1-
<25> LAN_MIDI1+
<25> LAN_MIDI1-
RD+
RDCT
NC
NC
CT
TD+
TD-
2
R837
<25> LAN_ACTIVITY#
T1
RX+
RXCT
NC
NC
CT
TX+
TX-
2
R14
RJ45_MIDI0+
RJ45_MIDI0-
16
15
14
13
12
11
10
9
1 LAN_ACTIVITY#_R
510_0402_5%
1
5.11K_0402_1%
12
Amber LED+
11
Amber LED-
PR4-
PR4+
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI1-
R840
75_0402_1%
C969
LAN_LINK#
<25> LAN_LINK#
C970
+3V_LAN
2
R838
10
SHLD1
15
SHLD2
14
SHLD1
13
Green LED+
FOX_JM36113-L2R8-7F
CONN@
0.1U_0402_16V4Z
SHLD2
Green LED-
1
510_0402_5%
RJ45_GND
0.1U_0402_16V4Z
2
R839
75_0402_1%
2
LAN_TCT
350uH_NS0013LF
16
C968
220P_0402_50V7K
RJ45_GND
LANGND
1
C973
1000P_1206_2KV7K
1
C974
2
C975
4.7U_0805_10V4Z
0.1U_0402_16V4Z
LAN_LINK#
LAN_ACTIVITY#_R
3
LAN_ACTIVITY#_R
1
2
C976
@ 68P_0402_50V8J
D16
@
LAN_LINK#
H18
H_3P4
PJDLC05_SOT23-3
C977
@ 68P_0402_50V8J
H17
H_3P4
@
H22
H_3P3
@
H27
H_2P3
@
H12
H_3P3
H3
H_3P3
H23
H_3P4
H6
H_2P8
H2
H_3P3
H24
H_3P4
H16
H_4P2
@
H20
H_3P4
@
H25
H_3P4
@
1
1
H8
H_4P0N
@
H26
H_3P4
H4
H_3P4
H21
H_4P6X4P0N
FD2
@
FIDUCIAL_C40M80
FD1
FD3
@
FIDUCIAL_C40M80
FD4
@
FIDUCIAL_C40M80
H15
H_4P2
H10
H_4P2
H5
H_2P8
H19
H_3P4
H9
H_3P4
H11
H_4P2
H7
H_3P4
H14
H_3P4
H1
H_3P4
Compal Secret Data
2005/03/08
Issued Date
2010/03/12
Deciphered Date
Title
Custom
FIDUCIAL_C40M80
Date:

SCHEMATIC, MB A5481
Rev
C
401743
Sheet

1
26
of
47
2
R675
1
0_0402_5%
U77
+3VS
D
+3V_CARD
@
1
2
R548
0_0805_5%
1
2
R547
0_0805_5%
+3VALW
+3VS
2
C851
+XDPWR_SDPWR_MSPWR
C852
1 C853
0.1U_0402_16V4Z
RST#
MODE_SEL
XTLO
XTLI
4.7U_0603_6.3V6K
R674
100K_0402_5%
1
R335
USB20_N4
USB20_P4
<18> USB20_N4
<18> USB20_P4
<34> 5IN1_LED#
1
0.1U_0402_16V4Z
RST#
2
0_0402_5%
1
3
7
9
11
33
AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3
8
44
45
47
48
3V3_IN
RST#
MODE_SEL
XTLO
XTLI
4
5
14
DM
DP
GPIO0
C854
1U_0402_6.3V4Z
MODE_SEL
R680
0_0402_5%
2
2
@ C855
47P_0402_50V8J
RREF
12
32
DGND
DGND
6
46
AGND
AGND
R678
6.19K_0402_1%
2
0_0402_5%
1
C856
XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
MS_INS#_SP9
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
XTAL_CTR
MS_D5
13
24
EEDO
EECS
EESK
SD_CMD
15
16
17
36
1
C860
2
1U_0402_6.3V4Z
D
XDCLE
XDCE#
XDALE
SDDAT2_XDRE#
SDDAT3_XDWE#
XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L
SDDAT6_XDD7_MSD3
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
XDD5_MSBS
XDD4_SDDAT1
SDCD
SDWP
XDCD
XTAL_CTR
2
R681
2
R671
1
0_0603_5%
SDCLK_XDD1_MSCLK
1
0_0402_5%
XTAL_CTR
If Open , use 12MHz. crystal
If Pull high , use CLKGEN 48MHz.
+3VS
SD_CMD
RTS5159-GR_LQFP48_7X7
R672
0_0402_5%
@ Y7
12MHZ_16PF_6X12000012
2
C858
XTLI
2
6P_0402_50V8D
R673
10_0402_5%
1
R676
<16> CLK_48M_SD
10
22
30
VREG
MS_D4
NC
10P_0402_50V8J
@
1
2
C857
6P_0402_50V8D
XTLO
EMI
+CARDPWR
+CARDPWR
B
+CARDPWR
1
C477
Close to CLK_SD_48M via
C342
C480
0.1U_0402_16V4Z
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
+XDPWR_SDPWR_MSPWR
0.1U_0402_16V4Z
+CARDPWR
1
R318
EMI
32
10
9
8
7
6
5
4
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE
34
33
35
40
39
38
37
36
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
11
31
7IN1 GND
7IN1 GND
2
0_0603_5%
41
42
1
A
R295
100K_0402_5%
C348
0.1U_0402_16V4Z
7 IN 1 CONN
SD-VCC
MS-VCC
21
28
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW
20
14
12
30
29
27
23
18
16
25
1
SD-WP-SW
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
26
17
15
19
24
22
13
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2
SD_CMD
SDCD
SDWP
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3
MS_INS#
XDD5_MSBS
C862
22P_0402_50V8J
7IN1 GND
7IN1 GND
TAITW_R015-B10-LM
CONN@
JAWD0 used
XD-VCC
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3
+5VS
1 C859
JREAD1
2005/07/29
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
1
27
of
47
C566
EC_SMB_DA1
2 100K_0402_5%
LID_SW#
R634 2
1 47K_0402_5%
KSO1
R639 2
1 47K_0402_5%
KSO2
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
EC test-mode issue
+3VS
R731
1
2.2K_0402_5%
EC_SMB_CK2
2
1
R732
EC_SMB_DA2
2
2.2K_0402_5%
+5VS
1 TP_CLK
R208
1 TP_DATA
R207
@
1
R519
2
10K_0402_5%
R460
1
<19> EC_THERM#
ENBKL
0_0402_5%
EC_THERM#_R
2
<41>
<41>
<8>
<8>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<18> PM_SLP_S3#
<18> PM_SLP_S5#
<18> EC_SMI#
<6> FAN_SPEED1
<33>
ON/OFF
<34> PWR_SUSP_LED
<34> NUM_LED#
6
14
15
16
17
18
19
25
28
29
E51TXD_P80DATA 30
E51RXD_P80CLK 31
32
34
36
EC_CRY1
EC_CRY2
4
OUT
IN
NC
2
67
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_INVT_PWM <24>
BEEP#
<35>
FANPWM <6>
ACOFF <40>
BATT_TEMP
BATT_OVP
AD_BID0
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
E51RXD_P80CLK
E51TXD_P80DATA
BATT_TEMP <41>
BATT_OVP <40>
ADP_I
<40>
R656
2 0_0402_5%
+3VALW
DAC_BRIG <24>
EN_DFAN1 <6>
IREF
<40>
CALIBRATE# <40>
EC_MUTE#
EC_RSMRST#
EC_MUTE# <36>
TP_LOCK_LED#
TP_CLK
TP_DATA
E51RXD_P80CLK <31>
E51TXD_P80DATA <31>
ACES_85205-0400
CONN@
AD_PID0
@ C762
0.1U_0402_16V4Z
U45
RSMRST#
@ NC7SZ08P5X_NL_SC70-5
TP_LOCK_LED# <34>
TP_CLK <29>
TP_DATA <29>
RSMRST# <18>
R740
R657
10K_0402_5%
10K_0402_5%
3S/4S#
<40>
65W/90W# <40>
EC_VLDT_EN <33>
LID_SW# <34>
LID_SW#
SPI Device Interface

SPI Flash ROM
1
2
3
4
EC_SI_SPI_SO <30>
EC_SO_SPI_SI <30>
EC_SPICLK <30>
EC_SPICS#/FSEL# <30>
Project ID
Please see page 3.
+3VALW
GPIO
SM Bus
17@
Ra
FSTCHG
FSTCHG <40>
BATT_GRN_LED# <34>
CAPS_LED# <34>
BATT_AMB_LED# <34>
PWR_LED <34>
SYSON
<37,44>
VR_ON <45>
ACIN
<19,37,38,40>
ACIN
R186
0--NCWG0
3--NAL00
7--NCWH0
100K_0402_5%
AD_PID0
15@
Rb
R534
100K_0402_5%
C309
0.1U_0402_16V4Z
B
GPI
XCLK1
XCLK0
GND
GND
GND
GND
GND
122
123
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
15P_0402_50V8J
2
EC_RSMRST#
EC_LID_OUT# <18>
EC_ON
<33>
EC_SWI# <18>
EC_PWROK <33>
BKOFF# <24>
WL_OFF# <31>
Board ID <VB support>

Please see page 3.
+3VALW
EC_THERM#_R
VGATE
ENBKL
EAPD
<45>
<13>
<35>
R219
Ra
SUSP#
<33,37,43>
PBTN_OUT# <18>
EC_PME# <25>
@
100K_0402_5%
AD_BID0
Chagne to D3 version
KB926QFD2_LQFP128_14X14
R215
C674
Rb
4.7U_0805_10V4Z
8.2K_0402_5%
C306
0.1U_0402_16V4Z
20mil
L69
ECAGND 1
2
FBMA-L11-160808-800LMT_0603
NC
15P_0402_50V8J
2
A
C343
68
70
71
72
1
2
3
4
C344
EC_CRY2
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
11
24
35
94
113
EC_CRY1
63
64
65
66
75
76
PS2 Interface
Place on MiniCard
2
4.7K_0402_5%
2
4.7K_0402_5%
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
For EC Tools
2 2.2K_0402_5%
R19
21
23
26
27
PWM Output
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
100P_0402_50V8J
R730 1
ECRST#
<18> EC_SCI#
<17> PM_CLKRUN#
EC_PME#
2 2.2K_0402_5% EC_SMB_CK1
C676 1
1 10K_0402_5%
100P_0402_50V8J
ACIN
JP37
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
AD
100P_0402_50V8J
R729 1
12
13
37
20
38
C673 1
R514 2
<17,21> CLK_PCI_EC
<13,15,17,25,31> PLT_RST#
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
C672 1
BATT_TEMP
+3VALW
1
2
3
4
5
7
8
10
BATT_OVP
+3VALW
AGND
1
0.1U_0402_16V4Z
<18> EC_GA20
<18> EC_KBRST#
<17> SERIRQ
<17> LPC_FRAME#
<17> LPC_AD3
<17> LPC_AD2
<17> LPC_AD1
<17> LPC_AD0
69
2
C549
47K_0402_5%
ECRST#
1
0.1U_0402_16V4Z
KSO[0..17]
+3VALW
AVCC
<29,34> KSO[0..17]
U27
VCC
VCC
VCC
VCC
VCC
VCC
<29,34> KSI[0..7]
9
22
33
96
111
125
KSI[0..7]
Please close to EC pin
C561
1000P_0402_50V7K
C568
1000P_0402_50V7K
1
1
C557
2
2
0.1U_0402_16V4Z
ECAGND
2
2
0.1U_0402_16V4Z
C476
L48
1
2 +EC_VCCA
FBMA-L11-160808-800LMT_0603
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1 C567
1
C569
R633
@ 10_0402_5%
R632
2
+3VALW
CLK_PCI_EC
C689
@ 22P_0402_50V8J
Compal Secret Data
Y1
2007/5/18
Issued Date
32.768KHZ_12.5P_MC-306
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet
1
28
of
47
For 17"
For 15"
BTN_L
BTN_R
SW3
15@ SMT1-05-A_4P
3
1
TP_CLK
BTN_R
TP_DATA
BTN_L
2
5
6
2
5
6
Right
BTN_R
2
5
6
Left
SW2
15@ SMT1-05-A_4P
3
1
5
6
BTN_L
Right
SW5
17@ SMT1-05-A_4P
3
1
Left
SW4
17@ SMT1-05-A_4P
3
1
D15
C174 1
100P_0402_50V8J
100P_0402_50V8J
D14
PJDLC05_SOT23-3
PJDLC05_SOT23-3
C169 1
TP_CLK
TP_DATA
Change to SCA00000200
To TP/B Conn.
JTP1
+5VS
<28>
<28>
TP_CLK
TP_DATA
+5VS
6
5
4
3
2
1
TP_CLK
TP_DATA
BTN_L
BTN_R
C137
0.1U_0402_16V4Z
ACES_85201-0605
CONN@
KALA0 used
KSI[0..7]
INT_KBD Conn.
KSI[0..7]
KSO[0..17]
KB1 for 15"

KB2 for 17"
<28,34>
KSO[0..17] <28,34>
JKB1
(Left)
KSO15
C243 1
100P_0402_50V8J
KSO7
C231 1
100P_0402_50V8J
KSO14
C242 1
100P_0402_50V8J
KSO6
C230 1
100P_0402_50V8J
KSO13
C241 1
100P_0402_50V8J
KSO5
C229 1
100P_0402_50V8J
KSO12
C240 1
100P_0402_50V8J
KSO4
C228 1
100P_0402_50V8J
KSI0
C239 1
100P_0402_50V8J
KSO3
C227 1
100P_0402_50V8J
KSO11
C238 1
100P_0402_50V8J
KSI4
C226 1
100P_0402_50V8J
KSO10
C237 1
100P_0402_50V8J
KSO2
C225 1
100P_0402_50V8J
KSI1
C236 1
100P_0402_50V8J
KSO1
C224 1
100P_0402_50V8J
KSI2
C235 1
100P_0402_50V8J
KSO0
C223 1
100P_0402_50V8J
KSO9
C234 1
100P_0402_50V8J
KSI5
C222 1
100P_0402_50V8J
KSI3
C233 1
100P_0402_50V8J
KSI6
C221 1
100P_0402_50V8J
KSO8
C232 1
100P_0402_50V8J
KSI7
C220 1
100P_0402_50V8J
KSO16
C245 1
100P_0402_50V8J
KSO17
C244 1
100P_0402_50V8J
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
(Right)
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSO0 G2
KSO1 G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
ACES_88747-2601
CONN@
hexainf@hotmail.com
GRATIS - FOR FREE
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
(Right)
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSO0 G2
KSO1 G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
28
27
ACES_88747-2601
CONN@
Compal Secret Data
Issued Date
JKB2
(Left)
28
27
2005/03/08
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet
29
of
47
+3VALW
1
R618
C675 1
2
0_0603_5%
2 0.1U_0402_16V4Z
+SPI_VCC
U17
<28> EC_SPICS#/FSEL#
+3VALW
2
R619 2
R621
1
SPI_WP#
1
3
1 4.7K_0402_5% SPI_HOLD# 7
4.7K_0402_5%
4
CE#
WP#
HOLD#
VSS
VDD
SCK
SI
SO
8
6
5
2
EC_SPICLK_R
R620 1
EC_SO_SPI_SI_R R622 1
EC_SI_SPI_SO_R R623 1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
EC_SPICLK <28>
EC_SO_SPI_SI <28>
EC_SI_SPI_SO <28>
MX25L8005M2C-15G_SOP8
SA00000XT00 : S IC FL 8M MX25L8005M2C-15G SOP 8P

ENE suggestion SPI Frequency over 66MHz
SST: 50MHz
MXIC: 70MHz
ST: 40MHz
R257
EC_SPICLK_R 1
@ 22_0402_5%
C296
1
2
@ 10P_0402_50V8J
ONLY MXIC used in this project (66MHz)

U44
EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#
1
3
7
4
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI
EC_SI_SPI_SO
MX25L512AMC-12G_SO8
@
Reserved for BIOS simulator.

Footprint SO8
SPI ROM Footprint 150mil
Issued Date
Compal Secret Data
2005/03/08
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet
30
of
47
+3VS_WLAN
+1.5VS
C442
4.7U_0805_10V4Z
C441
0.1U_0402_16V4Z
+3VALW
C439
4.7U_0805_10V4Z
C438
0.1U_0402_16V4Z
C440
0.1U_0402_16V4Z
C437
0.1U_0402_16V4Z
For Wireless LAN
<16> MINI1_CLKREQ#
<16> CLK_PCIE_MINI1#
<16> CLK_PCIE_MINI1
<12> PCIE_PTX_C_IRX_N0
<12> PCIE_PTX_C_IRX_P0
<12> PCIE_ITX_C_PRX_N0
<12> PCIE_ITX_C_PRX_P0
+3VS_WLAN
E51TXD_P80DATA
E51RXD_P80CLK
R654 1
2 0_0402_5% E51TXD_P80DATA_R
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
R487 1
2 0_1206_5%
+3VS
+3VS_WLAN
+1.5VS
Mini Card Power Rating

R655 0_0402_5%
WL_OFF#_R 1
2
PLT_RST#
R246 1
2 0_0603_5%
R243 1
2 0_0603_5%
@
Power
WL_OFF# <28>
PLT_RST# <13,15,17,25,28>
+3VS
+3VALW
SB_CK_SCLK <10,11,16,18>
SB_CK_SDAT <10,11,16,18>
Primary Power (mA)
Auxiliary Power (mA)

Normal
Peak
Normal
+3VS
1000
750
+3VALW
330
250
250 (wake enable)
+1.5VS
500
375
5 (Not wake enable)
USB20_N5 <18>
USB20_P5 <18>
(MINI1_LED#)
WL_ON_LED# <34>
R752 0_0402_5%
R550
@100K_0402_5%
G1
G2
G3
G3
<28> E51TXD_P80DATA
<28> E51RXD_P80CLK
+3VS_WLAN
JMINI2
1
3
5
7
9
11
13
15
53
54
55
56
For MINICARD Port80 Debug
<18> SB_PCIE_WAKE#
0_0402_5%
2
R653
1
@
FOX_AS0B226-S99N-7F
CONN@
+3VALW
H:9.9mm
3
2005/06/20
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

E
31
of
47
USB CONN. 1 & 2

+USB_VCCA
+USB_VCCA
W=80mils
W=80mils
1
1
C478+
C1 +
C474
C2
@
150U_D2_6.3VM
470P_0402_50V7K
150U_D2_6.3VM
470P_0402_50V7K
JUSB1
USB20_N0
USB20_P0
<18> USB20_N0
<18> USB20_P0
R598 1
R600 1
@
@
2 0_0402_5%
2 0_0402_5%
USB20_N0_R
USB20_P0_R
L67
4
1
WCM2012F2S-900T04_0805
JUSB2
1
2
3
4
VCC
DD+
GND
5
6
7
8
GND1
GND2
GND3
GND4
USB20_N1
USB20_P1
<18> USB20_N1
<18> USB20_P1
R599 1
R601 1
@
@
2 0_0402_5%
2 0_0402_5%
USB20_N1_R
USB20_P1_R
L68
4
SUYIN_020173MR004G565ZR
CONN@
KALA0 used
1
2
3
4
VCC
DD+
GND
5
6
7
8
GND1
GND2
GND3
GND4
SUYIN_020173MR004G565ZR
CONN@
KALA0 used
WCM2012F2S-900T04_0805
D31
USB20_N0_R
CH3
Vp
CH2
Vn
CH1
USB20_N1_R
+3VALW
+5VALW
U4
C111
GND
IN
IN
EN#
100K_0402_5%
OUT
OUT
OUT
FLG
8
7
6
5
USB20_P1_R
1
2
3
4
+USB_VCCA
R42
+USB_VCCA
R171
1
TPS2061DRG4_SO8
4.7U_0805_10V4Z
2
R677
10K_0402_5%
2
2
2
1
0_0402_5%
USB_OC#1 <18>
CH4
USB20_P0_R
CM1293-04SO_SOT23-6
USB_OC#0 <18>
C133
0.1U_0402_16V4Z
<37,43> SYSON#
2005/06/20
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

E
32
of
47
Power ON Circuit
For South Bridge
+3VS
+3VALW
+3VALW
note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,

SUSP# goes to low after SB_PWRGD goes to low for power
down.
C322
1U_0603_10V4Z
T1
14
P
1
R191
2
@ 0_0402_5%
SB_PWRGD <8,18>
VLDT_EN
2
G
Q11
2N7002_SOT23
O
7
SUSP
<37>
I
G
1
D
U13B
SN74LVC14APWLE_TSSOP14
14
R192
180K_0402_5%
U13A
NB_PWRGD
1
R198
<28> EC_PWROK
0_0402_5%
SB_PWRGD
+3VS
T2
For +1.2HT
SUSP#
+3VALW
+3VALW
+1.8VS
14
I
0.1U_0402_16V4Z
1
R183
2
0_0402_5%
VLDT_EN <37,42>
+3VALW
TOP Side
U13F
14
U13E
14
+3VALW
10
13
12
+3VALW
Power Button
R765 10K_0603_5%
O
G
2
@ 0_0402_5%
<28> EC_VLDT_EN
11
1
R180
5
C321
U13D
10K_0402_1%
D12
SUSP# 1
<28,37,43> SUSP#
U13C
14
R195
R281
100K_0402_5%
Bottom Side
D10
ON/OFFBTN#
<34> ON/OFFBTN#
R766 10K_0603_5%
ON/OFF
<28>
51ON#
51ON#
<38>
DAN202UT106_SC70-3
3
EC_ON
2
G
R290
10K_0402_5%
D11
RLZ20A_LL34
1
<28>
1
EC_ON
C358
1000P_0402_50V7K
Q17
2N7002_SOT23
@ SW10
SMT1-05-A_4P
1
3
ON/OFFBTN#
4
6
5
MP would remove
4
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Secret Data
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
E
33
of
47
PWR_LED#
MDC Conn.
JMDC1
Q68B
2N7002DW-T/R7_SOT363-6
PWR_LED
R291
HDA_SYNC_MDC
R357 1
2 33_0402_5%
HDA_RST_MDC#
<18> HDA_SYNC_MDC
<18> HDA_SDIN1
<18> HDA_RST_MDC#
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
R254
1
2
4
6
8
10
12
0_0402_5%
2
+3VALW
+3VALW
20mil
HDA_BITCLK_MDC
HDA_BITCLK_MDC <18>
100K_0402_5%
1
3
5
7
9
11
HDA_SDOUT_MDC
<18> HDA_SDOUT_MDC
<28>
ACES_88018-124G
CONN@
Connector for MDC Rev1.5
Q68A
2N7002DW-T/R7_SOT363-6
1U_0603_10V4Z
0_0402_5%
C432
22P_0402_50V8J
For EMI
<28> PWR_SUSP_LED
C3
R256
GND
GND
GND
GND
GND
GND
13
14
15
16
17
18
PWR_SUSP_LED#
R292
100K_0402_5%
To PWR LED/B
LED1
R250 1.2K_0402_5%
1
2
4
YG
PWR_LED#
PWR_SUSP_LED#
+5VS +3VALW +5VALW
HT-297UD/CB BLUE/AMB
HARVATEK
LED2
+5VALW
R253 1K_0402_5%
1
2
2
+5VALW
R252 1.2K_0402_5%
1
2
4
+3VS
JP14
YG
BATT_GRN_LED#
BATT_AMB_LED#
HT-297UD/CB BLUE/AMB
HARVATEK
BLUE/AMB LED
BATT_GRN_LED# <28>
BATT_AMB_LED# <28>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+5VALW
LID_SW#
TP_LOCK_LED#
KSO0
KSI2
PWR_SUSP_LED#
PWR_LED#
ON/OFFBTN#
KSI1
WL_ON_LED#
MEDIA_LED#
NUM_LED#
CAPS_LED#
LID_SW# <28>
TP_LOCK_LED# <28>
KSO0
<28,29>
KSI2
<28,29>
+5VS
+3VS
+3VALW
C435
C436
C444
C445
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ON/OFFBTN# <33>
KSI1
<28,29>
WL_ON_LED# <31>
NUM_LED# <28>
CAPS_LED# <28>
ACES_85201-20051
CONN@
+3VS
KSO0
2
+5VALW
R251 1K_0402_5%
1
2
2
KSI1
WL_BTN#
KSI2
TP_LOCK_BTN#
MEDIA_LED#
KSI3
KSI4
5IN1_LED# <27>
SATA_LED# <19>
Q67B
2N7002DW-T/R7_SOT363-6
KSI5
Q67A
2N7002DW-T/R7_SOT363-6
+5VS
+3VS
KSI6
Issued Date
Compal Secret Data
2005/06/20
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
34
of
47
+3VS
1
R784
+VDDA
2
0_0805_5%
+5VAMP
2
2
1
R786
R787
HD Audio Codec
C
2
2.4K_0402_1%
Q72
2
B
0.1U_0402_16V4Z
C903 1
1U_0402_6.3V4Z
MONO_IN
0.1U_0402_16V4Z
BEEP#
C902
1
1U_0402_6.3V4Z
<28>
22U_0805_6.3V6M
L81 1
2
FBMA-L11-201209-221LMA30T_0805
C900
R789
10K_0402_5%
RB751V_SOD323
C899
U81
60mil
C106
D38
L80 1
2
FBMA-L11-201209-221LMA30T_0805
+5VS
R783
20K_0402_1%
40mil
IN
GND
SHDN
OUT
BYP
+VDDA
@ G9191-475T1U_SOT23-5
4.75V
1
1
2
C901
0.01U_0402_25V7K
(output = 300 mA)
560_0402_5%
2SC2411KT146_SOT23-3
SB_SPKR
C904 1
1U_0402_6.3V4Z
560_0402_5%
<18>
R788
D37
RB751V_SOD323
L82
MBK1608121YZF_0603
1
2
10mil
1
+AVDD_HDA
0.1U_0402_16V4Z
35
AMP_LEFT
LOUT_R
36
AMP_RIGHT
16
MIC2_L
LOUT2_L
39
17
MIC2_R
LOUT2_R
41
23
LINE1_L
SPDIFO2
45
24
LINE1_R
DMIC_CLK1/2
46
18
LINE1_VREFO
NC
43
20
LINE2_VREFO
DMIC_CLK3/4
19
MIC2_VREFO
<28>
SENSE A
Impedance
PCBEEP_IN
RESET#
10
SYNC
1
R796
EAPD
2
0_0402_5%
PORT-A (PIN 39, 41)

PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
29
CPVEE
31
MIC1_VREFO
28
HPOUT_R
32
SDATA_OUT
47
EAPD
SPDIFO1
CBN
30
VREF
27
JDREF
40
HPOUT_L
33
AVSS1
AVSS2
26
42
DVSS1
DVSS2
1
R793
2
33_0402_5%
10mil
1
MIC1_VREFO_L
HP_RIGHT
CODEC_VREF
C918
2.2U_0402_6.3V6M
HP_RIGHT
20K
PORT-F (PIN 16, 17)
10K
PORT-G (PIN 43, 44)
5.1K
PORT-H (PIN 45, 46)
1
HP_LEFT
AGND
hexainf@hotmail.com
GRATIS - FOR FREE
A
1
R798
2
0_0805_5%
1
R799
2
0_0805_5%
1
R800
2
0_0805_5%
1
R801
2
0_0805_5%
1
R802
2
0_0805_5%
1
R803
2
0_0805_5%
GND
GNDA
2007/09/20
2010/03/12
Deciphered Date
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Date:
GNDA
Title
Size
B
B
GND
Compal Secret Data
Issued Date
HP_LEFT <36>
10mil
Change to ALC272X
DGND
HP_RIGHT <36>
HP_LEFT
SENSE B
<18>
HDA_SDIN0 <18>
2.2U_0402_6.3V6M
C917 1
ALC272-VA2-GR_LQFP48_7X7
Codec Signals
20K
37
CBP
GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B
48
39.2K
MONO_OUT
2
3
13
34
4
7
Sense Pin
MIC1_R
<18> HDA_SYNC_AUDIO
update this table
For EMI
HDA_BITCLK_AUDIO
MIC1_L
<18> HDA_RST_AUDIO#
SDATA_IN
2 C914
22P_0402_50V8J
2
1
0_0402_5%
C920
MIC1_C_R
22
4.7U_0805_6.3V6K
MONO_IN
12
1
R792
0.1U_0402_16V4Z
BITCLK
AMP_RIGHT <36>
10U_0805_10V4Z
44
6
AMP_LEFT <36>
C919
SENSE_A
SENSE_B
LOUT1_L
LINE2_R
MIC1_C_L
21
4.7U_0805_6.3V6K
1 20K_0402_1%
1 5.11K_0402_1%
LINE2_L
15
11
R794 2
R795 2
DVDD
14
C916
U82
R797
C915
2
0.1U_0402_16V4Z
<18> HDA_SDOUT_AUDIO
<36> MIC_PLUG#
<36> HP_PLUG#
10U_0805_10V4Z
C910
DVDD_IO
MIC1_R
20K_0402_1%
MIC1_R
+3VS
C907
MIC1_L
<36>
C906
MIC1_L
<36>
38
C908
10U_0805_10V4Z
C905
25
0.1U_0402_16V4Z
1
1
C909
AVDD2
L83 1
2
FBM-L11-160808-800LMT_0603
40mil
AVDD1
+VDDA
+3VS_DVDD
0.1U_0402_16V4Z

G
Sheet
35
H
of
47
+5VAMP
Int. Speaker Conn.
0.1U_0402_16V4Z
1
C921
10U_0805_10V4Z
1
C922
SPKL+
SPKL-
R804 1
R805 1
2 0_0603_5%
2 0_0603_5%
D39
C924
2
1
3900P_0402_50V7K R808
C925 1
C971
2
1
3900P_0402_50V7K R813
2 0.47U_0603_10V7K
AMP_C_LEFT
2
0_0603_5%
GAIN1
ROUT+
18
SPKR+
ROUT-
14
SPKR-
LOUT+
SPKL+
SPKL-
RIN-
@ R811
100K_0402_5%
G1
G2
Left
ACES_88266-02001
CONN@
R810 1
R807 1
2 0_0603_5%
2 0_0603_5%
20mil
SPK_R+
SPK_R-
D40
@
LOUT-
3
4
JSPK2
SPKR+
SPKR-
R812
100K_0402_5%
LIN+
LIN-
1
2
GAIN0
GAIN1
2
GAIN0
AMP_C_RIGHT 17
2
0_0603_5%
RIN+
1
2
1
2
1
2
3
4
G1
G2
Right
ACES_88266-02001
CONN@
PJDLC05_SOT23-3
<35> AMP_LEFT
<35> AMP_RIGHT
2 0.47U_0603_10V7K
@
PJDLC05_SOT23-3
@ R806
100K_0402_5%
VDD
PVDD1
PVDD2
R809
100K_0402_5%
16
15
6
+5VAMP
C923 1
SPK_L+
SPK_L3
20mil
10 dB
U83
JSPK1
EC_MUTE#
19
SHUTDOWN
12
BYPASS
10
Keep 10 mil width

2
C927
0.47U_0603_10V7K
LINE Out/Headphone Out
21
20
13
11
1
GND5
GND1
GND2
GND3
GND4
<28> EC_MUTE#
NC
TPA6017A2_TSSOP20
JHP1
8
7
2
C928
HP_RIGHT
<35> HP_LEFT
HP_LEFT
1
R814
1
R815
HPOUT_R_1 1
2
56.2_0402_1%
L84
HPOUT_L_1 1
2
56.2_0402_1%
L85
C929
HP_PLUG#
<35> HP_PLUG#
330P_0402_50V7K 330P_0402_50V7K
1
1
20mil
<35> HP_RIGHT
HPOUT_R_2
2
FBM-11-160808-700T_0603
2
FBM-11-160808-700T_0603
3
6
2
1
HPOUT_L_2
SINGA_2SJ-E351-S03
CONN@
MIC1_VREFO_L
MIC1_VREFO_L
MIC JACK
<35>
MIC1_R
<35>
MIC1_L
1
R818
1
R819
2
1K_0603_1%
2
1K_0603_1%
1
L86
1
L87
2 FBM-11-160808-700T_0603
1
MIC_PLUG# 5
4
2 FBM-11-160808-700T_0603
C930
220P_0402_50V7K
JMIC1
8
7
<35> MIC_PLUG#
R817
4.7K_0402_5%
2
R816
4.7K_0402_5%
RB751V_SOD323
D42
1 1
1 1
RB751V_SOD323
D41
MIC2_R_1
3
6
2
1
MIC2_L_1
1
C931
220P_0402_50V7K
SINGA_2SJ-E351-S01
CONN@
(HDA Jack)
2007/09/20
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

E
36
of
47
+5VALW
+3VALW TO +3VS
+5VALW TO +5VS
+3VS
R167
10K_0402_5%
+5VALW
S
S
S
G
1
2
3
4
1
R562
1U_0603_10V4Z
R508
100K_0402_5%
1
2
5VS_GATE
2
20K_0402_1%
+VSB
SUSP
2
G
2N7002_SOT23-3
C166
10U_0805_10V4Z
SUSP
SUSP
C165
1U_0603_10V4Z
0_0402_5%
5VS_GATE
2
Q12
2
G
<28,33,43> SUSP#
2N7002_SOT23
R586
10K_0402_5%
R728
1
C658
0.1U_0603_25V7K
R500
@
100K_0402_5%
D
C570
0.1U_0603_25V7K
<33>
10U_0805_10V4Z
C560
1
2
3
4
C143
4.7U_0805_10V4Z
2
Q29
S
S
S
G
AO4468_SO8
AO4468_SO8
D
D
D
D
D
D
D
D
8
7
6
5
8
7
6
5
10U_0805_10V4Z
U7
C562
U41
C559
+3VALW
+5VS
2
G
Q58
R31
10K_0402_5%
2N7002_SOT23
+1.8VS
U46
10U_0805_10V4Z
1U_0603_10V4Z
AO4430_SOIC8
C443
4.7U_0805_10V4Z
C759
0.1U_0603_25V7K 2
2
4.7U_0805_10V4Z
+1.2VALW
R698
470_0805_5%
+VSB
Q63
VLDT_EN#
2
G
2N7002_SOT23-3
2
G
Q64
C30
220U_B2_2.5VM_R25M
+5VALW
2N7002_SOT23-3
R725
10K_0402_5%
For PWR request
5VS_GATE
1
2
R699
33K_0402_5%
C758
2 R563
60.4K_0402_1%
10U_0805_10V4Z
1
2
3
4
S
S
S
G
VLDT_EN#
C632
0.1U_0603_25V7K
R700
33K_0402_5%
12/30 Change R563 to 60.4K
VLDT_EN
2N7002_SOT23
1
D
2 VLDT_EN#
G
Q13
2N7002_SOT23
2 SUSP
G
Q10
2N7002_SOT23
R185
470_0402_5%
1
1
1
1
R184
470_0402_5%
2SUSP
G
Q15
2N7002_SOT23
+1.1VS
2
1
D
2 SUSP
G
Q14
2N7002_SOT23
+NB_CORE
R181
470_0402_5%
+5VS
1
D
2 SYSON#
G
Q6
2N7002_SOT23
Q66
R726
100K_0402_5%
R270
470_0402_5%
1
1
R224
470_0402_5%
2 SUSP
G
Q36
2N7002_SOT23
Q65
2N7002_SOT23
+1.8VS
+3VS
R26
470_0402_5%
2 SUSP
G
Q35
2N7002_SOT23
2
G
2
1
1
1
S
R588
470_0402_5%
2 SYSON#
G
Q34
2N7002_SOT23
R587
470_0402_5%
R604
470_0402_5%
+1.8V
+1.5VS
+2.5VS
+0.9V
ACIN
3
2
G
<33,42> VLDT_EN
AO4430_SOIC8
D
D
D
D
C757
8
7
6
5
C446
C447
1U_0603_10V4Z
C756
1
2
3
4
1
S
S
S
G
D
D
D
D
Q5
R589
100K_0402_5%
U37
8
7
6
5
2
G
+1.8V
+1.2VALW
1
SYSON
SYSON
<28,44>
+1.2V_HT
+1.8V TO +1.8VS
SYSON#
<32,43> SYSON#
+1.2VALW TO +1.2V_HT
2N7002_SOT23-3
@
ACIN
<19,28,38,40> ACIN
+5VALW
2 SUSP
G
Q16
2N7002_SOT23
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Secret Data
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
E
37
of
47
DC231000500
VIN
VS
@ PR3
10K_0402_5%
2
1
2
PC6
0.1U_0603_25V7K
2
1
PR9
10K_0402_5%
1
2
PC5
1000P_0402_50V7K
RTCVREF
PBJ1
+RTCBATT
Vin Dectector
Min.
Typ
H-->L 16.976V 17.525V
L-->H 17.430V 17.901V
+RTCBATT
ML1220T13RE
45@
8
P
PU1A
LM358DT_SO8
PD3
GLZ4.3B_LL34-2
PR8
10K_0402_5%
PR6
22K_0402_5%
1
2
<19,28,37,40> ACIN
PR4
84.5K_0402_1%
PR160
10K_0402_5%
1
2 1
PR5
0_0402_5%
1
2
560P_0402_50V7K
PC4
2
1
12P_0402_50V8J
PC3
2
1
12P_0402_50V8J
PC2
2
1
560P_0402_50V7K
2
PC1
1
G
G
1
VIN
1
PR1
1M_0402_5%
1
2
VIN
PL1
SMB3025500YA_2P
1
2
ADPIN
PR7
20K_0402_1%
PJP1
SINGA_2DC-G756I200
Max.
17.728V
18.384V
VIN
PD4
LL4148_LL34-2
+1.5VSP
+1.5VS
JUMP_43X118
PJ3
+5VALWP
PJ4
+5VALW
+0.9VP
JUMP_43X118
VS
+0.9V
JUMP_43X79
PC8
0.1U_0603_25V7K
PJ5
+VSBP
PR14
22K_0402_1%
1
2
<33> 51ON#
PC7
0.22U_1206_25V7K
PR13
100K_0402_1%
+3VALW
PR11
68_1206_5%
2
N1
JUMP_43X118
PR10
PQ1
68_1206_5%
TP0610K-T1-E3_SOT23-3
PR12
200_0603_5%
CHGRTCP 1
2
PJ2
BATT+
PJ1
+3VALWP
PD5
LL4148_LL34-2
2
1
PJ6
+VSB
+1.8VP
JUMP_43X39
1
OUT
IN
GND
PC9
10U_0805_10V4Z
+1.2VALW
+1.1VSP
JUMP_43X118
+1.1VS
JUMP_43X118
PJ21
N2
+NB_COREP
1
PR15
200_0603_5%
PU2
G920AT24U_SOT89-3
3.3V
PJ8
PJ10
+NB_CORE
+2.5VSP
JUMP_43X118
+2.5VS
JUMP_43X118
PC10
1U_0805_25V4Z
PR17
560_0603_5%
1
2
+CHGRTC
PR16
560_0603_5%
1
2
+1.8V
JUMP_43X118
PJ7
+1.2VALWP
RTCVREF
Issued Date
Compal Secret Data
2008/06/11
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

D
38
of
47
ISL6237_B+
ISL6237_B+
3
2
1
25
PHASE2
PHASE1
16
LX5
23
LGATE2
LGATE1
18
DL5
PGND
22
OUT1
10
FB1
11
BYP
SKIP
29
1
2
3
3
2
1
LX3
DL3
FB3
@ PR25
10K_0402_1%
VL
30
OUT2
32
REFIN2
2VREF_ISL6237
1
PC31
LDOREFIN
@ PR27
2
EN_LDO
POK1
13
14
EN1
ILIM1
12
ILM1
PR31
365K_0402_1%
2
1
27
EN2
ILIM2
31
ILIM2
GND
21
TON
2
1
NC
5
PC33
1U_0603_10V6K
1
2
SPOK
PU3
ISL6237IRZ-T_QFN32_5X5
PR36
0_0402_5%
PC20
2200P_0402_50V7K
2
1
<41,44>
PR32
316K_0402_1%
+5VALWP Ipeak=6.87A ; Imax=4.81A

Choke DCRmax=26.5m ohm, DCRtyp=23m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 365K)/10=182.5mV
Ilimit=182.5mV/(18m*1.2) ~ 182.5mV/15m
=8.44A ~ 12.16A
Iocp=Ilimit+Delta I/2
=8.90A ~ 12.62A
Delta I=0.921A (Freq=400KHz)
2VREF_ISL6237 2
2
PR34
0_0402_5%
2
1
2VREF_ISL6237 1
PC34
0.047U_0603_16V7K
<8,41> MAINPWON
@ PR38
47K_0402_5%
1
2
PR37
0_0402_5%
2
check this part
VL
0_0402_5%
2
28
@ PR33
0_0402_5%
PR35
806K_0603_1%
0_0402_5%
1
POK2
2
1
PC32
0.22U_0603_25V7K
VL
REF
NC
PR30
200K_0402_5%
1
2
PD7
1SS355_SOD323-2
20
PR29
100K_0402_1%
1
2
+ PC30
330U_6.3V_M
FB5
PR28
1
PD6
GLZ5.1B_LL34-2
1
2
0.22U_0603_10V7K
+3.3VALWP Ipeak=4.26A ; Then set Imax=4.26A

Choke DCRmax=26.5m ohm, DCRtyp=23m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 316K)/10=158mV
Ilimit=158mV/(18m*1.2) ~ 158mV/15m
=7.31A~10.53A
VS
Iocp=Ilimit+Delta I/2
=7.76A~10.98A
Delta I=0.908A (Freq=300KHz)
PR24
63.4K_0402_1%
2
PC27
0.1U_0603_25V7K
PC26
0.1U_0603_25V7K
PQ5
AO4712_SO8
DH5
PR21 2.2_0603_5%
BST5A 2
1
PR26
10K_0402_1%
1
2
17
PR23
4.7_1206_5%
2
1
15
BOOT1
PL4
10UH_MSCDRI-104A-100M-E_4.6A_20%
2
1
PC29
680P_0402_50V7K
2
1
UGATE1
5
6
7
8
PC24
1U_0603_10V6K
1
2
19
BOOT2
LDO
UGATE2
24
PVCC
PC19
4.7U_1206_25V6K
2
1
PC23
4.7U_0805_6.3V6K
2
1
PC22
1U_0603_10V6K
1
2
26
VCC
VIN
TP
+5VALWP
DH3
PR20
2
1 BST3A
2.2_0603_5%
33
PQ3
AO4466_SO8
4
PC28
680P_0402_50V7K
2
6
VL
1
2
3
PQ4
AO4712_SO8
PR22
0_0402_5%
PC25
330U_6.3V_M
<BOM Structure>
8
7
6
5
1
PR19
4.7_1206_5%
2
1
PC21
0.1U_0603_25V7K
PQ2
AO4466_SO8
4
PL5
10UH_MSCDRI-104A-100M-E_4.6A_20%
1
2
+3VALWP
PC18
4.7U_1206_25V6K
2
1
8
7
6
5
5
6
7
8
PC17
2200P_0402_50V7K
2
1
@ PC203
680P_0402_50V7K
PC16
4.7U_1206_25V6K
2
1
B+
PR18
0_0805_5%
1
2
PC15
4.7U_1206_25V6K
2
1
PJ17
JUMP_43X118
2 2
1 1
@ PC35
0.047U_0402_16V7K
PQ6
TP0610K-T1-E3_SOT23-3
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Secret Data
2008/06/11
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet
D
39
of
47
B+
8
7
6
5
26
DH_CHG
PH
25
LX_CHG
PD8
2
ACDRV
ACDET
ACOP
AGND
LODRV
PGND
22
LEARN
21
CELLS
20
CELLS
VDAC
19
SE_CHG+
18
SE_CHG-
BAT
17
TP
29
VADJ
2
16
SRSET
15
PR56
10_0603_5%
1
2
IADAPT
PR58
340K_0402_1%
@ PR66
0_0402_5%
1
Charger ADJ
4.0V
3
2
1
2
<19,28,37,38>
@ PQ14
2N7002W-T/R7_SOT323-3
S
24751_VREF
2
PR70
210K_0402_0.1%
1
D
@ PQ18
2N7002W-T/R7_SOT323-3
2
G
@PC63
@PC63
1000P_0402_50V7K
CHGEN#
D
PQ19
2N7002W-T/R7_SOT323-3
2
G
<28> FSTCHG
PR72
100K_0402_5%
Calibrate#
L=0
4.2V
1.8755V
4.3V
2.8132V
4.35V
H=3.3V
Compal Secret Data
2008/06/11
Issued Date
2010/03/12
Deciphered Date
Title
Size
B
Date:
ACIN
D
2
G
VADJ
@ PR69
100K_0402_1%
2
S
PQ17
SSM3K7002F_SC59-3
3
2
3
1
2
G
ACGOOD#
1
D
65W/90W#
CP setting
PR244
100K_0402_5%
1
2
2
REGN
1
1
2
G
PQ20
2N7002W-T/R7_SOT323-3
1
@ PQ16
SI2301BDS-T1-E3_SOT23-3
PQ15
SSM3K7002F_SC59-3
2
G
@ PR59
100K_0402_1%
@ PR64
887K_0402_1%
2
1
2
PR75
100K_0402_1%
<28>
24751_VREF
2
PQ13_GATE
PR71
499K_0402_0.1%
2
1
@ PR61
0_0402_5%
1
<28>
<28> CALIBRATE#
PR74
100K_0402_1%
2
1
ACSET
PC61
0.1U_0402_16V7K
ACOFF
1
2
ADP_I
PR63
200K_0402_1%
2
1
24751_VREF
PR62
100K_0402_1%
2
1
2
2
PR73
64.9K_0402_1%
24751_VREF 1
2
24751_VREF
RTCVREF
PR67
105K_0402_1%
6
PC62
0.01U_0402_25V7K
IREF=0.7748*Icharge
@PC58
@PC58
0.01U_0402_25V7K
Icharge=(Vsrset/Vdac)*(0.1/PR46)
IREF <28> IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
<28> BATT_OVP
PU1B
LM358DT_SO8
7 0
PR65
10K_0402_1%
1
2
24751_VREF
PR60
499K_0402_1%
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A
PR68
340K_0402_1%
2
1
Vacset=3.3*(50K/(50K+64.9K))=1.436V
PC59
100P_0402_50V8J
65W adapter R=(100K*100K)/(100K+100K)=50K
PC60
0.01U_0402_25V7K
CP point=Iadapter*85%
CP Point Setting
PR57
100K_0402_1%
BQ24751ARHDR_QFN28_5X5
VS
SRSET
BATDRV
PR55
17.4K_0402_1%
2
1
14
Icharge Setting
For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
ICHG setting
/BATDRV
ACGOOD
VMB
Per cell=3.5V
13
ACGOOD#
BATT-OVP=0.1112*VMB
PC57
0.1U_0603_25V7K
12
ACSET
VADJ
SRP
SRN
1
2
11
PC54
0.1U_0603_25V7K
PQ13
SI2301BDS-T1-E3_SOT23-3
LI-3S :13.5V----BATT-OVP=1.5012V
VREF
PC53
0.1U_0603_25V7K
2
3
2
PC56
0.1U_0603_25V7K
10
<28>
+3VALWP
PQ13_GATE
BATT-OVP=0.1112*VMB
24751_VREF
LI-4S :18.0V----BATT-OVP=2.001V
PC55
1U_0603_10V6K
PR53
100K_0402_1%
1
2
Fsw : 300KHz
PC52
0.1U_0402_16V7K
1
2
1
24751_VREF
Cells selector
Input UVP : 17.26V
PC50
680P_0402_50V7K
ACOFF
PR52
54.9K_0402_1%
Input OVP : 22.3V
BATT+
PR48
4.7_1206_5%
DL_CHG
23
2
<28>
PQ11
AO4466_SO8
OVPSET
PC49
1U_0603_10V6K
OVPSET
PR51
340K_0402_1%
PC47
10U_1206_25V6M
24
1
PC51
0.47U_0603_16V7K
7
1
2
ACSET
4 Cell
PR50
0_0402_5%
1
2
@ PQ12
2N7002W-T/R7_SOT323-3
2
3S/4S#
G
REGN
CELLS
ACSET
VREF
@ PR49
@PR49
100K_0402_1%
PR47
54.9K_0402_1%
3 Cell
GND
CELLS
24751_VREF
LL4148_LL34-2
PC46
0.1U_0603_25V7K
REGN
Place close to back to back MOS
PR46
0.02_2512_1%
PL6
10UH_PCMB104T-100MS_6A_20%
1
2
PC48
10U_1206_25V6M
HIDRV
PC137
10U_1206_25V6M
2
1
ACN
ACP
2
3
4
5
ACN
ACP
2
/BATDRV
PQ10
AO4466_SO8
5
6
7
8
PR44
2.2_0603_5%
1
2
BTST
27
PC39
2200P_0402_25V7K
BTST
PQ9
AO4407A_SO8
PR274
0_0805_5%
1
PC43
0.1U_0603_25V7K
PC45
1U_0805_25V6K
1
2
PC38
4.7U_1206_25V6K
PVCC
5
6
7
8
28
CHGEN
PR41
100K_0402_1%
1
ACDET
PVCC
PU4
1
PC36
0.01U_0402_25V7K
CHG_B+
3
2
1
@PD11
@
PD11
1
RLZ24B_LL34
JUMP_43X118
CHGEN#
1
PC42
0.1U_0603_25V7K
PC37
4.7U_1206_25V6K
5
6
7
8
2
2
1
2
PC41
0.1U_0402_16V7K
1
2
PR45
340K_0402_1%
PC44
2.2U_0805_25V6K
PJ11
1
PC40
0.01U_0402_25V7K
4
2
2
1
PR43
3.3_1210_5%
1
2
3
PR39
0.015_2512_1%
1
2
3
PR42
100K_0402_1%
8
7
6
5
PR40
3.3_1210_5%
1
PQ8
AO4407A_SO8
3
2
1
PQ7
AO4407A_SO8
VIN
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet

E
40
of
47
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
VL
VL
VL
VMB
PR76
47K_0402_1%
PR77
47K_0402_1%
1
2
TM_REF1
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
LL4148_LL34-2
PR84
100K_0402_1%
PH2 near main Battery CONN :

BAT. thermal protection at 75 degree C
EC_SMDA
VL
EC_SMCA
PU5A
LM393DG_SO8
EC_SMB_DA1 <28>
PR82
100K_0402_1%
2
1
VL
EC_SMB_CK1 <28>
PJP3
PD9
BATT_TEMP <28>
2
2
PC68
1000P_0402_50V7K
PR85
1K_0402_1%
+3VALWP
PR81
13.3K_0402_1%
PC67
0.22U_0603_16V7K
<BOM Structure>
2
1
PR80
100_0402_1%
PR79
100_0402_1%
PR83
6.49K_0402_1%
2
1
PQ21
DTC115EUA_SC70-3
PR78
11.3K_0402_1%
1
2
PC66
0.01U_0402_25V7K
PC65
1000P_0402_50V7K
MAINPWON <8,39>
PC64
0.1U_0603_25V7K
PH1
100K_0603_1%_TSM1A104F4361RZ
BATT+
1
2
EC_SMCA
EC_SMDA
PL7
SMB3025500YA_2P
1
2
BATT_S1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
PJP2
SUYIN_250133MR007G115ZL
@ PR86
47K_0402_1%
@ PR87
47K_0402_1%
1
2
PQ22
TP0610K-T1-E3_SOT23-3
@ PR91
22.1K_0402_1%
PU5B
LM393DG_SO8
@ PC71
0.22U_0603_16V7K
@ PD10
LL4148_LL34-2
2
1
P
O
5
TM_REF1
@ PR89
6.49K_0402_1%
1
2
1
2
VL
+VSBP
1
PC70
0.1U_0603_25V7K
PR90
22K_0402_1%
1
2
VL
PR88
100K_0402_1%
B+
PC69
0.22U_1206_25V7K
@ PH2
100K_0603_1%_TH11-4H104FT
VL
SUYIN_200109MS020G209ZR
PQ23
2N7002W-T/R7_SOT323-3
2
G
2
4
PR93
0_0402_5%
2
<39,44> SPOK
PC72
0.1U_0402_16V7K
PR92
100K_0402_1%
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
A
Compal Secret Data
2008/06/11
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
D
41
of
47
PL16
FBMA-L11-322513-151LMA50T_1210
1
2
NB_51117_B+
PC206
10U_1206_25VAK
B+
1
+
@ PC300
68U_25V_M_R0.44
2
PR246
267K_0402_1%
1
2
3
2
1
BST_NBCOREP
V5FILT
VFB
15
14
13
LL
12
LX_NBCOREP
TRIP
11
V5DRV
10
+NB_COREP
DRVH
PL13
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1
2
PR250
4.7_1206_5%
5
6
7
8
VOUT
VBST
TON
DH_NBCOREP
PC209
0.1U_0603_25V7K
PR248
0_0603_5%
1
2BST_NBCOREP_11
2
+5VALW
D
D
D
D
PC208
0.1U_0402_16V7K
PR249
47K_0402_5%
TP
EN_PSV
PU12
1
<33,37> VLDT_EN
PR247
1.3K_0402_5%
1
2
PQ35
SIS412DN-T1-GE3_POWERPAK8-5
1
2
S
S
S
PC212
4.7U_0805_10V6K
PC211
680P_0603_50V8J
3
2
1
TPS51117RGYR_QFN14_3.5x3.5
4
PR252
12K_0402_1%
PGND
DL_NBCOREP
PC210
330U_D2E_6.3VM_R25M
PQ36
FDS6670AS_NL_SO8
PC214
1U_0603_10V6K
DRVL
@ PC213
@PC213
47P_0402_50V8J
1
2
+5VALW
PGOOD
6
PR251
300_0603_5%
1
2
GND
+
2
PR253
3.57K_0402_1%
1
2
PR255
30K_0402_1%
+3VS
PR254
10K_0402_1%
+3VS
2
PC215
0.1U_0402_16V7K
+5VALW
1
2
1.1V
FB
VIN
+1.1VSP
1
3
PR272
1.3K_0402_1%
APL5912-KAC-TRL_SO8
22U_0805_6.3V6M
EN
VOUT
PC229
2
1
PR270
10K_0402_5%
5
4
PC228
1U_0603_10V6K
VIN
VOUT
PC226
0.01U_0402_25V7K
2
1
VLDT_EN
POK
<33,37> VLDT_EN
PR273
12_0402_5%
1
2
1.017V
@PR261
@
PR261
10K_0402_1%
PC230
4.7U_0805_6.3V6K
PU15
POWER_SEL <13>
VCNTL
POWER_SEL
GND
PQ38
2N7002W-T/R7_SOT323-3
PR260
10K_0402_1%
2 1
2
G
2
PJ22
JUMP_43X79
@
PC227
1U_0402_6.3V6K
BOM control (R*C>1ms)
@ PR259
@PR259
10K_0402_5%
Ipeak=7A Imax=5.32A
Delta I=((19-1.1)*(1.1/19))/(1.8U*298K)=1.93A
Rtrip=12K
1/2DeltaI=0.96A
Rdson=9m~11.5m
Iocp=9.05A~14.30A
+1.2VALW
@ PR258
10K_0402_1%
2
G
S
VFB=0.75V
Rton=267K, Freq=298KHz
PR256
10K_0402_5%
PR257
10K_0402_1%
1
2
D
PQ37
2N7002W-T/R7_SOT323-3
<BOM Structure>
PR271
3.24K_0402_1%
2008/11/03
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
Date:
SCHEMATIC, MB A5481
Document Number
Rev
C
401743
Sheet
1
42
of
47
+1.8V
PJ12
JUMP_43X79
D
PU6
REFEN
NC
VOUT
NC
GND
PC74
1U_0402_6.3V6K
PU7
APL5508-25DC-TRL_SOT89-3
2
+3VS
3
2
@PC77
@
PC77
0.1U_0402_16V7K
IN
OUT
+2.5VSP
GND
PC78
1U_0402_6.3V6K
+0.9VP
1
PC79
4.7U_0805_6.3V6K
@ PR98
@PR98
150_1206_5%
2
PR96
1K_0402_1%
PC76
10U_0805_6.3V6M
PC75
0.1U_0402_16V7K
2
1
@ PQ24
2N7002W-T/R7_SOT323-3
2
G
@PR95
@
PR95
0_0402_5%
1
2
<32,37> SYSON#
RT9173DPSP_SO8
NC
GND
VCNTL
+3VALW
1
VIN
PR94
1K_0402_1%
PC73
4.7U_0805_6.3V6K
+1.8V
PJ14
JUMP_43X79
PC83
1U_0402_6.3V6K
5
4
VOUT
FB
VIN
PC84
4.7U_0805_6.3V6K
+1.5VSP
1
PC87
22U_0805_6.3V6M
GND
1
2
PU8
APL5915KAI-TRL_SO8
PC85
0.01U_0402_25V7K
PR102
1.54K_0402_1%
PC86
0.1U_0402_16V7K
EN
PR103
47K_0402_5%
VIN
VOUT
PR101
100K_0402_5%
1
2
<28,33,37> SUSP#
POK
VCNTL
+5VALW
PR104
1.74K_0402_1%
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
2008/06/11
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet

1
43
of
47
PL14
FBMA-L11-322513-151LMA50T_1210
1
2
1.8_51117_B+
PR107
0_0402_5%
1
2
1
5
6
7
8
D
D
D
D
2
1
DL_1.8V
PC92
4.7U_0805_10V6K
PC91
330U_6.3V_M
@ PC171
680P_0402_50V7K
PQ26
FDS6670AS_NL_SO8
4 G
@ PC93
47P_0402_50V8J
1
2
DRVL
+1.8VP
@ PR201
4.7_1206_5%
S
S
S
V5DRV
10
+5VALW
3
2
1
12
11
PL8
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1
2
PGOOD
LX_1.8V
LL
TRIP
VFB=0.75V
VFB
DH_1.8V
DRVH
13
PR108
PC90
0_0603_5%
0.1U_0603_25V7K
1
2BST_1.8V-1 1
2
PR110
16.2K_0402_1%
V5FILT
BST_1.8V
VBST
PGND
VOUT
TON
14
15
TP
EN_PSV
GND
PR109
300_0603_5%
1
2
PC94
1U_0603_10V6K
PU9
@PC89
@PC89
0.1U_0402_16V7K
+5VALW
VFB=0.75V
Vo=VFB*(1+PR111/PR112)=0.75*(1+14K/10K)=1.8V
Rton=267K=>Faw=297KHz
Cout ESR=15m ohm

Ipeak=11.96A, Imax=8.372A
Delta I=((19-1.8)*(1.8/19))/(L*Fsw)
((19-1.8)*(1.8/19))/(1.8u*297000)=3.048A
=>1/2DeltaI=1.524A
PR111
14K_0402_1%
1
2
C
PQ25
AO4466_SO8
3
2
1
<28,37> SYSON
PR200
0_0603_5%
1
2 4
PR106
267K_0402_1%
1
2
@ PC204
680P_0402_50V7K
5
6
7
8
B+
PC88
10U_1206_25VAK
PR112
10K_0402_1%
Rtrip=16.2K
Iocp=12.39A~20.69A
PL15
FBMA-L11-322513-151LMA50T_1210
1
2
2
3
2
1
+1.2VALWP
1
1 2
+
@ PC172
680P_0402_50V7K
PC98
330U_D2E_2.5VM
DL_1.2V
S
S
S
DRVL
+5VALW
PC99
4.7U_0805_10V6K
Compal Secret Data
PR120
10K_0402_1%
2008/06/11
Issued Date
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
5
6
7
8
V5DRV
10
@ PR203
4.7_1206_5%
5
6
7
8
11
PQ40
FDS6670AS_NL_SO8
D
D
D
D
TRIP
PL9
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1
2
3
2
1
LX_1.2V
PR118
12K_0402_1%
14
15
VBST
12
PGOOD
13
LL
VFB
PGND
VFB=0.75V
V5FILT
TP
DRVH
DH_1.2V
PR116
PC97
0_0603_5%
0.1U_0603_25V7K
1
2BST_1.2V-1 1
2
PR119
6.34K_0402_1%
1
2
1.2VP Ipeak=7.4A ; Imax=5.180A

Delta I=((19-1.2)*(1.2/19))/(L*Fsw)
((19-1.2)*(1.2/19))/(1.8u*298000)=2.10A
=>1/2DeltaI=1.05A
Rdson=11.5m/9m ohm
set Rtrip=12K
Icop_min=9.11A
Iocp_max=14.38A
VOUT
BST_1.2V
PC101
1U_0603_10V6K
A
TON
GND
@ PC100
47P_0402_50V8J
1
2
+5VALW
EN_PSV
@PC96
@PC96
0.1U_0402_16V7K
PR117
300_0603_5%
1
2
@ PC205
680P_0402_50V7K
B
PU10
VFB=0.75V
Vo=VFB*(1+PR119/PR120)=0.75*(1+6.04K/10K)=1.203V
Rton=267K=>Fsw=298KHz
PC95
10U_1206_25VAK
PR115
0_0402_5%
1
2
<39,41> SPOK
PQ39
AO4466_SO8
PR114
267K_0402_1%
1
2
B+
1.2_51117_B+
Rev
C
401743
Sheet
1
44
of
47
<8>
PGND2
24
23
COMP
FB
PHASE2
VDIFF
UGATE2
22
10
VSEN
BOOT2
21
41
GND PAD
ISEN1
PC175
10U_1206_25V6M
2
PR222
1_0402_5%
5
6
7
8
Rs
VSUM
PC191
10U_1206_25V6M
PC190
10U_1206_25V6M
3
2
1
Rn
+CPU_CORE
2
2
PR240
1_0402_5%
CPU_ISEN2
PR243
10K_0402_1%
1
PC198
0.22U_0603_16V7K
1
2
1
2
PR237
4.7_1206_5%
1
LG_CPU2
PC199
680P_0603_50V8J
3
2
1
3
2
1
PC197
1U_0402_6.3V6K
2
1
PQ34
AO4456_SO8
1
2
PR238
3.65K_0805_1%
1
2
PR239
10K_0402_1%
5
6
7
8
5
6
7
8
PQ33
AO4456_SO8
2
PR235
10_0603_5%
PL12
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
PHASE_CPU2
VSUM
PC196
0.01U_0402_50V7K
1
2
PH3
10K_0603_5%_TSM1A103J4302RE
Vdroop=Vn/Rdroop1*(Rdroop1+Rdroop2)
=Vn*(1+(Rdroop2/Rdroop1))
=Vn*(1+(PR231/PR230))
=Vn*G2
Close to Phase1 Choke PL11
PC195
0.22U_0402_6.3V6K
1
2
PC194
0.022U_0402_16V7K
1
2
PR234
0_0402_5%
PC193
0.22U_0402_6.3V6K
1
2
VCC_PRM
ISEN2
PR225
2.2_0603_5%
PR233
10_0402_5%
2
B+
Rn=(PR241+PH3)//(PR236)=5.875k, Rseuq=Rs/2=1.825K
Vdcrequ=Io*(DCR/2),
Vn=Vdcrequ*(Rn/(Rsequ+Rn))
=Io*(DCR/2)*(Rn/(Rsequ+Rn))
=Io*(DCR/2)*G1
CPU_ISEN2
CPU_ISEN1
UG_CPU2
2
@
@P
VCC_PRM
<8> CPU_VSS_SENSE
PC180
0.22U_0603_16V7K
1
2
CPU_B+
20
19
VDD
18
GND
17
VSUM
VIN
16
15
DFB
VO
14
12
13
DROOP
PU11
ISL6264CRZ-T_QFN40_6X6
PC182
4.7U_0603_6.3V6K
PC202
2200P_0402_50V7K
2
1
VID0
VW
+5VS
PR242
10K_0402_1%
LGATE2
25
1
2
PR220
3.65K_0805_1%
1
2
PR221
10K_0402_1%
26
1
2
PR219
4.7_1206_5%
PVCC
LG_CPU1
PR223 0_0402_5%
2
1
LGATE1
28
27
PC183
680P_0603_50V8J
PGND1
PQ31
AO4456_SO8
3
2
1
29
PQ30
AO4456_SO8
+CPU_CORE
CPU_ISEN1
`'&?'&`'&'& ~'&0~'&'&'&'&'&P|'& |'&'&@}'& {'&'&`z'&0z'&`{'&Py'& y'&'&`x'&'& w'&0w'&'&'&0x'&'&Pu'& u'&'&@v'&'&'&`s'&0s'&`t'&0t'& r'&'&`q'&0p'&'&pr'&?'&`?&?'&?'&P?
PQ32
& ?&?'&0?&?'&p?&`?&0?&`?&0?&?'&?'&`?&?'&p?& ?&?'&?'&0?&?'&p?& ?&?'&@?&?'&?'&P?&0?&`?&0?&?'&p?&`?&?'&@ '&?'&p?& ?&?'&0?&?'&p?& ?&?
SI7686DP-T1-E3_SO8
180P_0402_50V8J
CPU_ISEN2
1
2
PR230
PR231
1K_0402_1%
1.4K_0402_1%
4
+5VS
2
1
1
2
3
2
1
PHASE1
PR241
2.61K_0402_1%
1
2
PR232
10_0402_5%
1
2
5
2
30
PR236
11K_0402_1%
1
2
from output Bulk Cap
PC201
220U_25V_M
2
31
32
34
35
36
33
VID1
VID2
VID3
VID4
VID5
PSI_L
5
6
7
8
OCSET
+
2
PL11
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
3
2
1
SOFT
OFS
UGATE1
PC188
0.22U_0603_25V7K
+CPU_CORE
1
PR228
0_0402_5%
PHASE_CPU1
BOOT1
VR_ON
RBIAS
@PC186
@
PC186
0.068U_0402_16V7K
PC192
C192
1000P_0402_50V7K
PR229
10_0402_5%
2
1
PC176
0.22U_0603_25V7K
B+
UG_CPU1
@
@P
<8> CPU_VCC_SENSE
PQ29
SI7686DP-T1-E3_SO8
1
PR207
2.2_0603_5%
1
PR211
1
PR213
1
PR245
1
PR214
2
PR208
1
PR209
38
37
39
40
PGOOD
11
PC185
1000P_0402_50V7K
1
2
PC187
C187
1000P_0402_50V7K
1
2
PR227
255_0402_1%
1
2
SET
RTN
PC181
470P_0402_50V7K
1
2
PC184
220P_0402_50V8J
1
2
PR224
97.6K_0402_1%
1
2
PR226
1K_0402_1%
2
1
1
PR205
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
1
0_0402_5%
2
0_0402_5%
0_0402_5%
2
1
2
PR210
10K_0402_5%
PR215
150K_0402_1%
1
2
PR218
36.5K_0402_1%
1
2
PR217
4.02K_0402_1%
1
2
PC179
0.047U_0402_16V7K
1
2
PR216
6.81K_0402_1%
1
2
PC178
C178
1000P_0402_50V7K
1
2
PC177
1000P_0402_50V7K
1
2
C
CPU_B+
CPU_VID1 <8>
@
@P
PL10
FBMA-L18-453215-900LMA90T_1812
1
2
CPU_VID2 <8>
CPU_VID0 <8>
1
2
PR212
R212
10K_0402_5%
PR206
1
+3VS
@
@P
CPU_VID3 <8>
PC174
10U_1206_25V6M
1
2
<28> VGATE
VCC_PRM
CPU_VID4 <8>
PC200
2200P_0402_50V7K
2
1
PR204
10K_0402_5%
CPU_VID5 <8>
2
0_0402_5%
PSI_L
+3VS
<28>
VR_ON
@PD100
@
PD100
RB751V-40TE17_SOD323-2
2
1
CPU_ISEN1
VCC_PRM
VSUM
=>Vdroop=Vn*(1+(PR231/PR230))=Io*Rdroop
=>Io*(DCR/2)*G1*G2=Io*Rdroop
=>Rdroop=1.007m ohm
Iocp_min*Rdroop>Rocset*10uA
=>25A*1.007m ohm>Rocset*10uA
=>choose Rocset=2.74K
=>Iocp_min*1.007m ohm>2.74K*10u
=Iocp_min>27.209A
Iocp_max*Rdroop>Rocset*10.4uA
=>Icop_max>28.297A
Iocp=~27.209A~28.297A
2008/06/11
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
Deciphered Date
2010/03/12
Title
Date:
SCHEMATIC, MB A5481
Rev
C
401743
Sheet

1
45
of
47
Version change list (P.I.R. List)

Item
D
HW required to adjust from 1.14V to

1.12V
Reason for change

HW required to adjust from 1.14V to
1.12V
Modify List
Page 1 of 1
for PWR
Rev.
PG#
Date
Phase
0.1
42
Change PR271 from SD034300180 (S RES 1/16W 3K +-1%

0402) to SD034324180 (S RES 1/16W 3.24K 0402 1%)
09, 05/07
to PVT
Power sequense adjust.
HW required to adjust power sequense.
0.1
42
Add PC208 SE076104K80 (S CER CAP .1U 16V K X7R 0402) 09, 05/07
to PVT
Power sequense adjust.
HW required to adjust power sequense.
0.1
42
Change PR247 from SD028000080 (S RES 1/16W 0 +-5%

0402) to SD028130180 (S RES 1/16W 1.3K 0402 5%)
09, 05/07
to PVT
NB_COREP working frequency has

issue.
Because NB_COREP working frequency will be gitter

while system at heavy loading. Change to larger ESR
Cap will be solve.
0.1
42
Change PC210 from SGA19331D00 (S POLY C 330U 2.5V M

D2 TPE LESR15M H1.8) to SGA00002B00 (S POLY C 330U
6.3V M D2E ESR25M TPE H1.8)
09, 05/07
to PVT
BOM error
BOM error
0.1
42
Add PR270 SD28100280(S RES 1/16W 10K 0402 5%)
09, 05/07
to PVT
BOM error
BOM error
0.1
42
Change PR103 from SD028470280(S RES 1/16W 47K 0402 5%)

09, 05/07
to SD028100280(S RES 1/16W 10K 0402
5%)
to PVT
Fixed Issue
8
9
10
11
12
13
14
15
16
17
18
A
Issued Date
Compal Secret Data
2008/06/11
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Date:
Rev
C
401743
Sheet
1
46
of
46
Version change list (P.I.R. List) for HW

Item
D
Reason for change
Date
Item
4/9
26
P.18
4/9
27
P.16
4/9
28
PWR update circuit
BOM change
BOM change
BOM change
R30, R39 reserve
P.24
4/9
29
BOM change
Add C30
P.38
4/9
30
BOM change
Add R634, R639
P.28
4/9
31
BOM change
C383 Reserve
P.24
4/9
32
Pop R419
P.20
4/10
33
PG#
Modify List
R118 reserve
Change R178, R179 to 90.9/158 ohm
PWR update circuit
10
For Panel flash issue
R1,D2 Reserve, pop R763
P.24
5/18
11
For Panel flash issue
Add R414 and non-pop
P.24
5/18
12
Lid_SW intial issue
Add R19
P.28
5/18
13
HPET timer issue
Change C288,C290 to 33P
P.16
5/18
14
BOM change
change C276,C279 10P to 27P
P.19
5/19
Reason for change
Modify List
Rev.
PG#
D
5/15
15
16
17
18
19
20
B
21
22
23
24
25
2005/03/08
Issued Date
hexainf@hotmail.com
GRATIS - FOR FREE
5
Compal Secret Data
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
Custom
Date:
Rev
C
401743
Sheet
1
47
of
47

Acer Aspire 5517 5532 Compal La 5481p

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NCWG0/H0 Schematics Document

Compal Electronics, Inc.

Compal Secret Data

Wednesday, June 24, 2009

AMD S1g1 CPU

AMP & Audio Jack

Power On/Off CKT / LID switch / Power OK CKT

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Electronics, Inc.

Compal Secret Data

Wednesday, June 24, 2009

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

Board ID / SKU ID Table for AD channel

External PCI Devices

BTO Option Table

SB600 SM Bus 1 address

SB600 SM Bus 2 address

Compal Electronics, Inc.

Compal Secret Data

Wednesday, June 24, 2009

Mini PCI Socket

Compal Electronics, Inc.

Compal Secret Data

Wednesday, June 24, 2009

Compal Electronics, Inc.

Compal Secret Data

Wednesday, June 24, 2009

Reserve when PVT

Near CPU Socket

Compal Secret Data

Compal Electronics, Inc.

Wednesday, June 24, 2009

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR

Compal Secret Data

Compal Electronics, Inc.

Wednesday, June 24, 2009

SMBus Address: 1001110X (b)

VID1: For compatibility

ROUTE AS 80 Ohm DIFFERENTIAL PAIR

NOTE: HDT TERMINATION IS REQUIRED

Compal Secret Data

Compal Electronics, Inc.

AMD: suggest DBREQ need pull high

Wednesday, June 24, 2009

Near CPU Socket

Under CPU Socket