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DECLARATION

We declare that this report entitled Design of Voltage Divider BJT Transistor Network is the result of our own laboratory session except as cited in the references. The report has not been accepted for any subject and is not concurrently submitted in candidature of any other subject

Group Members: 1. 2. 3. 4.

Matrix No. :

Signature:

Date:

TABLE OF CONTENTS

CHAPTER

TITTLE

PAGE

DECLARATION TABLE OF CONTENTS

1 2

INTRODUCTION 1.1 1.2 Objectives Equipment

4 4 4

LITERATURE REVIEW

METHODOLOGY 3.1 Flowchart

9 10

4.1 4.2

Discussion and Suggestion Conclusion

12 12

REFERENCES Appendices 13

CHAPTER 1

INTRODUCTION

1.1

OBJECTIVES

By finishing this laboratory exercise, students are expected to gain the following skills:

1. Ability to design a stable voltage-divider bias BJT transistor configuration.

1.2

EQUIPMENT

1. Digital Multimeter 2. Resistor 3. Transistor: 2N3904 4. DC Power Supply 5. Breadboard 6. Wires

CHAPTER 2

LITERATURE REVIEW

A BJT is comprised basically of three doped semiconductor regions forming two p-n junctions connected back to back. The three semiconductor regions are identified as: the Base (B), the collector (C), and the emitter (E). The labelling codes "npn" and "pnp" identify the doping the three semiconductor regions that make up a BJT: npn implies n-type doping of the collector and emitter and p-type doping of the base; pnp implies the inverse. While the collector and emitter are always of the same doping type, the doping concentrations may be different in those two regions. The operation of a BJT depends on both electron and hole conduction. Depending on the bias of each of the two p-n junctions, the BJT operates in one of four distinct regions as shown below.

In many applications, the BJT is used in a common-emitter configuration. The EbersMoll model, used in PSpice, is used by SPICE to model common-emitter BJT circuits to model the transistor circuit in all operating regions. In linear applications, BJT circuits must be designed so that the transistor operates in the forward-active region. In order to insure operation in the forward-active region, the transistor is biased at a quiescent operating point, commonly called the Q-point, based on the DC conditions of the BJT. The quiescent point is determined by the transistor input and output characteristics and the applied currents and voltages. The quiescent point is defined by the BJT DC quantities VBE, IB, VCE, and IC . These points may be determined through the use of load-line analysis and design methods. The biasing configurations that are to be investigated are the fixed-bias and self-bias circuits shown in Figures below, respectively.

For the Q-point in the forward active region, VBE = 0.7V. In order design and analyze a biased circuit, we require the BJT F for finding the base current from the collector current (or viseversa). For the Fixed-Bias circuit shown in Figure above, the base-emitter KVL analysis yields

and the collector-emitter KVL analysis yields

Use the relationship and Q-points.

to solve for appropriate

and

values given

The Self-Bias circuit in Figure above requires conversion of the subcircuit connected to the base of the BJT to be converted to the Thevenin equivalent circuit for ease of design and analysis. Below shows the transformation of the self-bias circuit using Thevenin equivalents.

So the Base-Emitter KVL equation for the Thevenin Equivalent circuit is:

Note also that This equation may simplify design when analyzing the Base-Emitter KVL loop.

CHAPTER 3

METHODOLOGY

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Figure above shows the connection of voltage-divider bias circuit for BJT. We construct the circuit above using 2N3904 transistor in a simulation such Multisim or Proteus. This simulation will determine the value of VRE, VR2, VTH, VB, and VE after we have calculated the value af all resistor manually. We will employ the design rule that =100 and = 0.1 .

1. For the given specification, the required value of RC for the voltagedivider configuration in the Figure was calculated. 2. Using = 0.1 = 1.5V; the value of RE is calculated as required. > 10 will result in = = + . The value of

3. Assuming

R1 and R2 were calculated manually as well. 4. Using any suitable simulation and theory, Table 1 was completed.

3.1

FLOWCHART

Pre Lab session.

Acknowle dge the formulae of voltage divider

Calculate the value of all resistor.

The calculated value of resistor was recorded.

Use multisim to simulate the experiment

The values of the result were recorded.

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Construct circuit for voltage-divider bias of transistor 2N3904

Record the required value measured and fill in Table 3

Calculate the ratio as indication of the relative stability of the design.

Calculate and complete Table 4.

Come with a discussion, precaution and suggestion

Conclude the experiment

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CHAPTER 4

4.1

Discussion and Suggestion:

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4.2

Conclusion:

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REFERENCES

http://en.wikipedia.org/wiki/Bipolar_transistor_biasing http://www.wisc-online.com/Objects/ViewObject.aspx?ID=SSE1302

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Appendices

From multisim software