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  • Shree Chanakya Education Society's Indira College of Engineering and Management Lesson Plan for VLSI Design and Technology

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    Harold Wilson
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    This document contains a lesson plan for the course "VLSI Design and Technology" with the following details: - It lists 44 class meetings from July to September with the syllabus topics to be covered on each date, ranging from MOSFET amplifiers to VLSI testing and design validation. - The course is divided into 6 units covering topics such as CMOS logic design, VHDL, programmable logic devices, faults and testing techniques, clocking and power distribution challenges, and I/O architectures. - The teaching scheme allocates 4 hours of lectures and 2 hours of practicals per week, with exams accounting for 100 marks for theory and 50 marks for practicals.

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    This document contains a lesson plan for the course "VLSI Design and Technology" with the following details: - It lists 44 class meetings from July to September with the syllabus topics to be covered on each date, ranging from MOSFET amplifiers to VLSI testing and design validation. - The course is divided into 6 units covering topics such as CMOS logic design, VHDL, programmable logic devices, faults and testing techniques, clocking and power distribution challenges, and I/O architectures. - The teaching scheme allocates 4 hours of lectures and 2 hours of practicals per week, with exams accounting for 100 marks for theory and 50 marks for practicals.

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    Attribution Non-Commercial (BY-NC)
    Descărcați ca PDF, TXT sau citiți online pe Scribd
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    31 vizualizări2 pagini

    Shree Chanakya Education Society's Indira College of Engineering and Management Lesson Plan for VLSI Design and Technology

    Încărcat de

    Harold Wilson
    This document contains a lesson plan for the course "VLSI Design and Technology" with the following details: - It lists 44 class meetings from July to September with the syllabus topics to be covered on each date, ranging from MOSFET amplifiers to VLSI testing and design validation. - The course is divided into 6 units covering topics such as CMOS logic design, VHDL, programmable logic devices, faults and testing techniques, clocking and power distribution challenges, and I/O architectures. - The teaching scheme allocates 4 hours of lectures and 2 hours of practicals per week, with exams accounting for 100 marks for theory and 50 marks for practicals.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    din 2

    SHREE CHANAKYA EDUCATION SOCIETYS

    INDIRA COLLEGE OF ENGINEERING AND MANAGEMENT


    Approved By AICTE New Delhi, DTE (MS) and Affiliated to Pune University ( Id-No. PU/PN/Engg/282/2007)

    Department of Electronics &Telecommunication Engineering

    Lesson Plan
    Teaching Scheme Lecturers/week: 4 hrs Practicals/week: 2 hrs VLSI DESIGN AND TECHNOLOGY (404182) Examination Scheme Paper: 100 Marks Practical: 50 Marks

    Sr.No

    Planned Date

    Syllabus to Covered

    UNIT I
    1. 102/07/2012 . 2. 04/07/2012 3. 05/07/2012 4. 09/07/2012 5. 12/07/2012 6. 13/07/2012 7. 16/07/2012 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 17/07/2012 18/07/2012 19/07/2012 23/07/2012 24/07/2012 25/07/2012 26/07/2012 30/07/2012 31/07/2012 01/08/12 06/08/2012 07/08/2012 08/08/2012 09/08/2012 13/08/2012 14/08/2012 16/08/2012 21/08/2012 22/08/2012 23/08/2012
    Enhancement MOSFET equivalent circuit parasitics, as resistor, diode. Active load, current source and push pull inverter amplifiers. Current source and sink. Common source, drain and gate amplifiers. Cascode amplifier. Differential amplifier. CMOS op-amp.

    Unit II
    CMOS Inverter, voltage transfer curve, body effect, hot electron effect, velocity saturation Static and dynamic dissipations. Power delay product. Noise margin. Combinational logic design, W/L calculations. Transmission gate, design using TGs. Parameter, layout, Design Rule Check. Technology scaling.

    Unit III
    VHDL design units, modeling styles synthesizable and non synthesizable test benches design flow, functions, procedures, attributes, test benches, configurations Finite State Machines (FSM), packages. Synchronous and asynchronous machines state diagrams and VHDL codes for FSMs.

    Unit IV
    Need of PLDs Comparison with ASIC general purpose processor, DSP processor, microcontroller, memories etc. Features, specifications, detail architectures,

    28. 27/08/2012 29. 28/08/2012 30. 29/08/12 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 30/08/2012 03/09/2012 04/09/2012 05/09/2012 09/09/2012 10/09/2012 11/09/2012 12/09/2012 13/09/2012 17/09/2012 18/09/2012 20/09/2012 24/09/2012

    limitations of Complex Programmable Logic Device (CPLD) Field Programmable Logic Devices (FPGA). application areas

    Unit V
    Types of fault, stuck open, short, stuck at 1, 0 faults Fault coverage Need of Design for Testability (DFT). Controllability, predictability, testability Built In Self Test (BIST) Partial and full scan check. Need of boundary scan check JTAG, Test Access Port (TAP) controller.

    Unit VI
    Clock skew, Clock distribution techniques clock jitter Supply and ground bounce, power distribution techniques. Power optimization. Interconnect routing techniques wire parasitics. Design validation. Off chip connections, I/O architectures I/O architectures. Signal integrity Issues, EMI immune chip design

    44. 25/09/2012

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