VNH3ASP30-E

AUTOMOTIVE FULLY INTEGRATED H-BRIDGE MOTOR DRIVER

TARGET SPECIFICATION

Table 1. General Features

TYPE VNH3ASP30-E RDS(on) 42 m max (per leg) IOUT 30 A Vccmax 41 V

Figure 1. Package

I I I

OUTPUT CURRENT: 30A

5V LOGIC LEVEL COMPATIBLE INPUTS UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN I OVERVOLTAGE CLAMP I THERMAL SHUT DOWN I CROSS-CONDUCTION PROTECTION I LINEAR CURRENT LIMITER I VERY LOW STAND-BY POWER CONSUMPTION I PWM OPERATION UP TO 20 KHz I PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF VCC I CURRENT SENSE OUTPUT PROPORTIONAL TO MOTOR CURRENT I IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE DESCRIPTION The VNH3ASP30-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic High-Side drivers and two Low-Side switches. The High-Side driver switch is designed using STMicroelectronics well known and proven proprietary VIPower M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/ protection circuitry.

MultiPowerSO-30

The Low-Side switches are vertical MOSFETs manufactured using STMicroelectronics proprietary EHD (STripFET) process. The three dice are assembled in MultiPowerSO-30 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals IN A and INB can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAG A/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in the truth table on page 7. The CS pin allows to monitor the motor current by delivering a current proportional to its value. The PWM, up to 20KHz, lets us to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state.

Table 2. Order Codes

Package Tube
VNH3ASP30-E

Tape and Reel

VNH3ASP30TR-E

MultiPowerSO-30

Rev. 1 September 2004 1/18

VNH3ASP30-E
Figure 2. Block Diagram
VCC

OVERTEMPERATURE A

OV + UV

OVERTEMPERATURE B

CLAMP HSA

CLAMP HSB

HSA

DRIVER HSA

LOGIC

DRIVER H SB

HSB

CURRENT LIMITATION A OUTA CLAMP LSA

DRIVER LSA

CURRENT LIMITATION B
1/K

1/K CLAMP LSB

DRIVER LS B

OUTB

LSA

LSB

GNDA

DIAGA/ENA INA

CS

PWM INB DIAGB/ENB

GNDB

Figure 3. Configuration Diagram (Top View)

OUTA Nc VCC Nc INA ENA/DIAGA Nc PWM CS ENB/DIAGB INB Nc VCC Nc OUTB

30

OUTA Nc GNDA GNDA GNDA OUTA Nc VCC Nc OUTB

OUTA
Heat Slug3

VCC Heat Slug1

OUTB
Heat Slug2

15

16

GNDB GNDB GNDB Nc OUTB

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VNH3ASP30-E
Table 3. Pin Definitions And Functions
Pin No 1, 25, 30 2,4,7,12,14,17, 22, 24,29 3, 13, 23 6 5 8 9 11 10 15, 16, 21 26, 27, 28 18, 19, 20 Symbol OUTA, Heat Slug2 NC VCC, Heat Slug1 ENA/DIAGA INA PWM CS INB ENB/DIAGB OUTB, Heat Slug3 GNDA GNDB Function Source of High-Side Switch A / Drain of Low-Side Switch A Not connected Drain of High-Side Switches and Power Supply Voltage Status of High-Side and Low-Side Switches A; Open Drain Output Clockwise Input PWM Input Output of Current sense Counter Clockwise Input Status of High-Side and Low-Side Switches B; Open Drain Output Source of High-Side Switch B / Drain of Low-Side Switch B Source of Low-Side Switch A (*) Source of Low-Side Switch B (*)

Note: (*) GNDA and GNDB must be externally connected together.

Table 4. Pin Functions Description

Name VCC GNDA GNDB OUTA OUTB INA INB PWM ENA/DIAGA ENB/DIAGB CS Description Battery connection. Power grounds, must always be externally connected together. Power connections to the motor. Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise). Voltage controlled input pin with hysteresis, CMOS compatible.Gates of Low-Side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition). Analog current sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor.

Table 5. Block Descriptions (see Block Diagram)

Name LOGIC CONTROL OVERVOLTAGE + UNDERVOLTAGE HIGH SIDE AND LOW SIDE CLAMP VOLTAGE HIGH SIDE AND LOW SIDE DRIVER LINEAR CURRENT LIMITER OVERTEMPERATURE PROTECTION FAULT DETECTION Description Allows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table. Shut-down the device outside the range [5.5V..16V] for the battery voltage. Protect the High Side and the Low Side switches from the high voltage on the battery line in all configuration for the motor. Drive the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge. Limits the motor current, by reducing the High Side Switch gate-source voltage when short-circuit to ground occurs. In case of short-circuit with the increase of the junctions temperature, shuts-down the concerned High Side to prevent its degradation and to protect the die. Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin.

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Table 6. Absolute Maximum Rating
Symbol VCC Imax IR IIN IEN Ipw VCS Parameter Supply Voltage Maximum Output Current (continuous) Reverse Output Current (continuous) Input Current (INA and INB pins) Enable Input Current (DIAGA/ENA and DIAGB/ENB pins) PWM Input Current Current Sense Maximum Voltage Electrostatic Discharge (R=1.5k, C=100pF) - CS pin - logic pins - output pins: OUTA, OUTB, VCC Junction Operating Temperature Case Operating Temperature Storage Temperature Value + 41 30 -30 +/- 10 +/- 10 +/- 10 -3/+15 2 4 5 Internally Limited -40 to 150 -55 to 150 Unit V A A mA mA mA V kV kV kV C C C

VESD

Tj Tc TSTG

Figure 4. Current and Voltage Conventions

IS VCC IINA IINB IENA IENB INA INB DIAGA/ENA DIAGB/ENB PWM Ipw GND VINA VINB VENA VENB Vpw IGND GNDA GNDB VCC OUTA OUTB CS ISENSE VOUTB VSENSE IOUTA IOUTB VOUTA

Table 7. Thermal Data

Symbol Rthj-case Rthj-amb (*) Parameter Thermal resistance junction-case (Per leg) Thermal resistance junction-ambient (MAX) (MAX) Value 1.0 20 Unit C/W C/W

Note: (*) When mounted using the recommended pad size on FR-4 board (see MultiPowerSO-30 Mechanical data).

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ELECTRICAL CHARACTERISTICS (VCC=9V up to 16V; -40C<Tj<150C; unless otherwise specified) Table 8. Power
Symbol VCC Parameter Operating supply voltage Test Conditions Off state: INA=INB=PWM=0; Tj=25 C; Min 5.5 Typ Max 16 Unit V

VCC=13V
IS Supply Current INA=INB=PWM=0 On state: INA or INB=5V, no PWM INA or INB=5V; PWM=20kHz IOUT=12A; Tj=25C IOUT=12A; Tj= - 40 to 150C IOUT=12A; Tj=25C IOUT=12A; Tj= - 40 to 150C If=12A Tj=25C; VOUTX=ENX=0V; IL(off) High Side Off State Output Current (per channel) Dynamic Cross-conduction Current

12

30 TBD 10 TBD 30 60 12 24

A A mA mA m m m m V A A A

RONHS RONLS Vf

Static High-Side resistance Static Low-Side resistance High Side Free-wheeling Diode Forward Voltage

0.8

1.1 3 5

VCC=13V
Tj=125C; VOUTX=ENX=0V;

VCC=13V
IRM IOUT=12A (see fig. 9) 1.7

Table 9. Logic Inputs (INA, INB, ENA, ENB)

Symbol VIL VIH VIHYST VICL IINL IINH VDIAG Parameter Input Low Level Voltage Input High Level Voltage Input Hysteresis Voltage Input Clamp Voltage Input Current Input Current Enable Output Low Level Voltage Test Conditions Normal operation (DIAGX/ENX pin acts as an input pin) Normal operation (DIAGX/ENX pin acts as an input pin) Normal operation (DIAGX/ENX pin acts as an input pin) IIN=1mA IIN=-1mA VIN=1.25 V VIN=3.25 V Fault operation (DIAGX/ENX pin acts as an output pin); IEN=1mA Min Typ Max 1.25 3.25 0.5 5.5 -1.0 1 6.3 -0.7 7.5 -0.3 10 0.4 Unit V V V V V A A V

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ELECTRICAL CHARACTERISTICS (continued) Table 10. PWM
Symbol Vpwl Ipwl Vpwh Ipwh Vpwhhyst Vpwcl CINPWM PWM PWM PWM PWM PWM Parameter Low Level Voltage Pin Current High Level Voltage Pin Current Hysteresis Voltage Test Conditions Vpw=1.25V Vpw=3.25V Ipw = 1 mA Ipw = -1 mA VIN =2.5V Min 1 3.25 10 0.5 VCC+0.3 VCC+0.7 VCC+1.0 -6.0 -4.5 -3.0 25 Typ Max 1.25 Unit V A V A V V V pF

PWM Clamp Voltage PWM Pin Input Capacitance

Table 11. Switching (VCC=13V, RLOAD=1)

Symbol f td(on) td(off) tr tf Parameter PWM Frequency Turn-on Delay Time Turn-off Delay Time Rise Time Fall Time Delay Time During Change of Operating Mode High Side Free Wheeling Diode Reverse Recovery Time Test Conditions Input rise time < 1s (see fig. 8) Input rise time < 1s (see fig. 8) (see fig. 7) (see fig. 7) (see fig. 6) (see fig. 9) 300 Min 0 Typ Max 20 250 250 2 2 1800 Unit kHz s s s s s ns

1 1
600 110

tDEL
trr

Table 12. Protection And Diagnostic

Symbol VUSD VOV ILIM VCLP TTSD TTR THYST Parameter Undervoltage Shut-down Undervoltage Reset Overvoltage Shut-down High-Side Current Limitation Total Clamp Voltage (VCC to GND) Thermal Shut-down Temperature Thermal Reset Temperature Thermal Hysteresis Test Conditions Min Typ 4.7 19 45 48 175 Max 5.5 22 60 54 200 Unit V V V A V C C C

16 30 IOUT=12A VIN = 3.25 V 43 150 135 7

15

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ELECTRICAL CHARACTERISTICS (continued) Table 13. Current Sense (9V<VCC<16V)
Symbol K1 K2 dK1 / K1 (*) dK2 / K2 (*) ISENSEO Parameter IOUT /ISENSE IOUT /ISENSE Analog sense current drift Analog sense current drift Analog Sense Leakage Current Test Conditions IOUT=30A; RSENSE=700 Tj= - 40 to 150C IOUT=8A; RSENSE=700 Tj= - 40 to 150C IOUT=30A; RSENSE=700 Tj= - 40 to 150C IOUT >8A; RSENSE=700 Tj= - 40 to 150C IOUT=0A; VSENSE=0V; Tj= - 40 to 150C Min 4000 3750 -8 -10 0 Typ 4700 4700 Max 5400 5650 +8 +10 70 % % A Unit

Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40C to 150C and 9V<VCC<16V) with respect to its value measured at T j=25C, VCC=13V.

WAVEFORMS AND TRUTH TABLE Table 14. Truth Table In Normal Operating Conditions
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. PWM pin usage: In all cases, a 0 on the PWM pin will turn-off both LSA and LSB switches. When PWM rises back to 1, LSA or LSB turn on again depending on the input pin state. OUTB H L H L CS High Imp. ISENSE=I OUT/K
ISENSE=I OUT/K

INA 1 1 0 0

INB 1 0 1 0

DIAGA/ENA 1 1 1 1

DIAGB/ENB 1 1 1 1

OUTA H H L L

Operating mode Brake to VCC Clockwise (CW) Counterclockwise

(CCW)

High Imp.

Brake to GND

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VNH3ASP30-E
Figure 5. Typical Application Circuit For Dc To 20KHz PWM Operation
VCC
Reg 5V + 5V 3.3K 1K DIAGA/ENA 1K

VCC

HSA
OUTA

HSB
OUTB

C
1K

PWM

INA

LSA
10K CS

LSB

33nF

1.5K

S 100K G D b) N MOSFET

In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides (for example if a short to ground occurs as it could be the case described in line 1 and 2 in the table below); - short to battery condition on the output (saturation detection on the Low-Side Power MOSFET). Possible origins of fault conditions may be:

OUTA is shorted to ground ---> overtemperature detection on high side A. OUTA is shorted to VCC ---> Low-Side Power MOSFET saturation detection. When a fault condition is detected, the user can know which power element is in fault by monitoring the IN A, INB, DIAGA/ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the respective output (OUTX) again, the input signal must rise from low to high level.

Table 15. Truth Table In Fault Conditions (detected on OUTA)

INA 1 1 0 0 X X X INB 1 0 1 0 X 1 0 DIAGA/ENA 0 0 0 0 0 0 0 DIAGB/ENB 1 1 1 1 0 1 1 OUTA OPEN OPEN OPEN OPEN OPEN OPEN OPEN OUTB H L H L OPEN H L CS High Imp. High Imp. IOUTB/K High Imp. High Imp. IOUTB/K High Imp.

Fault Information

Protection Action

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Table 16. Electrical Transient Requirements
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E Test Level I -25V +25V -25V +25V -4V +26.5V Test Level II -50V +50V -50V +50V -5V +46.5V Test Level III -75V +75V -100V +75V -6V +66.5V Test Level IV -100V +100V -150V +100V -7V +86.5V Test Levels Result III C C C C C E Test Levels Delays and Impedance 2ms, 10 0.2ms, 10 0.1s, 50 0.1s, 50 100ms, 0.01 400ms, 2 Test Levels Result IV C C C C C E

Test Levels Result I C C C C C C

Test Levels Result II C C C C C E

Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

Reverse Battery Protection Three possible solutions can be thought of: a) a Schottky diode D connected to V CC pin b) a N-channel MOSFET connected to the GND pin (see Typical Application Circuit on fig. 5) c) a P-channel MOSFET connected to the V CC pin.

The device sustains no more than -30A in reverse battery conditions because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH3ASP30 will be pulled down to the VCC line (approximately -1.5V). Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through C I/Os, series resistor is: V V IOs CC R = --------------------------------I Rmax

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VNH3ASP30-E
Figure 6. Definition Of The Delay Times Measurement
VINA,

t
VINB

t
PWM

t
ILOAD tDEL

tDEL

Figure 7. Definition Of The Low Side Switching Times

PWM

t
VOUTA, B 90% 80%

tf

20%

10%

tr

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VNH3ASP30-E
Figure 8. Definition Of The High Side Switching Times

VINA,

tD(on)

tD(off)

t
VOUTA

90%

10%

Figure 9. Definition Of Dynamic Cross Conduction Current During A PWM Operation

IN A=1, IN B=0
PWM

t
IMOTOR

t
VOUTB

t
ICC IRM

t
trr

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VNH3ASP30-E
Figure 10. Waveforms in full bridge operation

DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS (*)

NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB

tDEL (*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE

tDEL

NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS

CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND

INA INB ILIM IOUTA->OUTB TTSD TTR

Tj
DIAGA/ENA DIAGB/ENB CS normal operation

Tj > TTR

OUTA shorted to ground

normal operation

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VNH3ASP30-E
Figure 11. Waveforms In Full Bridge Operation (continued)

OUTA shorted to VCC and undervoltage shutdown

INA INB OUTA OUTB IOUTA->OUTB DIAGB/ENB DIAGA/ENA CS V<nominal

undefined undefined

normal operation

OUTA shorted to VCC

normal operation

undervoltage shutdown

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VNH3ASP30-E
Figure 12. Half-bridge Configuration The VNH3ASP30-E can be used as a high power half-bridge driver achieving an ON resistance per leg of 22.5m . Suggested configuration is the following:

VCC

INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB

INA INB DIAGA/ENA DIAGB/ENB PWM

OUTA

OUTB

GNDA

GNDB

GNDA

GNDB

Figure 13. Multi-motors Configuration The VNH3ASP30-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAG X/EN X pins allow to put unused half-bridges in high impedance. Suggested configuration is the following:

VCC

INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB

INA INB DIAGA/ENA DIAGB/ENB PWM

M2

OUTA

OUTB

GNDA

GNDB

GNDA

GNDB

M1

M3

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PACKAGE MECHANICAL Table 17. MultiPowerSO-30 Mechanical Data
Symbol A A2 A3 B C D E E1 e F1 F2 F3 L N S 0deg 5.55 4.6 9.6 0.8 1.85 0 0.42 0.23 17.1 18.85 15.9 16 1 6.05 5.1 10.1 1.15 10deg 7deg 17.2 millimeters Min. Typ Max. 2.35 2.25 0.1 0.58 0.32 17.3 19.15 16.1

Figure 14. MultiPowerSO-30 Package Dimensions

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Figure 15. MultiPowerSO-30 Suggested Pad Layout

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REVISION HISTORY
Date Revision Sep. 2004 1 - First issue. Description of Changes

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

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