if ( J = '0' and K = '0' ) then

JK FLIPFLOP

NULL ;

library IEEE;

elsif ( J = '0' and K = '1' ) then

use IEEE.STD_LOGIC_1164.ALL;

qtemp <= '0' ;

qbartemp <= '1' ;

-- Uncomment the following library declaration if using

elsif ( J = '1' and K = '1' ) then

-- arithmetic functions with Signed or Unsigned values

qtemp <= '1' ;

--use IEEE.NUMERIC_STD.ALL;

qbartemp <= '0' ;

else

-- Uncomment the following library declaration if

instantiating

qtemp <= not qtemp ;

-- any Xilinx primitives in this code.

qbartemp <= not qbartemp ;

--library UNISIM;

end if;

--use UNISIM.VComponents.all;

end if;

entity JKFlip is
port (

clock

end process;
: in std_logic;

end Behavioral;

: in std_logic;

: in std_logic;

Q,Qn

: out std_logic;

rest

: in std_logic);

D.FLIP FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

end JKFlip;
entity Flip is
architecture Behavioral of JKFlip is
signal qtemp, qbartemp : std_logic :='0';
Port

clc

: in std_logic;

begin
rest
Q

<= qtemp;

Qn

<= qbartemp;

process (clock,rest)

: in std_logic;

: in std_logic;

: out

std_logic);

begin
if ( rest ='1' ) then

end Flip;

qtemp <= '0' ;

architecture Behavioral of Flip is

qbartemp <= '1' ;

begin

elsif (rising_edge (clock) ) then

process (clc, rest)

begin

if (rest = '1') then

Q <= '0' ;
elsif ( clc'event and clc = '1' ) then
Q <= D ;

--Outputs
signal Z : std_logic;
-- No clocks detected in port list. Replace <clock>
below with

end if;
-- appropriate port name
end process;
end Behavioral;
constant <clock>_period : time := 10 ns;

RANGKAIN KOMBISIONAL
LIBRARY ieee;

BEGIN

USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Instantiate the Unit Under Test (UUT)

uut: alarmtemperatursuhu PORT MAP (

--USE ieee.numeric_std.ALL;

oven => oven,

ENTITY alrmtmperatursuhu_tb IS

tungku => tungku,

END alrmtmperatursuhu_tb;

KL => KL,

ARCHITECTURE behavior OF alrmtmperatursuhu_tb IS

PA => PA,

-- Component Declaration for the Unit Under Test

(UUT)

Z => Z

COMPONENT alarmtemperatursuhu

);

PORT(
oven : IN std_logic;
tungku : IN std_logic;
KL : IN std_logic;

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';

PA : IN std_logic;

wait for <clock>_period/2;

Z : OUT std_logic

<clock> <= '1';

);

wait for <clock>_period/2;

END COMPONENT;
--Inputs

end process;

signal oven : std_logic := '0';

signal tungku : std_logic := '0';
signal KL : std_logic := '0';
signal PA : std_logic := '0';

-- Stimulus process
stim_proc: process
begin

-- hold reset state for 100 ns.

wait for 100 ns;

architecture Behavioral of debouncing is

signal A,B : std_logic_vector(2 downto 0) := "000";

wait for <clock>_period*10;

begin
-- insert stimulus here

process (clk,enter)

wait;

begin

end process;

if(clk'event and clk='1') then

A <= A(1 downto 0)& enter; --shift left

END;

end if;

Sistem hirarki

end process;

library IEEE;
process(clk,mode)

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

begin
if (clk'event and clk='1')then
B<= B(1 downto 0) & mode; --shift left

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

end if;
end process;
enter_db <= not(A(2)) and A(1) and A(0);
mode_db <= not(B(2)) and B(1) and B(0);

-- Uncomment the following library declaration if

instantiating

end Behavioral;

T FLIPPLOP

-- any Xilinx primitives in this code.

library IEEE;
--library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
--use UNISIM.VComponents.all;

-- Uncomment the following library declaration if using

entity debouncing is
-- arithmetic functions with Signed or Unsigned values
Port ( clk : in STD_LOGIC;
--use IEEE.NUMERIC_STD.ALL;
enter,mode : in STD_LOGIC;
enter_db , mode_db : out STD_LOGIC);
end debouncing;

-- Uncomment the following library declaration if

instantiating
-- any Xilinx primitives in this code.

--library UNISIM;

ARCHITECTURE behavioral OF
pintumobilcoy_pintumobilcoy_sch_tb IS

--use UNISIM.VComponents.all;
COMPONENT pintumobilcoy
PORT( XLXN_8

IN

STD_LOGIC;

IN

STD_LOGIC;

OUT

STD_LOGIC);

SIGNAL XLXN_8

STD_LOGIC;

SIGNAL XLXN_9

STD_LOGIC;

SIGNAL XLXN_10

STD_LOGIC;

entity TFlip is
XLXN_9

XLXN_10 :
Port

( t

in std_logic;

clc:

in std_logic;

END COMPONENT;

q
qn

:
:

out std_logic;
out std_logic);

end TFlip;
BEGIN
architecture Behavioral of TFlip is
UUT: pintumobilcoy PORT MAP(
begin

XLXN_8 => XLXN_8,

Process (clc,t)

XLXN_9 => XLXN_9,

XLXN_10 => XLXN_10

begin

);
if clc = '1' then

-- *** Test Bench - User Defined Section ***

q <= NOT t;

tb : PROCESS

qn <= t;

BEGIN

end if;
end process;

WAIT; -- will wait forever

END PROCESS;

end Behavioral;

-- *** End Test Bench - User Defined Section ***

pintu mobil

END;

LIBRARY ieee;

SEVEN SEGMENT

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY pintumobilcoy_pintumobilcoy_sch_tb IS
END pintumobilcoy_pintumobilcoy_sch_tb;

--library UNISIM;
--use UNISIM.VComponents.all;
"0101111"
when MSB="0000" else --B
"1100101"

when MSB="0000" else C

"0011111"

when MSB="0000" else --D

"0011111"

when MSB="0000" else --E

"1101100";

--F

entity sevsegmen is
Port ( hasil : in STD_LOGIC_VECTOR (7 downto 0);
ledone,ledtwo : out STD_LOGIC_VECTOR (6
downto 0));

"1101111"

when MSB="0000" else --6

"1010010"

when MSB="0000" else --7

"1111111"

when MSB="0000" else --8

"1111011"

when MSB="0000" else --9

"1111110"

when MSB="0000" else --A

end sevsegmen;
architecture Behavioral of sevsegmen is
end Behavioral;
signal LSB, MSB : std_logic_vector(3 downto 0);
begin
LSB <= hasil(3 downto 0);

DEBOUNCING

MSB <= hasil(7 downto 4);

LIBRARY ieee;

ledone <= "1110111"

USE ieee.std_logic_1164.ALL;

when LSB="0000" else --0

"0010010" when LSB="0001" else --1

-- Uncomment the following library declaration if using

"1011101" when LSB="0010" else --2

-- arithmetic functions with Signed or Unsigned values

"1011011" when LSB="0011" else --3

--USE ieee.numeric_std.ALL;

"0111010" when LSB="0100" else --4

"1101011" when LSB="0101" else --5
"1101111" when LSB="0110" else --6
"1010010" when LSB="0111" else --7
"1111111" when LSB="1000" else --8
"1111011" when LSB="1001" else --9
"1111110" when LSB="1010" else --A
"0101111" when LSB="1011" else --B
"1100101" when LSB="1100" else --C
"0011111" when LSB="1101" else --D
"1101101" when LSB="1110" else --E
"1101100" ;

--F

ENTITY debouncing_tb IS
END debouncing_tb;
ARCHITECTURE behavior OF debouncing_tb IS
-- Component Declaration for the Unit Under Test
(UUT)
COMPONENT debouncing
PORT(
clk : IN std_logic;
enter : IN std_logic;
mode : IN std_logic;
enter_db : OUT std_logic;
mode_db : OUT std_logic
);
END COMPONENT;

ledtwo <= "1110111" when MSB="0000" else --0

"0010010"

when MSB="0001" else --1

"1011101"

when MSB="0000" else --2

"1011011"

when MSB="0000" else --3

"0111010"

when MSB="0000" else --4

"1101011"

when MSB="0000" else --5

--Inputs
signal clk : std_logic := '0';
signal enter : std_logic := '0';

signal mode : std_logic := '0';

--Outputs
signal enter_db : std_logic;

end process;
END;

TFLIP-FLOP

signal mode_db : std_logic;

library IEEE;
-- Clock period definitions
use IEEE.STD_LOGIC_1164.ALL;
constant clk_period : time := 10 ns;
-- Uncomment the following library declaration if using
BEGIN
-- arithmetic functions with Signed or Unsigned values
-- Instantiate the Unit Under Test (UUT)
--use IEEE.NUMERIC_STD.ALL;
uut: debouncing PORT MAP (
clk => clk,

-- Uncomment the following library declaration if

instantiating

enter => enter,

-- any Xilinx primitives in this code.

mode => mode,

--library UNISIM;

enter_db => enter_db,

--use UNISIM.VComponents.all;

mode_db => mode_db

entity TFlip is
Port

( t

clc:

in std_logic;

-- Clock process definitions

:out std_logic;

clk_process :process

qn

:out std_logic);

);

in std_logic;

begin
clk <= '0';

end TFlip;

wait for clk_period/2;

architecture Behavioral of TFlip is

clk <= '1';

begin

wait for clk_period/2;

Process (clc,t)
begin

end process;

if clc = '1' then q <= NOT t;

-- Stimulus process
stim_proc: process

qn <= t;

begin

end if;

-- hold reset state for 100 ns.

end process;

wait for 100 ns;

end Behavioral;

wait for clk_period*10;

alrm ttemperatur suhu

-- insert stimulus here

wait;