HVDC Course Tutorials

Tutorial Supplemental

Prepared by: Randy Wachal Date: June 18, 2008 Revision: 1 Date:

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Tutorial 1B Simple Six Pulse Rectifier Objective(s):

Getting familiar with PSCAD. Introduction to 6 pulse configuration Impact of Commutating reactance Individual thyristors control (PLL timing Waveform)

T1.1 Case Simple_6P.psc; simple_6P_thyristors.psc

V1 RL RL RL RL A B C Eab A B 100.0 [MVA] #1 #2 A B Vab Vbc 0 .0 5 [H ] Vca 1 3 5 Voutdc Vplus 1 .0 [o h m ] Id c 4 6 2 Vminus
Pulsea Eca -1.0 1.0 [ohm] * * * Va Vb Vc 6 1 2 3 4 5 6 PLL thetaY Six 6 Pulse 6 Theta Dblck (1) FP1 (2) FP2 H (3) FP3 L (4) FP4 (5) FP5 (6) FP6 Alpha Order Theta

C 132.0 [kV] C 5.0 [kV]

Fig.1 6 pulse with Diodes Observe Ac and Dc voltages. Adjust transformer leakage impedance between 0 and 45%. Typical DC Values of transformers impedance are 15-20%. Typical Ac transformers impedances are in the range of 5-10%. Why is there a difference? Adjust DC output impedance? What effect does it have on the valve side current waveforms? T1.2 Adjust firing angle alpha and observe impact of DC Voltage and current waveforms. (change Transformer Xc impedance) Observe how firing pulses are generated? (Array of 2 variables) Firing pulses compare Theta ramp with alpha order. How is theta developed? Are there different theta waveforms for each of the 6 valves? Could the same theta waveforms be used if the transformer connection was star/delta instead of star/star? Valve fire timing signals are generated from Ac system voltages and not from Valve side voltages. Why?
Voutdc 2 FP1 1 3 2 FP3 5 2 FP5 Vplus

Eab Ebc -1.0

Idc 0.05 [H]

2 FP4 4 6

2 FP6 2

2 FP2

Vminus

Fig.2 Diodes are replaced with Thyristors

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Tutorial 2A Current Controller Objective(s):

Add PI Current Controller to 12 pulse Rectifier

T2.1: Starting with simple_12P_rectifer.psc add current controller as illustrated below. What are appropriate limits of PI controller for a rectifier? How do you tune Controller Ki and Kp parameters? Why is the factor 0.017453 used as a multiplier?

How do you determine whether the Current Error should be positive or negative for a given set of conditions?

I 0.017453 * P

Idc

T2.2; Add a gamma controller to simple _12P_invertor? What HVDC value does changing gamma control?

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Tutorial 3A HVDC2 AC System Impedance Objective(s):

Introduction to Harmonic Impedance and potential resonance issues LiveWire Post Processing software PSCAD generated output files (snapshot *.snp, *.out) are stored in case name.emt directory.

T3.1 Case HVDC2_Harm_imp.psc Using the phasorimp component develop the impedance profile for the rectifier AC bus and the invertor ac bus. By saving the files to a *.txt allows for easier importing into the post processing viewer program (LiveWire) however this is not necessary. In the PSCAD application the output of the Impedance calculation can be viewed as a text format. The file is saved in HVDC2_Harm_Imp.emt folder In Livewire; use the File>Insert Data from file(s)> command to Insert the datafile for the Rectifier AC impedance file (*.txt) and Plot the Z+ data, Z- data and Z0 magnitude on the plot windows. Explain the consequence of harmonic impedance plot. Add a 2nd harmonic filter on the rectifier AC bus and re calculate the harmonic impedance. Is this change as expected? Repeat for the Invertor bus T3.2 Case HVDC2_Harm_imp.psc: Snapshot Initialization and AC Fault Snapshot is a feature in PSCAD allowing the simulation to begin from a steady state or initialization. Go to Case name project settings: Select Timed Snapshot option and give snapshot file a name and snapshot Time. Run case and allow it to get to steady state. Snapshot file will be created. Now go back to project and change Timed Snapshot to None ( you dont want to write over your snapshot file) and Select Startup from Snap and select appropriate snapshot file from Case name.emt folder Suggestion: It makes sense to select time as integer. Ie 1 or 10 seconds, PSCAD graphs can be reset to zero when starting from a Snapshot file, but Case time is still Snapshot time + new case time. When applying a fault transient remember to include snapshot time.. If snapshot is = 1.0, Fault applied at 1.5 seconds will occur at 0.5 sec when starting from Snap is selected. Generate Snapshot file and start from Snapshot. Apply slg and 3 phase fault Ac fault at rectifier bus, and ac invertor bus using the snapshot feature For a rectifier and then inverter side, ac fault, what is the impact on rectifier and invertor DC voltage and current? Why is there fundamental frequency on DC Voltage? Looking at DC current can you tell where the fault is? How? T3.3 Case HVDC2_Harm_imp.psc: Output Files. Go to Case name project settings: Select Save Channels to disk? option and give output files a name. Run case and Generate output files In Livewire use the File>Insert Data from file(s)> command to insert the EMTDC.inf datafile name from the HVDC2_Harm_imp.emt folder. Every output channel will be available. Change the PSCAD case and resolve it. Livewire will detect a new timestamp on the *.out files and ask to reload with the new data.

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Tutorial 6: Pole Deblock Transients Objective(s):

Investigate Pole Deblock transients. Illustrate the use of sequence control blocks within PSCAD

T3.1 Case HVDC3_Deblock.psc In order to place a HVDC Pole into service typically it is done in at least two steps. The 1st step is to energize the transformers at both rectifier and Inverter sides. This is usually done independently at each side. Next step would be to deblock (or release) firing pulses at each end.

GRS

AM GM

ARS

Com. Bus

The value KBR controls the fire pulse deblock at the Rectifier and KBi will control the invertor.

AO 6 Pulse Bridge KB KBR

This case has been modified to allow the transformer to energize first and after any transformer transient has decayed away then deblock the rectifier.

D1

RECTIFIER 1000MW 500KV

1.

Deblock the rectifier before the inverter. Happens to the DC current and DC voltage at each end.

2. Deblock the inverter before the rectifier. Do the DC current and Voltage respond the same? Explain any differences. Look also at AC system voltage. 3. Does the starting value of the Current / Gamma PI controller(s) make a difference in the response? 4. What is the MVar requirement for rectifier before Invertor and Invertor before rectifier? In high ESCR system is this important, what about low ESCR systems, why? Is it possible or desirable to deblock both Rectifier and Inverter at exactly the same time?

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Tutorial 7: BiPole Power Controller Objective(s):

Investigate Bipole system using an overall system power controller.

T3.1 Case HVDC5_BipolePO.psc Pole 1 Positive Pole is deblocked at 0.04 seconds and can develop 1 pu voltage. Pole 1 in operation by itself circulates return current through the ground (or metallic) return. Pole 2 (negative pole) deblocks at 1 second. The current order for Pole 1 and Pole2 should be equal (eliminate ground current) and is determined by Power Order / DC Voltage. Depending on the value of DC voltage, the current order for a specific power order is calculated.

P1_Iorder

VDCIp2 VDCI

RMS RMS

N BP_PO Bipole Power Order

N/D D 1.1

D E

Min

P1_Iorder 1.0

P2_Iorder

[Invctl] P1_VDC

D + F 1.0

D E

Max

[Invctl] P2_VDC

1.

Evaluate performance at various power levels. Start at a low value and increase. 0.3, 0.5, 0.75. 1.0 Per unit Bipole power order. In this model ac voltages are fixed. (no tap changer control implemented) At what level of power order is power delivered not equal to power actual? Why and how is this adjusted?

2. What methods could be used to minimize Pole deblock transients? 3.

0.1

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P2_Iorder