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topics related to Verification,
ModelBased Design and
architecture of asic
Presentation flow
1. Verification Flow.
2. Verification in Asic.
3. Steps to reduce verification.
4. Timescale for verification of Asic.
5. How architecture is defined?
6. How much detailing need to defined at architecture level ?
7. Outputs we get from architecture stage.
8. Introduction to ModelBased Design
9. How Model based design reduces verification time ?
10. Example on modelBased Design.
Verification flow
1. Feature extraction from design
specification.
2. Listing out test cases.
3. Verification Environment
Architecture Plan
Verification flow contd.
Feature Extraction:
Task: Extract features from design specifications.
Which Features:
1. covered by random stimulus generation ,
2. verifiable by separate test cases,
3. coverage module contain,
4. features the assertion can catch.
Verification flow contd.
Verification Environment Architecture Plan
Task:
Prepares the structure of verification environment.
Points Included in structure :
Based of project requirements following points are considered while
architecture is built
1. re usability.
2. Is it a verification IP
3. What blocks the verification language can support ?
4. Controllability of the stimulus generation.
Verification in Asic
Type of Verification Where it is placed Which tools it uses. Need
HDL(verilog) or
Functional Verification RTL HVL(e, Vera, SystemC) For Checking functional correctness of asic design
What: cosimulation is the simulation of model of the hardware running
the software simultaneously providing visibility of hardware model while
allowing the software to be controlled and observed at any and all levels
of detail necessary of understanding system behavior.
How: It allows to verify the system after each stage, instead of verifying
at the final stage. thereby reduces the verification time
Steps to reduce verification
time
Use of Emulator to check Hardware
What: Emulator is a hardware device that can be used to emulate a
piece of hardware functionality. It is commonly used as a
debugging tool to test a system under development for
functional correctness.
How: 1. Emulation is a faster solution to verification problem.
2. In Emulation a portion of emulatable design is synthesised
and optimized. The compiled design is then loaded onto an
emulator.
3. Emulators are able to provide execution speed
close to real time. This allows verification engineers to
reduce verification time.
Steps to reduce verification
time
Use of assertion based verification:
What : Assertionbased verification is the methodology that allows
assertion to be specified. Assertion are design check to catch the
bugs early.
How : 1. Simplying diagnosis and detecting bugs by localizing
occurrence of suspected bug, thereby reducing simulationdebug
time significantly.
2. Selfchecking code helps in design reuse which ultimately
reduces verification time.
Time Scale For verification of
asic
Total design and verification time
5.50%
5.50%
3.50% Design
2.50% Functional and logic
verification
40.00% Static time analysis
Signal Integrity
15.00%
Power Checking
Other
Physical verification
28.00%
How Architecture is defined ?
●
The Architecture of the asic can be defined
by partitioning the function on the block
diagram , clearly specifying the functions ,
interfaces and interactions.
●
A verification plan shall be
established,defining how the functionality of
design is verified
What details Architecture
document contains ?
1. Introduction
✔
Applicable and reference documents
✔
Acronyms and Abbreviations.
✔
Numbering and Naming conventions.
✔
Discrepancies w.r.t functional specification.
2. Architectural Description
✔
Block partitioning
✔
Data format and protocols
✔
High level block diagram with data and control flows.
✔
External devices and protocol
✔
HDL model overview
contd.
✔
Detailed Architecture Description
✔
Block diagram
✔
Block Interaction
✔
Test architecture and interfaces
✔
Reset generation
✔
Buitin self test
✔
Block Descriptions [for each block]
✔
purpose and sequence of operations
✔
Interfaces
✔
Internal Structure
✔
Detailed Functionality
✔
State machine graphs
✔
Handling unused states
contd.
3. Feasibility analysis of the architecture
✔
Operating frequency
✔
Power dissipation
✔
Metastability
✔
Complexity and Packaging issues
What are the outputs from
architecture stage?
●
Verification plan : Defines how the
functionality of design is verified.
●
Architecture Design Document
●
Preliminary datasheets : Showing all the
parts. where data is not known, such as for
timing,estimates shall be used
Introduction to ModelBased
Design
✔
In ModelBased Design, a system model is at the center of the
development process from requirements capture and design to
implementation and test.
✔
✔
Model Based Design contd.
✔
The model is an executable specification that is continually refined
throughout the development process. Simulation shows whether the
model works correctly.
When software and hardware implementation requirements are
included, such as fixedpoint and timing behavior, you can
automatically generate code for embedded deployment and create test
benches for system verification, saving time and avoiding the
introduction of handcoding errors.
Advantages of ModelBased
Design
1. Executable models : keeps design at algorithmic level until it is
completely verified.
2. Cost reduces
Reduce rework
reducetesting
3. Automatic code generation
minimizes coding errors.
4. Test with design
Detects error earlier : it moves the verification process all the way to
the beginning of design cycle and thus helps to detect system specification
related errors ,design error and implementation error early.
Steps for ModelBased Design
1. Create an executable specification consisting of algorithms, system model
and system level verification environment.
2. verify the system model against functional requirements using simulation.
3. automatically generate HDL code for asic.
4. Employ the executable specification as a testbench to verify software and
hardwareimplementations.
Thank You