33arm Selector Guide

SPRING2007
ARROW ARM SOLUTIONS GUIDE
ARM Solutions c
www.arrownac.com/arm
ARM SUPPORT
4 Arrow Services and Solutions
Table of Contents
ARM CORES
8 ARM7TDMI
10 ARM920T
12 ARM926EJ-S
14 ARM966E-S
16 ARM1136J(F)-S
18 ARM Cortex-A8
20 ARM Cortex-M3
It’s a fact. Arrow Electronics is the
22 ARM CortexR4(F)
only distributor and approved training
24 Intel XScale®
center for ARM tools in North America.
Which means we can solve your
ARM-powered design challenges
ARM SUPPLIERS
efficiently and completely. Our broad
line card features more than a dozen
major silicon suppliers offering ARM
technology and our innovative services
can help you at every point in your
design cycle. Whether you need 34 Freescale
support for ARM software development i.MX31
or architecture, you can rely on Arrow 36 Intel®
to deliver up-to-date and accurate Intel® Network Processors and Intel® I/O Processors
technical information from well-versed
industry experts. Arrow’s vast line card,
services, and unparalleled expertise 40 NXP
deliver comprehensive ARM solutions LPC210x | LPC23xx and LPC24xx | LPC2478
that get you to market faster. 46 STMicroelectronics
STR7 and STR9 Families | STR730F | STR710F | STR750F |
STR910F
54 Texas Instruments
DaVinci™
TOOLS
58 IAR
IAR Embedded Workbench Version 4.41 for ARM
60 Keil
The Keil RealView Microcontroller Development Kit
62 ARM
RealView Tools by ARM
Arrow Electronics ARM Solutions

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4 |
ARM Support from Concept through Production

Arrow solves your ARM challenges through outstanding technical support, training, and seminars designed to address your
specific ARM requirements. We’re here to help you navigate at every point in the design cycle.
Engineering Expertise—the Right Team Arrow Technical Solutions Forum (ATSF): c

for the Job c ARM Seminar Series for Cost-Sensitive
Arrow’s Field Applications Engineers (FAEs) provide expert Applications
support for all your design requirements, no matter where you This seminar series offered by Arrow addresses embedded
are located. Our FAEs undergo monthly ARM training and customers’ demand for ARM technology and supports your
constantly deliver the latest technical overviews of ARM emerging requirements.
technologies, so you can rest assured the information you ARM offers some of the
receive is accurate, up-to-date, and relevant. best solutions for balanc-
ing the needs for high per-
formance, high integration, low power, and small die sizes
The Industry’s Only ARM Training Center c (low cost). This ARM technology seminar series provides
valuable solutions that get you to market faster. Visit
Arrow is the “go-to source” for ARM training. It’s the only
www.arrownac.com/atsf for more information.
approved ARM training center in North America and the
only distributor for ARM tools. You can turn to us for relevant
technical information conveyed by seasoned
ARM Seminar Series for High-End
trainers because our team draws from the
Applications
world’s largest and most experienced pool
of ARM technology experts. Our field ARM technology is widely used in high-performance applications
trainers provide multi-day classes that that require the most from a processor yet need to maintain a
dive deep into ARM architectures and low power profile. This seminar series is aimed at applications
surrounding development tools. These that utilize media, complex user interfaces, and computational-
classes can be conducted at any Arrow intensive applications on large data segments. The higher end
branch or customer location and give you access to quality of the industrial, medical, transportation, and other commercial
technical training available only from Arrow and ARM. markets is addressed, providing you with valuable, effective
To register or for more information, go to solutions. For more information, visit www.arrownac.com/atsf.
www.arrownac.com/arm.
EmbeddedDeveloper.com c
Finding the right ARM solution has never been easier.
With EmbeddedDeveloper.com, you can search ARM
devices by core type, peripheral sets, price, and many
other specifications. Compare and contrast device functions,
download specifications and datasheets, and even go to
the Arrow shopping
cart and buy the best
development tool FIND. COMPARE. BUY.
solution on-line.
For information on Arrow’s ARM training and seminars, visit www.arrownac.com/arm or call 1-866-910-3650.

1-866-910-3650
| 5
Innovative Arrow Services

Access to comprehensive ARM offerings and leading suppliers is complemented by Arrow services that go far beyond
getting you the components you need. Our engineering services, on-line development tool selection process, complimentary
development tool evaluation program, supply chain solutions, and custom logic solutions ensure the success of your design
from concept to production.
Arrow Consulting Engineering Services c Supply Chain Solutions c

The Arrow Consulting Engineering Services (ACES) program For decades, Arrow has successfully managed one of the most
puts you in touch with pre-screened, qualified, and certified complex supply chains in the world, allowing us to offer
third-party solutions and design unmatched insight and expertise. Our services, which include
services companies so you can collaborative material planning tools, vendor managed inventory
save time, effort, and resources. programs, performance analysis services, materials management
The superior core competencies programs, and electronic communication services, can support
of our partners allow them to your needs throughout a product’s entire lifecycle—from the
provide complete outsourced technical discovery stage to design and prototype development,
designs—while allowing you to and through production and product end of life.
focus on your core competency.
Custom Logic Solutions c

Arrowdevtools.com c Arrow’s Custom Logic Solutions group has partnered with
Find the best reference designs and evaluation tool solutions industry leaders to meet your custom logic needs with the
with arrowdevtools.com—an on-line development tool selection right combination of vendor technology, design services, and
and purchasing intellectual property.
process that gives you Solutions range from
access to a vast range small FPGAs to
of development tools. structured ASICs, to
This proprietary highly complex standard cell ASICs. More than 130 local
parametric search engine allows you to narrow your tool search engineers and over 20 factory Custom Logic Solutions
quickly and intuitively to the unique tool you need to keep your engineers, as well as integrated staff from Arrow’s network of
development on track. Browse and compare different solutions design services partners, provide comprehensive design services
and then conveniently and confidently purchase your tool for that help you get to market quickly with the right product at the
immediate delivery from arrowdevtools.com on-line or through lowest possible risk and cost. Custom Logic Solutions also
Arrow’s sales team. Arrowdevtools.com offers everything you extends engineering support into the IP space, enabling you
need to move your project rapidly to completion. to piece together complex SOCs (Systems On A Chip) without
having to be “experts at everything.”
TestdriveSM c
Arrow’s Testdrive tool evaluation program helps you save time Global Programming Services c
and money on your designs. The program allows you to try tools More and more companies are relying on programmable
before you buy them, free of charge for 21 days. You can test a devices to improve performance, simplify design, reduce chip
vast selection of tools count, and ease manufacturing. To help you keep up with
from all the major constant advances in technology, Arrow has developed Global
semiconductor suppliers Programming Services to support procurement and the actual
without impacting your programming of your devices. Our services can give you greater
budget. Additionally, levels of scheduling flexibility, reduce internal coordination and
Arrow’s Field Applications Engineers are familiar with the tools tracking, and avoid cost on capital equipment and staffing, to
offered through Testdrive and can work through any issues that get you to market faster.
may arise, saving you precious resources and giving you access
to some of the industry’s leading expertise.
For information on Arrow’s Innovative Services, visit www.arrownac.com/arm or call 1-866-910-3650.
8 |
ARM7TDMI and ARM7TDMI-S

ARM 32-Bit RISC Core with 16-Bit System Costs
The ARM7TDMI core is the industry’s most widely used 32-bit embedded RISC microprocessor. The ARM7TDMI-S is a
synthesizable version of the ARM7TDMI. Optimized for cost- and power-sensitive applications, the ARM7TDMI solution
provides the low power consumption, small size, and high performance needed in portable, embedded applications.
The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best
combination of performance, power, and area characteristics. The ARM7TDMI core enables system designers to build
embedded devices requiring small size, low power, and high performance.
The ARM7 family also includes the ARM7TDMI processor, the ARM7TDMI-S processor, the ARM720T processor, and the
ARM7EJ-S processor, each of which has been developed to address different market requirements.
RISC Advantages c
The ARM architecture is based on the Reduced Instruction Set
Computer (RISC) principles. The RISC instruction set and
ETM Interface
related decode mechanism are much simpler than those of the
Complex Instruction Set Computer (CISC) designs. This
simplicity has the following advantages: Control EmbeddedICE-RT Thumb
logic logic decoder
• A high instruction throughput
• An excellent real-time interrupt response
• A small, cost-effective, processor macrocell
32-bit High-performance
ALU multiplier
ARM7TDMI-S
The Instruction Pipeline c

• The instruction pipeline Bus Interface Unit
• Memory access
• Memory interface Coprocessor
• EmbeddedICE Interface
The Instruction Pipeline c

The ARM7TDMI core uses a pipeline to increase the speed of
the flow of instructions to the processor. This allows several
operations to take place simultaneously. Memory Access c
The ARM7TDMI core has a Von Neumann architecture with a
A three-stage pipeline is used, so instructions are executed in
single 32-bit data bus carrying both instructions and data. Only
three stages:
load, store, and swap instructions can access data from memory.
• Fetch (the instruction is fetched from memory) This simplifies the internal logic of the processor memory inter-
• Decode (decoding of registers used in the instruction) face using less die area.
• Execute (register/s read from register bank; shift and ALU
operations; write register/s back to register bank)
Memory Interface c
During normal operation, while one instruction is being executed,
The ARM7TDMI processor memory interface has been designed
its successor is being decoded and a third instruction is being
to allow performance potential to be realized while minimizing the
fetched from memory.
use of memory. Speed-critical control signals are pipelined to
allow system control functions to be implemented in standard
low-power logic. These control signals facilitate the exploitation
of fast-burst access modes supported by many on-chip and
off-chip memory technologies.

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EmbeddedICE-RT Logic c On execution, 16-bit Thumb instructions are transparently

The EmbeddedICE-RT logic provides integrated on-chip debug decompressed to full 32-bit ARM instructions in real time
support for the ARM7TDMI core. You use the EmbeddedICE-RT without performance loss.
logic to program the conditions under which a breakpoint or
watchpoint can occur.
Applications c
The EmbeddedICE-RT logic contains a Debug Communications
• Industrial
Channel (DCC), which is used to pass information between the
• Automotive
target and the host debugger. The EmbeddedICE-RT logic is
• Personal audio (MP3, WMA, and AAC players)
controlled through the Joint Test Action Group (JTAG) test
access port.
Features c
Architecture c • 32-/16-bit RISC architecture (ARM v4T)
• 32-bit ARM instruction set for maximum performance
The ARM7TDMI processor has two instruction sets: and flexibility
• The 32-bit ARM instruction set • 16-bit Thumb instruction set for increased code density
• The 16-bit Thumb® instruction set • Unified bus interface; 32-bit data bus carries both
instructions and data
Having both 32-bit ARM instructions and 16-bit Thumb • Three-stage pipeline
instructions gives the ARM7TDMI processor two advantages: • 32-bit ALU
instruction compression and higher performance over typical • Very small die size and low power consumption
16-bit architectures. • Fully static operation
• Coprocessor interface
Microprocessor architectures traditionally have the same • Extensive debug facilities:
width for instructions and data. In comparison with 16-bit – EmbeddedICE-RT real-time debug unit
architectures, 32-bit architectures exhibit higher performance
– JTAG interface unit
when manipulating 32-bit data and can access a large address
– Interface for direct connection to Embedded Trace
space much more efficiently.
Macrocell (ETM)
Typically, 16-bit architectures have higher code density than
32-bit architectures, but they have approximately half the
performance.
Benefits c
The Thumb instructions implement a 16-bit instruction set on a • Generic layout can be ported to specific process
32-bit architecture to provide: technologies
• ARM and Thumb instruction sets can be mixed with
• Higher performance than a 16-bit architecture minimal overhead to support application requirements for
• Higher code density than a 32-bit architecture speed and code density
• Small die size reduces overall SoC area, cost, and power
The Thumb instruction set is a subset of the most commonly consumption
used 32-bit ARM instructions. Thumb instructions are each • EmbeddedICE-RT and optional ETM units enable
16 bits long and have a corresponding 32-bit ARM instruction. extensive, real-time debug facilities
This has the same effect on the processor model. Thumb
instructions operate with the standard ARM register
configuration, allowing excellent interoperability between
ARM and Thumb states.
Performance Characteristics c
0.18 µm 0.13 µm 0.090 µm
Speed Optimized Speed Optimized Speed Optimized
Frequency* (MHz) 115 133 236
Area (mm2 ) 0.59 0.26 0.18
Power** (mW/MHz) 0.21 0.06 –
*Worst-case conditions—0.18 µm process—1.62V, 125°C, slow silicon; 0.13 µm process—1.08V, 125°C, slow silicon; 90 nm process—0.9V, 125°C, slow silicon
**Typical-case conditions—0.18 µm process—1.8V, 25°C, typical silicon; 0.13 µm process—1.2V, 25°C, typical silicon; 90 nm process—1V, 25°C, typical silicon
10 |
ARM920T
High-Performance and Low-Power Platform OS
The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of
fetch, decode, execute, memory, and write stages. It can be provided as a standalone core that can be embedded into
more complex devices. The standalone core has a simple bus interface that allows you to design your own caches and
memory systems around it.
The ARM920T processor is a member of the ARM9TDMI family of general-purpose microprocessors, which includes:
• ARM9TDMI (core)
• ARM940T (core plus cache and protection unit)
• ARM920T (core plus cache and MMU)
ARM920T Application Support Features c

The ARM9TDMI family of microprocessors supports both the
32-bit ARM and 16-bit Thumb® instruction sets, allowing you ETM Interface
to trade off between high performance and high code density.
The ARM920T processor is a Harvard cache architecture
processor that is targeted at multi-programmer applications
where full memory management, high performance, and low 16K 16K
Instruction Data
power are all-important. The separate instruction and data cache cache
ARM9TDMI
caches in this design are 16 KB each in size, with an eight-word core
MMU MMU
line length. The ARM920T processor implements an enhanced
ARM architecture v4 MMU to provide translation and access
permission checks for instruction and data addresses. Write buffer
ARM920T
The ARM920T processor supports the ARM debug architecture Control Logic and Bus Interface Unit
and includes logic to assist in both hardware and software
debug. The ARM920T processor also includes support for
coprocessors, exporting the instruction and data buses along Coprocessor
with simple handshaking signals. Interface AMBA AHB Interface
The ARM920T’s interface to the rest of the system is over

unified address and data buses. This interface enables
implementation of an Advanced Microcontroller Bus Architecture
(AMBA), an Advanced System Bus (ASB), or an Advanced
High-performance Bus (AHB) scheme either as a fully compliant
AMBA bus master, or as a slave for production test. The
ARM920T processor also has a Tracking ICE mode, which
allows an approach similar to a conventional ICE mode of
operation.
The ARM920T processor supports the addition of an
Embedded Trace Macrocell (ETM) for real-time tracing of
instructions and data.

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Applications c • MMU which supports operating systems including

• Automotive infotainment Symbian OS, Windows CE, Linux, and Palm OS
• Industrial connectivity • Instruction and data caches: ARM920T = 16K/16K,

ARM922T = 8K/8K
• Medical handheld
• Industry-standard AMBA bus interface
• Platform OS-based devices
• ETM interface for real-time trace capability with ETM9
• Next-generation smart phones,
communicators, and PDA’s
• 3G baseband and applications processor

Benefits c
• Runs all major OS’s and existing middleware
• Digital still camera
• Single development toolkit for reduced development
• Audio and video decoding costs and shorter development cycle time
• Set-top box • Multiple sourcing from industry-leading silicon vendors
• Code-compatible upward migration path to ARM10E

family
Features c
• 32-/16-bit RISC architecture (ARMv4T) • Excellent debug support for SoC designers
• 32-bit ARM instruction set for maximum performance • Instruction set can be extended by the use of
and flexibility coprocessors
• 16-bit Thumb instruction set for increased code density
0.18 µ M 0.13 µM
Speed Optimized Speed Optimized
Frequency* (MHz) 190-200 230-250
Area with cache (mm2) 11.80 4.70
Cache size 16K/16K 16K/16K
Power with cache** (mW/MHz) 0.80 0.25
*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon
**Typical-case conditions—0.18 µm process–1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon
12 |
ARM926EJ-S
ARM926EJ-S Jazelle-Enhanced Macrocell Processor
The ARM926EJ-S™ fully synthesizable processor features a Jazelle-enhanced 32-bit RISC CPU, flexible size
instruction and data caches, Tightly Coupled Memory (TCM) interfaces, and a Memory Management Unit (MMU).
It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for multi-layer AHB-based
systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit
multiplier, capable of single-cycle MAC operations. The instruction set includes 16-bit fixed-point DSP instructions to
enhance performance of many signal processing algorithms and applications as well as supports Thumb® and Java byte-
code execution.
The ARM926EJ-S processor is a member of the ARM9 family of

general-purpose microprocessors. The processor is targeted at
multi-tasking applications where full memory management, high
ETM9 Interface
performance, small die size, and low power are all important.
The processor supports the 32-bit ARM and 16-bit Thumb Instruction Data
instruction sets, enabling the user to trade off between high per- TCM interface TCM interface
formance and high code density. The ARM926EJ-S processor
includes features for efficient execution of Java byte codes, pro- Instruction Data
viding Java performance similar to JIT, but without the associated cache ARM9EJ-S cache
code overhead. MMU core MMU
The ARM926EJ-S processor supports the ARM debug architec- ARM926EJ-S

ture and includes logic to assist in both hardware and software Write buffer
debug. The processor has a Harvard cached architecture and
Control Logic and Bus Interface Unit
provides a complete high-performance processor subsystem,
including:
• An ARM9EJ-S integer core Coprocessor AMBA AHB interface
Interface Instruction Data
• An MMU
• Separate instruction and data AMBA AHB bus interfaces
• Separate instruction and data TCM interfaces
The ARM926EJ-S processor provides support for external

coprocessors, enabling the addition of other floating-point or The tightly coupled instruction and data memories are
other application-specific hardware acceleration. The processor instantiated externally to the ARM926EJ-S macrocell, providing
implements ARM architecture version 5TEJ. you with the flexibility to optimize the memory subsystem for
performance, power, and particular RAM type. The TCM
The ARM926EJ-S processor is a synthesizable macrocell. This
interfaces enable non-zero wait-state memory to be attached,
means that you can optimize the macrocell for a particular target
as well as provide a mechanism for supporting DMA.
library, and you can configure the memory system to suit your
target application. You can individually configure the cache sizes
to be any power of two between 4 KB and 128 KB.

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Applications c Benefits c
• Automotive infotainment • Runs all major OS’s and existing middleware
• Audio and video decoding • Single-chip MCU, DSP, and Java solution
• Platform OS-based devices • Support for leading Java run-times
• Next-generation smart phones, communicators, • High-efficiency Java bytecode execution

and PDAs
• Ultra-low Java power consumption
• 3G baseband and applications processor
• Java JIT compiler performance without the
• Digital still camera disadvantages
• Jazelle support code has no increase in VM size
Features c • Simple single-processor software structure, no need

• 32/16-bit RISC architecture (ARMv5TEJ) for software partitioning across MCUs
• 32-bit ARM instruction set for maximum • Single development toolkit for reduced development
performance and flexibility costs and shorter development cycle time
• 16-bit Thumb instruction set for increased code density • Multiple sourcing from industry-leading silicon vendors
• DSP instruction extensions and single-cycle MAC • Code-compatible upward migration path through to
the latest cortex family of processors
• ARM Jazelle technology
• Process portable synthesizable design
• MMU which supports operating systems including
Symbian OS, Windows CE, and Linux • Excellent debug support for SoC designers
• Flexible instruction and data cache sizes • Instruction set can be extended by the use of
coprocessors
• Instruction and data TCM interfaces with
wait-state support • ARM-EDA Reference Methodology deliverables
significantly reduce the time to generate a specific
• EmbeddedICE-RT logic for real-time debug technology implementation of the core and to generate
industry-standard views and models
• Industry-standard AMBA bus AHB interfaces
• Optional MOVE coprocessor delivers video encoding

performance
0.18 µ M 0.13 µ M 90 nm
Speed Optimized Speed Optimized Area Optimized Speed Optimized Area Optimized
Standard cells SAGE-X SAGE-HS SAGE-X Advantage-HS Metro
Memories HSHD HSHD HSHD Advantage Metro
Frequency* (MHz) 200 276 238 500 250
Area with cache (mm2 ) 6.5 2.78 2.39 1.55 0.85
Area without cache (mm2 ) 3 1.61 1.45 1.05 0.50
Cache size 8K/8K 8K/8K 8K/8K 8K/8K 8K/8K
Power with cache** (mW/MHz) – – 0.48 0.29 0.14
Power without cache** (mW/MHz) – – 0.36 0.24 0.11
*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon; 90 nm process—0.9V, 125˚C, slow silicon
**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon; 90 nm process—1V, 25˚C, typical silicon
14 |
ARM966E-S
Embedded Core with Flexible Memory System and DSP Instruction Set Extensions
The ARM966E-S processor is targeted at a wide range of embedded applications where high performance, low system
cost, small die size, and low power are all important. The ARM966E-S macrocell is a fully synthesizable 32-bit RISC
processor aimed specifically at embedded hard real-time applications. The core implements the ARMv5TE instruction
set and features an enhanced 16 x 32-bit multiplier capable of single-cycle MAC operations, and 16-bit fixed point DSP
instructions to accelerate signal processing algorithms and applications.
The ARM966E-S processor has separate, directly connected

instruction and data Tightly Coupled Memory (TCM), which
have flexible sizes and run at the processor clock speed. The
ETM Interface
ARM966E-S processor supports ARM’s real-time trace
technology with the optional ETM9 Embedded Trace Macrocell.
The ARM966E-S features a simple memory map providing an
area and power-efficient solution for applications that do not
require complex memory management support. The core
Instruction Data
includes an AMBA AHB™ interface and a coprocessor TCM interface TCM interface
ARM9E
interface for connection to application acceleration hardware core
such as the VFP9-S floating-point coprocessor.
The ARM966E-S processor provides a high-performance
ARM966E-S
Write buffer
processor subsystem that includes the ARM9E-S RISC integer
CPU core featuring: Control Logic and Bus Interface Unit
• ARMv5TE 32-bit instruction set with improved
ARM/Thumb code inter-working and enhanced
multiplier designed for improved DSP performance Coprocessor
AMBA AHB interface
Interface
• ARM debug architecture with additional support for
real-time debug; this enables critical exception handlers
to execute while debugging the system
• Support for external TCM; a TCM interface is provided

for each of the external instruction and data memory
blocks; the TCM interfaces of the ARM966E-S processor
enable high-speed operation without incurring the • An AMBA AHB bus interface
performance and power penalties of accessing the
system bus, while having a lower area overhead than a • Support for external coprocessors enabling floating-
cached memory system; the size of both the Instruction point or other application-specific hardware acceleration
and Data TCM blocks are implementor-specific to enable to be added
tailoring of the hardware to the embedded application
• Support for the use of a scan test methodology for
• A simple fixed memory map for the local TCM, ideal the standard-cell logic and Built-In-Self-Test (BIST)
for real-time embedded control applications for the TCM
Providing this complete high-frequency subsystem frees the SoC

designer to concentrate on design issues unique to their system;
the synthesizable nature of the device eases integration into
ASIC technologies.

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Applications c Benefits c
• Automotive control: Powertrain with VFP9-S coprocessor • Single-chip MCU and DSP solution
• Industrial control • Deterministic performance from TCM memories
• Mass storage devices: hard disc drives and DVD drives • Simple single-processor software structure; no need
for software partitioning across MCUs and eliminates
• Networking systems multi-MCU debugging
• Wireless devices • Single development toolkit: reduced development

costs and shorter development cycle time
• Digital still cameras
• Optimized for hard real-time applications
• Multiple sourcing from industry-leading silicon vendors

Features c
• 32-/16-bit RISC architecture (ARMv5TE) • Code-compatible upward migration path to
ARM10E family
• 32-bit ARM instruction set for maximum performance
and flexibility • Excellent debug support for SoC designers
• 16-bit Thumb instruction set for increased code density • Instruction set can be extended by the use of
coprocessors
• Tightly Coupled Memories (TCMs)
• ARM-EDA Reference Methodology deliverables
• EmbeddedICE-RT logic for real-time debug significantly reduce the time to generate a specific
technology implementation of the core and to generate
• Floating point capability with VFP9-S coprocessor industry-standard views and models
• ARM-Synopsys Reference Methodology compliant Core area, frequency range, and power consumption are
deliverables
dependent on process, libraries, and optimizations. The
• Optional MOVE coprocessor delivers video encoding numbers quoted above are illustrative of synthesized cores
performance using general-purpose TSMC process technologies and
ARM Artisan standard-cell libraries and RAMs.
The speed-optimized implementations refer to the library
choices and synthesis flow decisions and tradeoffs made
in order to achieve the target frequency performance. The
area-optimized implementations refer to the library choices
and synthesis flow decisions and tradeoffs made in order to
achieve a target area density.
0.18 µ M 0.13 µM 90 nm
Speed Optimized Speed Optimized Speed Optimized Area Optimized
Standard cells NA NA Advantage-HS Metro
Frequency* (MHz) 200 250 500 250
Area (mm2) 2 1 0.70 0.35
Power** (mW/MHz) 0.70 0.25 0.15 0.07
16 |
ARM1136J(F)-S
A High-Performance, Low-Power Processor with DSP and Media Extensions
The award-winning ARM1136J-S™ and ARM1136JF-S™ processors deliver up to 660 Dhrystone 2.1 MIPS in a 0.13 µm
process. Both processors feature the ARM v6 instruction set with media extensions, ARM Jazelle® technology for efficient
embedded Java execution, ARM Thumb® code compression, and an optional floating-point coprocessor. Media processing
extensions offer up to 1.9x the acceleration of media-processing tasks such as MPEG4 encode.
Instruction and data cache sizes are configurable, and optional Tightly Coupled Memories (TCMs) can be added to
accelerate interrupt handling and data processing. These processors feature AMBA® 2.0 AHB™ interfaces compatible
with a wide range of system IP and peripherals. The ARM1136JF-S processor also features an integrated floating-point
coprocessor, which makes it particularly suitable for embedded 3D-graphics applications.
The ARM1136JF-S processor incorporates an integer unit that

implements the ARM architecture v6. It supports the ARM and
Thumb instruction sets, Jazelle technology to enable direct
execution of Java bytecodes, and a range of SIMD DSP
instructions that operate on 16-bit or 8-bit data values in
Debug VFP Coprocessor
32-bit registers.
Interface Controller
The ARM1136JF-S processor is a high-performance, low-power,
ARM cached processor macrocell that provides full virtual mem-
ory capabilities. Instruction Data
Cache Cache
ARM1136J-S
TCRAM core TCRAM
Features
F - SS
c
M 1 1 3 6 J (F)-
• An integer unit with integral EmbeddedICE-RT logic

Memory Management
• An eight-stage pipeline
• Branch prediction with return stack

Instruction Data Peripheral
• Low-interrupt latency DMA
AARRM
Interface Interface Port

• External coprocessor interface and coprocessors
14 and 15
• Instruction and Data Memory Management Units (MMUs),

managed using MicroTLB structures backed by a unified
Main TLB
• Instruction and data caches, including a non-blocking

data cache with Hit-Under-Miss (HUM) Core c
The ARM1136JF-S processor is built around the ARM11 core
• The caches are virtually indexed and physically in an ARMv6 implementation that runs the 32-bit ARM, 16-bit
addressed, and have a 64-bit interface to both caches Thumb, and 8-bit Jazelle instruction sets. The processor contains
EmbeddedICE-RT logic and a JTAG debug interface to enable
• Level-one TCM that can be used as a local RAM with
hardware debuggers to communicate with the processor.
DMA, or as SmartCache
• High-speed Advanced Microprocessor Bus Architecture Registers c

(AMBA) level two
The ARM1136JF-S core contains:
• Vector Floating-Point (VFP) coprocessor support
• 31 general-purpose 32-bit registers
In addition to the ARM1136J-S, ARM introduced a version that
• Seven dedicated 32-bit registers
includes a VFP coprocessor. This is designated as the
ARM1136JF-S.

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Thumb Instruction Set c Memory System c

Thumb is an extension to the ARM architecture. It contains a The core provides a level-one memory system with
subset of the most commonly used 32-bit ARM instructions that the following features:
has been encoded into 16-bit wide opcodes, to reduce memory
requirements. • Separate instruction and data caches
• Separate instruction and data RAMs

DSP Instructions c
• 64-bit datapaths throughout the memory system
The ARM DSP instruction set extensions provide the following:
• Complete memory management
• 16-bit data operations
• 32-bit dedicated peripheral interface
• Saturating arithmetic
• MAC operations Applications c
Multiply instructions are processed using a single-cycle 32x16 • Automotive infotainment: in-car entertainment, DVD
implementation. There are 32x32, 32x16, and 16x16 multiply players, and navigation equipment
instructions (MAC).
• Networking: control processors in network infrastructure,
switch, and router products
Media Extensions c
• Consumer: digital TVs, set-top boxes, game consoles,
The ARMv6 instruction set provides media instructions to com-
and handheld digital media players
plement the DSP instructions. The media instructions are divided
into the following main groups:
• Additional multiplication instructions for handling 16-bit Core area, frequency range, and power consumption are
and 32-bit data, including dual-multiplication instructions dependent on process, libraries, and optimizations. The
that operate on both 16-bit halves of the source numbers quoted above are illustrative of synthesized cores
registers; this group includes an instruction that improves using general-purpose TSMC process technologies and
the performance and size of code for multi-word ARM Artisan standard-cell libraries and RAMs.
unsigned multiplications
• Instructions to perform Single Instruction Multiple Data choices and synthesis flow decisions and tradeoffs made
(SIMD) operations on pairs of 16-bit values held in a in order to achieve the target frequency performance. The
single register, or on quadruplets of 8-bit values held in a area-optimized implementations refer to the library choices
single register; the main operations supplied are addition and synthesis flow decisions and tradeoffs made in order to
and subtraction, selection, pack, and saturation achieve a target area density.
The cache sizes are specified as InstructionCache/DataCache.

The area without cache numbers quoted exclude RAM area,
but include all logic including memory management, cache
control, and debug. The area with cache numbers quoted
includes the core, the specified instruction and data caches,
and all necessary RAMs.
90 nm
Speed Optimized Area Optimized
Standard cells Advantage-HS Metro
Memories Advantage Metro
Frequency* (MHz) 620 320
Area with cache (mm2 ) 2.50 1.55
Area without cache (mm2 ) 1.80 0.90
Cache size 16K/16K 16K/16K
Power** with cache (mW/MHz) 0.45 0.24
Power** without cache (mW/MHz) 0.37 0.18
18 |
ARM Cortex-A8
Processors for Complex OS and User Applications
The ARM Cortex™-A8 processor is the first applications processor based on the ARMv7 architecture and is the highest
performance, most power-efficient processor ever developed by ARM. With the ability to scale in speed from 600 MHz to
greater than 1 GHz, the ARM Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing
operation in less than 300 mW and performance-optimized consumer applications requiring 2000 Dhrystone MIPS.
The ARM Cortex-A8 processor is ARM’s first superscalar processor featuring technology for enhanced code density and
performance, NEON™ technology for multimedia and signal processing, and Jazelle® RCT (Runtime Compilation Target)
technology for efficient support of ahead-of-time and just-in-time compilation of Java and other bytecode languages.
The exceptional speed and power efficiency of the Cortex-A8 DFT/Test Debug ETM
processor is enabled by new ARM Artisan® Advantage-CE

libraries supporting and implementing advanced leakage control.
The processor is supported by a wide range of ARM

technologies for rapid system design including: IFetch IDecode IExecute Load store
• The RealView® DEVELOP family of software

development tools I-side L1 Prefetch Decode & Dependency
Flags
ALU1
Load L1 cache D-side
L1 cache and sequencer check and store interface L1
• The RealView CREATE family of ESL tools and models RAM interface branch
prediction
issue RegBank
ALU2 RAM
• CoreSight™ debug and trace technology as well MAC

TLB TLB
as software library support through the OpenMAX
multimedia processing standard
• AMBA® 3 AXI high-performance SoC interconnect
Level 2 Instruction and Data DMA arbitration NEON unit
cache
NEON Issue and
instruction Decode forward NEON load
Architectural Features c L2 cache and preload engine queue control control data queue
CORTEX -A8
The ARM Cortex-A8 processor’s sophisticated pipeline NEON

Floating
NEON
Load
Fill and eviction queue Point Store
architecture is based on dual, symmetric, in-order issue, L2 cache
data RAM
L2 cache
tag RAM
NEON
RegBank
13-stage pipeline with advanced dynamic branch prediction BIU Write
buffer VFPLite NEON
Integer
achieving 2.0 DMIPS/MHz.

• The in-order, dual-issue, superscalar microprocessor
core includes:
– 13-stage main integer pipeline
– 10-stage NEON media pipeline AXI
– Dedicated Level 2 (L2) cache with programmable
wait states
– Global-history-based branch prediction
• The processor works in conjunction with a • The ARM Cortex-A8 is ARMv7 architecture-compliant
power-optimized load store pipeline to deliver 2.0 and includes:
DMIPS/MHz for power-sensitive applications – Thumb®-2 technology for greater performance, energy
efficiency, and code density
– NEON signal processing extensions to accelerate
media codecs such as H.264 and MP3
– Jazelle RCT Java-acceleration technology to optimize
Just In Time (JIT) and Dynamic Adaptive Compilation
(DAC), and to reduce memory footprint by up to
three times
– TrustZone technology for secure transactions and
Digital Rights Management (DRM)

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• Integrated L2 Cache: • Memory System:

– Built using standard compiled RAMs – Single-cycle load-use penalty for access to
– Configurable size from 64K-2 MB the L1 cache
– Programmable delay – Hash array in the L1 cache limits activation of the
memories to when they are likely to be needed
• Optimized Level 1 (L1) Cache: – Direct interface between the integrated, configurable
– Performance- and power-optimized L2 cache and the NEON media unit for data streaming
– Combines minimal access latency with hash way – Banked L2 cache design that enables only one bank
determination to maximize performance and minimize at a time
power consumption – Support for multiple outstanding transactions to the
Level 3 (L3) memory to fully utilize the CPU
• Dynamic Branch Prediction:
– Enabled by branch target and global-history buffers
– Achieves 95% accuracy across industry benchmarks
– Replay mechanism minimizes miss-predict penalty
65 nm
Speed Optimized
Frequency* (MHz) 600-800
Area with cache (mm2) <4
Area without cache (mm2) <3
Power with cache** (mW/MHz) < 0.5
*Core area, frequency range, and power consumption are dependent on process, libraries, and optimizations. The numbers quoted above are illustrative of synthesized cores using general-purpose TSMC process technologies and ARM Artisan
standard-cell libraries and RAMs.
Area is for core only (excluding NEON, Trace technology, and L2 cache). Frequency and power are for mobile applications. Frequency for consumer applications = 1 GHz. The speed-optimized implementations refer to the library choices and synthesis
flow decisions and tradeoffs made in order to achieve the target frequency performance. The area-optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.
**The 65 nm (LP) dynamic power measured is at 1.2V nominal and, hence, is higher than the 65 nm (GP) dynamic power, which is at 1.0V. However, the 65 nm (LP) leakage is significantly lower and this is the major consideration for mobile or
battery-operated devices that need to conserve power in standby mode.
20 |
ARM Cortex-M3
Processors Optimized for Cost-Sensitive and Deeply-Embedded Applications
The ARM CortexTM-M3 processor has been developed to provide a high-performance, low-cost platform that meets the
needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor executes purely Thumb®-2 instructions, delivering the high performance
expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a
few kilobytes of memory for microcontroller class applications.
In addition to minimizing its memory requirement, the ARM

Cortex-M3 processor is also the smallest 32-bit core designed
by ARM at just 33k gates for the central processing core Configurable ETM
(CM3Core) and 60k gates total, including many close system NVIC
peripherals. This design reduces silicon area requirements even ARM core
further, enabling the smallest of packages or the manufacturing
of devices on low-cost processes, such as 0.35 µM and
Memory Serial wire
0.25 µM. DAP protection unit viewer
Cortex-M3
The ARM Cortex-M3 processor also reduces the number of pins Data Flash
watchpoints patch
required for debug from five to one, by implementing a new
debug interface technology—Single Wire Debug—that can
replace the current multi-pin JTAG port. Bus Matrix
Code SRAM &

interface peripheral I/F
Outstanding Performance c
In addition to unparalleled performance, power consumption,
and memory utilization, the ARM Cortex-M3 processor also
achieves exceptional interrupt handling. By implementing the
register manipulations required for handling an interrupt in Enabling Technology c
hardware, this core achieves minimal clock overhead on entering The ARM Cortex-M3 processor has been designed “from
interrupts, and switches between pending or higher priority inter- the ground up” to provide optimal performance and power
rupts in only six cycles. The design, which comes with consumption within a minimal memory system. To achieve this,
32 interrupt channels as standard, can be configured to the core executes only the Thumb-2 instruction set, which
between 1 and over 240 channels. delivers an unparalleled combination of ARM instruction set
performance with industry-leading code density. The design,
which is based on a three-stage pipeline Harvard architecture,
The ARM Cortex-M3 processor also includes an optional also maximizes memory utilization through the support of
Memory Protection Unit (MPU) to provide a privileged mode unaligned date storage, and single-cycle atomic bit manipulation.
of operation for complex applications.
The exceptional performance of the ARM Cortex-M3 processor

is achieved through a highly revised architecture that also
implements many new technologies in this type of core, such
as hardware divide and single-cycle multiply.

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Benefits c Core area, frequency range, and power consumption are

The ARM Cortex-M3 processor offers significant benefits dependent on process, libraries, and optimizations. The
to system and software developers. numbers quoted above are illustrative of synthesized cores
using general-purpose TSMC process technologies and ARM
• Lower cost devices through smaller processing Artisan® standard-cell libraries and RAMs. Area numbers include
core, system, and memories the CM3Core, the Nested Vectored Interrupt Controller (NVIC),
• Ultra-low power consumption and integrated and Bus Matrix, but not the optional components including the
sleep modes Memory Protection Unit, Embedded Trace Macrocell, Breakpoint
Unit, Data Watchpoint Unit, and Trace Port Interface Unit.
• Outstanding processing performance for challenging
applications
• Fast interrupt handling for critical control applications
choices and synthesis flow decisions and tradeoffs made in
• Platform security with optional integrated memory order to achieve the target frequency performance. The
protection unit area-optimized implementations refer to the library choices
and synthesis flow decisions and tradeoffs made in order to
• Enhanced system debug for faster development achieve a target area density.
• No assembler code requirement to ease system

development
• Wide application envelope encompassing ultra-low-

cost microcontrollers and high-performance SoC
0.18 µ M 0.13 µ M
Speed Optimized Area Optimized Speed Optimized Area Optimized
Standard cells SAGE-X Metro SAGE-X Metro
Frequency* (MHz) 100 50 135 50
Area (mm2 ) 0.86 0.70 0.39 0.30
Power** (mW/MHz) 0.19 0.14 0.12 0.09
*Worst-case conditions—0.18 µm process—1.62V, 125˚C, slow silicon; 0.13 µm process—1.08V, 125˚C, slow silicon
**Typical-case conditions—0.18 µm process—1.8V, 25˚C, typical silicon; 0.13 µm process—1.2V, 25˚C, typical silicon
22 |
ARM Cortex-R4(F)
Embedded Processors for Real-Time Applications
The ARM Cortex™-R4 processor is the first deeply embedded processor to be based on the ARMv7 architecture and
is targeted at very high-volume, deeply embedded applications such as hard-disk drives, inkjet printers, and automotive
safety systems.
The ARM Cortex-R4 processor provides key savings in cost and power consumption for system developers, offering
substantially higher performance than any other processor with similar die size. Along with the ARM1156T2-S and ARM
Cortex-M3 processors, the ARM Cortex-R4 processor completes comprehensive coverage for the diverse needs of the
embedded microprocessor market. Furthermore, the ARM Cortex-R4 processor supports substantial synthesis time
configurability that enables designers to match the processor precisely to the application requirements.
In addition to the ARM Cortex-R4, ARM has introduced the

ARM Cortex-R4F, which contains a Floating Point Unit (FPU).
The ARM Cortex-R4F processor’s FPU performs floating-point
calculations that allow a greater dynamic range and accuracy Debug
VIC Port ETM Interface
than fixed-point calculations. The FPU is backward compatible Interface
with earlier ARM FPUs (VFP9/10/11), and is optimized for the
single-precision processing most commonly used in automotive
and control applications. The FPU is particularly useful in Prefetch
sophisticated control applications, where algorithms are often & Branch TCM
Prediction core Arbiter
modeled in an environment such as Simulink or ASCET-SD, Unit and
and code is auto-generated using tools such as Real Time Interface
FPU
Workshop Embedded Coder, ASCET-SE, or dSPACE Targetlink.
C o r t e x - R 4 (F)
F
Memory
The ARM Cortex-R4 processor is capable of running at clock Protection
speeds of up to 400 MHz on typical 90 nm processes, and the Instruction Unit FP exec 1 Data
Cache Cache
focus throughout the design is on efficiency and configurability.
AXI Master Interface AXI Slave Interface
Technical Innovations c
• Thumb®-2 technology; an innovation that has enabled
partners to combine the minimal memory footprint of
16-bit Thumb code with the high performance of 32-bit • CoreSight™ technology; a framework for complete
ARM code system debug and trace; this includes the ETM-R4
embedded trace macrocell and many other CoreSight
• AMBA 3 AXI protocol; a set of major enhancements to components
AMBA for high-performance on-chip interconnect, the
ARM Cortex-R4 processor integrates a 64-bit master port • A significantly improved local memory architecture
as well as a 64-bit DMA port for direct access to the for TCM and DMA; TCM can now be unified into a
Tightly Coupled Memories (TCM) single logical address space and can run as fast as
cache memory
• A selective superscalar eight-stage pipeline that
provides more than 1.6 DMIPS/MHz in an efficient low • Enhancements over the ARMv6 architecture include
gate count implementation improvements in interrupt handling and the memory
protection scheme; new instructions for managing
• Non-Maskable Interrupts (NMI); many real-time interrupts reduce the critical early-interrupt handler code,
applications demand this and the ARM Cortex-R4 and the worst-case interrupt latency is vastly improved to
supports a configurable NMI pin only 20 clock cycles
• Performance monitoring support; very useful for refining

and tuning a system through advanced profiling of the
system performance

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• Architected support for parity in the caches and parity or • Either one, two, or three TCM ports can be included
ECC in the TCMs; soft errors are an increasing concern in
embedded systems and either parity or ECC is now • A number of breakpoints and watchpoints can
essential in many systems be selected
• A very efficient branch prediction and prefetch unit • Dynamic Branch Prediction
provide a branch accuracy of more than 90% for - Enabled by branch target, global-history buffers,
typical C code and a function called return stack
- Achieves 90% accuracy across industry benchmarks
• The overall aim of the ARM Cortex-R4 processor is to
provide around 40% more efficiency than the ARM9 • Single-cycle load-use penalty for access to the L1 cache
family whilst increasing the maximum clock speed, and TCM
supporting the use of low-power, dense RAMs for
cache and TCMs, and delivering an efficient • A single 64-bit AXI master port for easy integration into
Thumb-2 engine the SoC interconnect
• An AXI slave port to allow direct access to TCMs by DMA

controllers and other processors in the system
Architectural Features c
• Vectored Interrupt Controller (VIC) port for fast
The ARM Cortex-R4 processor’s sophisticated pipeline connection to interrupt management peripherals
architecture is based on low-cost dual-issue pipeline, eight
stages with advanced dynamic branch prediction achieving
Core area, frequency range, and power consumption are
1.6 DMIPS/MHz; the ARM Cortex-R4 processor is fully
dependent on process, libraries, and optimizations. The
ARMv7 architecture-compliant and includes:
numbers quoted above are illustrative of synthesized cores
• Thumb-2 technology for greater performance, energy using general-purpose TSMC process technologies and ARM
efficiency, and code density Artisan standard cell libraries and RAMs.
• Hardware divide instructions for control applications The speed-optimized implementations refer to the library
choices and synthesis flow decisions and tradeoffs made in
• Optimized level-one caches and TCM order to achieve the target frequency performance. The
• Synthesis optional cache controllers (with optional cache area-optimized implementations refer to the library choices
parity) and TCM ports for flexibility and synthesis flow decisions and tradeoffs made in order to
achieve a target area density.
• Full wait and error support on TCM interfaces
The cache sizes are specified as InstructionCache/DataCache.
• Flexible configuration at synthesis time of major The area without cache numbers quoted exclude RAM area,
level-one features but include all logic including memory management, cache
control, and debug. The area with cache numbers quoted
• A Memory Protection Unit (MPU) can be removed or an includes the core, the specified instruction and data caches
eight- or 12-region one selected and all necessary RAMs.
0.13 µ M 90 nm
Area Optimized Speed Optimized Area Optimized
Standard cells SAGE-HS Advantage-HS Metro
Memories HS Advantage Metro
Frequency* (MHz) 300 500 210
Area with cache (mm2) 3.35 2.50 1.50
Area without cache (mm2 ) 1.99 1.66 0.80
Cache size 16K/16K 16K/16K 16K/16K
Power** with cache (mW/MHz) – 0.41 0.22
Power** without cache (mW/MHz) – 0.33 0.16
24 |
Intel XScale®
Designed to Enable High Performance, Low Power Consumption, and Systems Integration
The Intel XScale® core is based on an ARM processor family second-generation core and consists of innovative
custom circuits, a proprietary design, and proprietary process techniques. This unique core enables processors in the
Intel XScale® family to operate on very low current while in run and low-power modes.
Designed to enable high performance, low power consumption, and systems integration, the Intel XScale® core
empowers OEMs to develop smaller, more cost-effective, handheld devices with longer battery life, while providing the
performance to run MIPS-intensive multimedia applications such as audio encode/decode, video compression, and speech.
The Intel XScale® microarchitecture extends to set-top boxes, networking, intelligent I/O, and remote-access servers.
This unique processor engine design affords a substantial leadership position in the handheld device market segment
where high performance, low power, and integration-per-cost-effectiveness are all critical factors.
The Intel XScale® core targets the portable information device • Power management unit saves power with idle, sleep,
segment, which consists of feature-rich handheld devices such and quick wake-up modes
as (but not limited to) the following:
• 128-entry branch target buffer maintains pipeline
• Vertical application devices capacity with statistically correct branch choices
• Palm-size devices • 32 KB instruction cache achieves high performance and
low power consumption levels by keeping a local copy of
• Smart phones/3G+ multimedia phones
important instructions
• PC companions
• 2 KB data cache avoids “thrashing” of the data cache for
frequently changing data streams
The processor is also packaged in a “smaller footprint, lower
cost” version focused on handheld and portable applications, • 32-entry instruction memory management unit enables
and a “higher performance” version for the PC companion and logical-to-physical address translation, access
vertical application device segments. In addition to handheld permissions, and instruction-cache attributes
segments, the Intel XScale® core also provides a market entry
to tethered applications such as screen phones, low-end • Four entry fill and pend buffers obtain core efficiency by
set-top boxes, web terminals, and other Internet appliances. allowing non-blocking and “hit-under-miss” operation
with data caches
• Performance monitoring unit analyzes hit rates with two

32-bit event counters and one 32-bit cycle counter
Features and Benefits of Intel XScale ®
Microarchitecture c • Debug unit debugs programs with hardware

• Superpipelined RISC technology achieves high speed breakpoints and a 256-entry trace-history buffer
and ultra-low power with a seven-stage integer/eight- (for flow change messages)
stage memory superpipelined core
• 32-bit coprocessor interface achieves a
• Dynamic voltage management obtains the right blend high-performance interface between the core
of performance and power with dynamic voltage and and coprocessors
frequency scaling “on the fly”
• 64-bit core memory bus with simultaneous 32-bit input
• Media processing technology achieves efficient media path and 32-bit output path obtains up to 4.8 GBytes/sec
processing with a multiply-accumulate coprocessor that @ 600 MHz bandwidth for internal accesses
performs two simultaneous 16-bit SIMD multiplies with
40-bit accumulation • Eight-entry write buffer provides continuous core
execution while data is written to memory
• The Thumb instruction set supported selects the

16-bit Thumb instruction set from the current program
status register

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ARM Architecture Compatibility c • Additional functionality has been added to coprocessor

15; coprocessor 14 also added
The Intel XScale® microarchitecture implements the integer
instruction set architecture specified in ARM Version 5TE. • Enhancements were made to the event architecture,
“T” refers to the Thumb instruction set, and “E” refers to the instruction cache, and data-cache parity
DSP-enhanced instruction set.
ARM Version 5 introduces a few more architecture features over
Version 4, specifically the addition of tiny pages (1 Kbyte), a new DSP Coprocessor 0 (CP0) c
instruction (CLZ) that counts the leading zeroes in a data value, ®
The Intel XScale microarchitecture adds a DSP coprocessor
enhanced ARM-Thumb transfer instructions, and a modification to the architecture for increasing the performance and the
of the system-control coprocessor, CP15. precision of audio-processing algorithms. This coprocessor
contains a 40-bit accumulator and eight new instructions.
The 40-bit accumulator is referenced by several new instructions
ARM DSP-Enhanced Instruction Set c
that were added to the architecture; MIA, MIAPH, and MIAxy
The Intel XScale® microarchitecture implements the ARM are multiply/accumulate instructions that reference the 40-bit
DSP-enhanced instruction set, which is a set of instructions accumulator instead of a register-specified accumulator. MAR
that boosts the performance of signal-processing applications. and MRA read and write the 40-bit accumulator.
New multiply instructions operate on 16-bit data values, and
Access to CP0 is always allowed in all processor modes when
new saturation instructions are available as well (see below).
bit 0 of the coprocessor access register is set. Any access to
• SMLAxy instruction is a 16x16+32 with a 32-bit result CP0 when this bit is clear will cause an undefined exception.
Note that only privileged software can set this bit in the
• SMLAWy instruction is a 32x16+32 with a 32-bit result
coprocessor access register. Two new instruction formats
• SMLALxy instruction is a 16x16+64 with a 64-bit result were added for coprocessor 0: multiply with internal
accumulate format, and internal accumulate access format.
• SMULxy instruction is a 16x16 with a 32-bit result
• SMULWy instruction is a 32x16 with a 32-bit result

Branch Prediction c
• QADD adds two registers and saturates the result if an ®
The Intel XScale microarchitecture implements dynamic
overflow has occurred
branch prediction for the ARM instructions B and BL, and for
• QDADD doubles and saturates one of the input registers the Thumb instruction, B. Any instruction that specifies the
and then adds and saturates the result PC as the destination is predicted as “not taken.” For example,
an LDR or an MOV that loads or moves directly to the PC will
• QSUB subtracts two registers and saturates the result if be predicted “not taken” and incur a branch-latency penalty.
an overflow has occurred
These instructions (ARM B, ARM BL, and Thumb B) enter into
• QDSUB doubles and saturates one of the input registers the branch target buffer when they are “taken” for the first time.
and then subtracts and saturates the result (A “taken” branch refers to when they are evaluated to be true.)
Once in the branch target buffer, the Intel XScale®
microarchitecture dynamically predicts the outcome of these
Extensions to ARM Architecture c instructions based on previous outcomes. A penalty of “zero”
®
for correct prediction means that the Intel XScale®
The Intel XScale microarchitecture includes a few extensions to
microarchitecture can execute the next instruction in the
the ARM Version 5 architecture to meet the needs of various
program flow in the cycle following the branch.
markets and design requirements. The following is a list of the
extensions that are discussed in the next subsections.
• A DSP coprocessor (CP0) has been added that contains
Power Management c
a 40-bit accumulator and eight new instructions
®
The Intel XScale microarchitecture defines three low-power
• New page attributes were added to the page table modes: idle, drowsy, and sleep. All state information is lost on
descriptors; the C- and B-page attribute encoding entering sleep mode. The only way to exit sleep mode is through
was extended by one additional bit to allow for the reset sequence. State is retained in idle and drowsy modes.
more encodings: write-allocate and mini-data
Both idle and drowsy modes are exited by interrupt, even if the
cache; an attribute specifying ECC for 1 MB regions
interrupt is masked. A single coprocessor 14 register write is
was also added
used to enter any low-power mode.
34 |
i.MX31 Multimedia Applications Processors

Core: ARM1136JF-S™
The popular i.MX31 and i.MX31L multimedia applications processors are developed
with Freescale’s Smart Speed Technology to drive high performance applications at
very low power for extended battery life. The entire portfolio of i.MX processors offers
a range of performance and price levels, on chip integration, and broad connectivity
options. i.MX processors also have one of the best power-to-performance ratios of
any processor in their class. They are becoming the applications processors of choice
for portable media players, smartphones, automotive infotainment systems, V2IP
phones, video surveillance systems, and many other devices. Freescale provides
board support packages (BSPs) to simplify and support development on leading
operating systems and RTOSes. Freescale is a Gold-level Microsoft Windows
Embedded Partner and offers BSPs for the three most recent Windows CE releases (4.2, 5.0, 6.0) Windows Mobile
5.0 and the new Windows Mobile 6. The i.MX portfolio continues to grow, and new processors will be shipping in
production this year.
Features c i.MX31 Block Diagram

• CPU complex with L2 cache, vector floating point co-processor,
and Smart Speed switch
• Smart power management including support for multiple low power
modes, dynamic voltage frequency scaling, and dynamic process
temperature compensation
• External memory interface with support for multiple
types of memory
• Smart multimedia with support for hardware accelerated MPEG4
encode, as well as pre & post processing
• Display port with ability to support a variety of popular display
devices and up to two displays simultaneously
• Sensor port which provides connection to either one or
two image sensors
• System connectivity, including USB high speed OTG, CSPIs,
I2C, PCMCIA, ATA, UARTs
• 2D/3D graphics acceleration (only available on i.MX31)
• Board support packages for the major operating systems
Benefits c
• High performance with 32-bit DDR and L2 cache
• Long battery life for mobile applications
• Ability to boot from NAND flash
• MPEG4 playback at 30 fps VGA resolution
• Interactive console-like gaming experience with OpenGL-ES based
graphics acceleration
• On chip LCDC eliminates the need for timing chips when using
certain displays
• Capture, process, and display of moving and still objects
• High level of integration simplifies overall board design and
lowers BOM cost

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | XS c a l e | A R M 1 1 | C o r t e x - A 8
Family Comparative Features c
Part Temp °C Package Core Max Timer Timer Serial Interface USB Peripherals
Number Type Variant ID Frequency Channels Bits Description
MCIMX31VKN5B 0 to +70 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator,
sensor port, 2D/3D graphics accelerator
MCIMX31LVKN5B 0 to +70 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port
MCIMX31CVKN5C -40 to +85 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator,
sensor port, 2D/3D graphics accelerator
MCIMX31LCVKN5C -40 to +85 MAPBGA 457 ARM1136JF-S 532 2 32 3/I2C; 2/SSI/I2S; 3 CSPI; 2.0 high speed OTG + 2 hosts 5 UARTs/1 Fast IR, 1/1-wire I/F, LCD controller, multimedia accelerator, sensor port
Development Tools Matrix c

Tool Name Description Part Number
i.MX31 ADS Complete hardware development system with power management board and included features such as LCD, camera, and board support packages MCIMX31ADSE
i.MX31 Lite Kit Low-cost development kit for basic evaluation and application development; peripheral accessories and software available separately MCIMX31LITEKIT
i.MX31 Lite Kit i.MX31 Application Development System
For more information on Arrow’s ARM solutions, pricing, and availability, visit www.arrownac.com/arm or call 1-866-910-3650.
To research and compare and contrast ARM solutions, visit www.embedded-developer.com.
i.MX31 Multimedia Applications Processors | Freescale Semiconductor
36 |
Intel ® Network Processors and Intel ® I/O Processors

Core: Intel XScale® Technology
Intel XScale® Technology is available in two families: The Intel® network processors family
and the Intel® I/O processors family of devices. With a single architecture and integrated
design, the Intel® IXP4XX product line of network processors delivers scalable performance,
reduced power, and lower cost in packages optimized for residential and small/medium
enterprise network applications, as well as communications-based embedded applications.
Many storage, networking, and embedded applications require fast I/O throughput for
optimal performance. Intel® I/O processors (IOP) allow applications to transfer data faster,
reduce communication bottlenecks, and improve overall system performance.
Features c Intel ® IXP46X Product Line Block Diagram

• Intel XScale® Microarchitecture running at up to 667 MHz
HSS-0
HSS-1
• Intel® network processors: Peripherals - USB, up to 3 10/100
NPEA
Ethernet MACs, PCI, DDR, Expansion Bus, UARTs, I2C, SSP UTOPIA-2/MII/SMII
MII/SMII
UTOPIA, AAL,
• Intel® network processors: Advanced Serial Interfaces including HSS, HDLC

133.32 MHz Advanced High-Performance Bus
NPE B Queue Flag Bus

a high speed serial port for connecting to T1/E1 or MII/Quad SMII 1 MII or
Quad SMII Cryptography Unit Queue Manager
EAI, SHA
SLICs/CODECs; UTOPIA-2 Support; NPE C HW RNG
8KB SRAM
MII/SMII
• Intel® network processors: Integrated support for cryptography, MII/SMII AES, DES
SHA-1/-256/
DDR1-266
Controller
32-bit +
ECC
PMU IEEE Interrupt -384/-512, MO5
time synchronization and ECC memory (AHB) 1588 Controller
Timers Bridge
Memory Port Interface

• Intel® I/O processors: Integrated Designs 66.66 MHz Advanced Peripheral Bus Bridge 133.32 MHz Advanced High-Performance Bus
• Intel® I/O processors: I/O Processing Performance Bus Interface Unit

UART UART GPIO USB USB PCI Expansion Bus
I2C
• Comprehensive Set of Development Tools 921KBaud 921KBaud Controller SSP Device v1.1 Host 2.0** Controller Controller Intel XScale® Core
266/400/533/667 MHz
32 KB Data Cache
32 KB Instruction Cache
16 GPIO
Parity
32-bit +
32-bit
2 KB Mini-Data Cache
Benefits c **USB 2.0 Host supports low-speed (1.5 Mb/s) and full-speed (12 Mb/s) modes.
• Intel’s groundbreaking new microarchitecture provides very high

processor performance with extremely low power consumption;
Intel XScale® technology provides the platform for the most
advanced designs in storage, infrastructure and embedded
communications
• Provides reduced overall system cost as well as ease of
connectivity to industry standard peripherals/devices
• Support for voice applications and connection to industry standard
WAN interface
• Improves performance and reliability
• I/O processors are available in single- or dual-chip configurations
this provides developers with pre-validated component sets,
simplified board designs, and board-space cost savings
• Offloads I/O processing functions, such as I/O interrupt processing
and parity calculations from a host processor; I/O processors are
also excellent general-purpose processors for high-bandwidth
applications that require integrated processors with low power
consumption and high-speed peripherals
• Faster time-to-market and support for multiple tool-chains and
operating systems on the Intel XScale® microarchitecture

1-866-910-3650
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AR M7 | Cortex-M3 | AR M9 | Cortex-R4 | XScale | AR M11 | Cortex-A8

Part Total Temp °C Package Core M a x A/D A/D Timer Timer Serial Interface GPIO Ethernet USB Peripherals
Number RAM Type Variant ID Frequency Bits Channels Channels Bits Description
IXP43X eternal up to 1 GB -0 to +70 PBGA XScale 667 0 – 4 32 High Speed UART, SSP/SSI, I2C 16 2 x 10/100 2x2.0 HS Host DDR I/II, 32-bit 33 MHz PCI, 16-bit Expansion Bus, UTOPIA 2,
DES/3DES/AES/SHA 1/SHA256/384/512, IEEE 1588
IXP42X eternal up to 256 MB -40 to +85 PBGA XScale 533 0 – 4 32 2 High Speed UARTs 16 2 x 10/100 1x1.1 Device SDRAM, 32-bit 33 MHz PCI, 16-bit Expansion Bus,
SHA-1/MD5/ES/DES,/AES
80219 eternal up to 1 GB 0 to +55 FCBGA5 XScale 800 0 0 3 32 2xI2C 8 – – PCI, DDR
IOP331/2 eternal up to 2 GB 0 to +95 FCBGA5 XScale 800 0 – 3 32 2xUARTs, 3xI2C 8 – – PCI-X/PCIe, DDRII, 266 MHz 64-bit internal bus
IOP333 eternal up to 2 GB 0 to +95 FCBGA5 XScale 800 0 – 3 32 2xUARTs, 3xI2C 16 – – PCI-X/PCIe, DDRII, 333 MHz 64-bit internal bus
2
IOP348 eternal up to 2 GB 0 to +95 FCBGA5 XScale 1200 0 0 3 32 2xUARTs, 3xI C 16 – – PCI, PCIe, SAS/SATAII, DDII
IOP341/2 eternal up to 2 GB 0 to +95 FCBGA5 XScale 1200 0 – 3 32 2xUARTs, 3xI2C 16 – – PCI-X/PCIe, 1 or two XScale processor cores, DDRII, 400 MHz
128-bit internal bus
IXP46X eternal up to 1 GB -40 to +85 PBGA XScale 667 0 – 4 32 2 High Speed UARTs 16 3 x 10/100 1.1 Device, 2.0 DDR I, 32-bit 33 MHz PCI, 32-bit Expansion Bus, FS Host
SSP/SSI, I2C UTOPIA 2, DES/3DES/AES/SHA1/ SHA256/384/512, IEEE 1588

Intel® IXDP465 Development Platform Intel® IXDP465 Development Platform, optional T1/E1, Voice, and Ethernet Modules; includes 4 PCI expansion slots, 3 Ethernet ports, USB host and device, 2 UARTS KIXDP465AD
® ® ® ®
Intel IXDP425 / IXCDP1100 Development Platform Intel IXDP425 / IXCDP1100 Development Platform, Network processor base card with the Intel IXP425 network processor at 533 MHz, Two Intel LXT972A LAN PHY expansion cards, KIXDP425BD
One ADSL PHY expansion card, One voltage regulator expansion card, Two High-Speed Serial (HSS) ports, Two UART (DB-9) connectors, One USB connector, Four PCI bus connectors
Intel® KIXRP435 Development Platform Intel® KIXRP435 Development Platform Includes 10/100 802.11a/g WLAN, 3x10/100 Ethernet, 2 Wideband FXS + 1 FXO, 2xUSB 2.0, UART, IR, RCA, Audio, Component Video, S-Video KIXRP435 - Hamoa
Intel® IQ80332 Software Development Features Intel® 82545EM Gigabit Ethernet Controller, Primary PCI- PCI Express* supports up to x8 lane, Secondary PCI is PCI-X, two UARTs, Two 7-segment hex LED displays in a dPCI IQ80332
and Processor Evaluation Kit Express form factor
Intel® IQ80219 Development Kit Intel® IQ80219 Development Kit featuring a primary PCI-X interface 133 MHz/64-bit or PCI 66 MHz/64-bit, Two Intel® 31244 Serial ATA I/O controllers, Intel® BW31154 PCI 133 MHz IQ80219.DOM
transparent bridge,256MB DDR SDRAM with ECC, one PCI-X 64-bit/100 MHz expansion slot
Intel® EP80219 Development Intel® EP80219 Development Kit features a 10/100 Ethernet controller, one GD31244 SATA controller, a serial port, and a mini-PCI connector for expansion, RTC, Power control, EP80219
and Temp Sensor
The IQ81342MC board features a 1.2GHZ two core Intel®

IOP342 I/O processors processor. This board has dual UARTs,
Dual Gbit Ethernet and a x8 PCI Express slot and a 64-bit PCI-X
slot for expansion, and fits in a standard flex-ATX chassis.
Intel, the Intel logo, and Intel XScale are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries. *Other names and brands may be claimed as the
property of others. Intel® Network Processors and Intel® I/O Processors | Intel®
40 |
LPC210x 70 MHz, 32-bit microcontroller with

ARM7TDMI-S
Core: ARM7TDMI-S
These powerful yet cost-effective microcontrollers have up to 32 KB of zero

wait-state Flash and up to 8 KB of SRAM. Each has a 10-bit A/D converter with
eight channels and multiple serial interfaces.
The lowest-priced part, the LPC2101, starts at only USD $1.47 each for 10 Kpcs,
making it an attractive alternative to lower performing 8- or 16-bit MCUs. Blending
high performance (63 Dhrystone MIPs) with low power consumption in a tiny 7 mm x 7 mm LQFP48 package makes the
part ideal for almost any application.
These cost-effective processors are stuffed with a variety of peripherals, including 10-bit ADCs, 4 timers, and multiple
I2C, SPI, and UART interfaces. The series also features several new power-saving modes and fast general-purpose I/O,
allowing more flexibility for designers. The code and peripherals are fully compatible with all of the other members of
the NXP LPC2000 family, which has nearly 40 members and continues to grow.
Features c LPC210x Block Diagram

• 70-MHz, 32-bit ARM7 Core Architecture with AHB/APB interfaces
• Up to 32 KB of zero wait-state Flash
• Fast 70 MHz performance at 63 Dhrystone MIPs
• Tiny 7mm x 7mm LQFP packaging
• Stuffed with low-power features and advanced peripherals
• Incredibly low pricing starting at $1.47
Benefits c
• Ideal upgrade for any application using lower performance
8- or 16-bit MCUs
• Ideal for almost any application
• Design flexibility

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | Xs c a l e | A R M 1 1 | C o r t e x - A 8
Part Total Total Temp. °C Package Core Max A/D A/D Timer Timer Serial Interface GPIO Ethernet USB Peripherals
Number Flash RAM Type Variant ID Frequency Bits Channels Channels Bits Description
LPC2101 8 2 -40 to +85 LQFP48 ARM7TDMI-S 70 10 8 7 32 2xUART, SPI, SSP 32 – – –

MCB2103 evaluation board from Keil The evaluation board connects to your PC using the serial port (for flash download with the NXP LPC2000 FLASH Utility) or the JTAG interface; it can be powered from a USB connector MCB2103
(50mA typical) or from a 5V to 9V DC power supply; debugging is supported via the JTAG interface using the Keil ULINK USB-JTAG adapter and the _Vision IDE and Debugger
MCB2103 Keil Evaluation Board
NXP Family of Microcontrollers | NXP
42 |
LPC23xx and LPC24xx 72 MHz, 32-bit

microcontrollers with ARM7TDMI-S core
Core: ARM7TDMI-S
The LPC23xx and LPC24xx use a high-performance 32-bit ARM7 core that operates
at up to 72 MHz. Each device has 512 KB of on-chip Flash. The LPC23xx offers up
to 58 KB of SRAM, while the LPC24xx offers up to 98 KB of SRAM. Both devices
have two AHB buses, so high-bandwidth peripherals like Ethernet and USB can run
simultaneously, without impacting the main application. The LPC24xx is also the only
ARM7 MCU with two-port USB capability; it has one USB device, and one USB
Host or OTG. This unique ability enables new advances for multiple communications applications by supporting com-
pound (Host + device) USB functionality, such as a USB mini-hub.
Features c LPC24xx Block Diagram

• On-chip RC-oscillator 4 Mhz trimmed to 1%
• Four 32-bit general purpose timers
• PWM block supporting 3-Phase Motor Control
• Watchdog timer from multiple clock source options
• 10-bit A/D converter and 10-bit D/A converter
• Low-power Real Time Clock with 2 KB SRAM and
battery back-up
• General Purpose DMA controller
• High-speed Serial: I2S (digital Audio), three I2C,
three SPI/SSP, four UARTs
Benefits c
• Allows fast simultaneous communications operations
• Eliminates communication bandwidth bottlenecks
• Design flexibility

1-866-910-3650
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Part Total Total Temp.°C Package Core Max A/D A/D Timer Timer Serial Interface GPIO Ethernet USB Peripherals
LPC2468FET208 512 98 -40 to +85 TFBGA208 ARM7TDMI-S 72 10 8 4 32 2xSSP, I2S, 4xUART, 3xI2C – 10/100 2.0 FS, OTG 2xCAN
2 2
LPC2468FBD208 512 98 -40 to +85 LQFP208 ARM7TDMI-S 72 10 8 4 32 2xSSP, I S, 4xUART, 3xI C – 10/100 2.0 FS, OTG 2xCAN
2 2
LPC2378FBD144 512 58 -40 to +85 LQFP144 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I S, 4xUART, 3xI C – 10/100 2.0 FS, OTG 2xCAN
2 2
LPC2368FBD100 512 58 -40 to +85 LQFP100 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I S, 4xUART, 3xI C 70 10/100 2.0 FS, OTG 2xCAN
2 2
LPC2366FBD100 256 58 -40 to +85 LQFP100 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I S, 4xUART, 3xI C 70 10/100 2.0 high speed OTG + 2 hosts 2xCAN
2 2
LPC2364FBD100 128 34 -40 to +85 LQFP100 ARM7TDMI-S 72 10 8 4 32 SPI, 2xSSP, I S, 4xUART, 3xI C 70 10/100 2.0 high speed OTG + 2 hosts 2xCAN

Keil MCB2300 Evaluation Boards The Keil MCB2300 Evaluation Boards introduce you to the NXP LPC23xx series of ARM microcontrollers and allow you to create and test working programs for this advanced architecture; MCB2300
two versions of the board are available: the MCB2360 for the 100-pin LPC2368 and the MCB2370 for 144-pin LPC2378
Keil RealView Microcontroller Development Kit The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard compilation MDK-ARM
tools and sophisticated debugging support
Keil ULINK2 The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target hardware; ULINK2
ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works with standard
Windows USB drivers
44 |
LPC2478 72 MHz, 32-bit ARM-based microcontroller

with integrated LCD support
Core: ARM7TDMI-S
These innovative and cost-effective microcontrollers support concurrent operations
of high-bandwidth peripherals with significant power savings. The large array of
peripherals supported by these devices in addition to the LCD interface include
10/100 Ethernet, USB host/OTG/device, two CAN channels, four UARTs, three
I2C buses, two-input and two-output I2S, SPI, SSP, RTC, ADC/DAC, SD/MMC
card interface, external interfaces to SRAM, SDRAM and NOR Flash.
The LPC2478 microcontroller is the industry’s only ARM7 Flash-based MCU offering integrated LCD support as well
as a Flashless version, the LPC2470.
Features c LPC247x Block Diagram

• 72-MHz, 32-bit ARM7 core with dual AHB interfaces
• 512 KB of fast 128-bit wide embedded Flash (LPC2478 only)
• LCD interface
• 10/100 Ethernet MAC interface with DMA
• USB 2.0 full-speed OTG/Device/OHCI plus PHY and DMA
• Two CAN 2.0B controllers with acceptance filtering
• External interfaces to SRAM, SDRAM, and NOR Flash
• 10-bit A/D converter and 10-bit D/A converter
Benefits c
• Significant savings in cost, area, and power consumption
• Ideal for a wide range of industrial, consumer, retail and
medical systems using LCD panels and requiring network
or Internet connectivity
• LCD implementation allows code execution on-chip

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LPC2470FBD208 0 98 -40 to +85 LQFP208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA,
2.0/OTG SPI, 2xSSP, 3xI2C, I2S USB 2.0/OTG w/PHY and DMA, SD/MMC
LPC2470FET208 0 98 -40 to +85 TFBGA208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA,
SPI, 2xSSP, 3xI2C, I2S USB 2.0/OTG w/PHY and DMA, SD/MMC
LPC2478FBD208 512 98 -40 to +85 LQFP208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA,
LPC2478FET208 512 98 -40 to +85 TFBGA208 ARM7TDMI 72 10 8 4 32 4xUART(1xIrDA), 2xCAN, 160 1 1 LCD (1024x768), 10/100 with MII/RMII and DMA,

Keil RealView Microcontroller Development Kit The RealView Microcontroller Development Kit (MDK) supports the LPC24xx family of microcontrollers from NXP; this kit is perfect for the developer who requires industry-standard MDK-ARM
compilation tools and sophisticated debugging support
Keil ULINK2 The Keil ULINK2 USB-JTAG Adapter connects your PC's USB port to your target hardware (via JTAG, SWD, or OCDS) and allows you to debug embedded programs running on target ULINK2
hardware; ULINK2 offers all the features of the original ULINK USB-JTAG Adapter and adds serial wire debug (SWD) support, return clock support, and a real-time agent; ULINK2 works
with standard Windows USB drivers
46 |
STR7 and STR9 Families

Core: ARM7TDMI, ARM966E-S
STMicroelectronics brings the power of 32-bit ARM® processor cores to the world
of microcontrollers, opening endless opportunities to embedded system designers
by making control and connectivity applications easy and affordable. With a wide
range of embedded memories, peripherals and architectural enhancements, ST's
STR7 and STR9 families help scale designs to achieve the best fit for an applica-
tion. STR7 and STR9 families address needs, from low-end to high-performance,
with a common set of tools and software, thus reducing cost and time to market.
Features c STR750 ARM7

• Performance up to 54 MIPs @ 60 MHz, 3.0 to 3.6V or 4.5 to 5.5V,
STR710 ARM7
and -40 to +85°C, or up to +105°C
• Performance up to 45 MIPs @ 50 MHz, 3.0 to 3.6V,
• The best integration and balanced control/communication
and -40 to +85°C
• Safety and low power
• STR7’s biggest RAM (64 KB)
• Unique motor control peripherals
• The most UARTs (4)
• Suitable for many general-purpose applications
• External memory interface
• Peripherals include CAN, USB, 3xUARTs, and advanced timers
• Peripherals include CAN, USB, 4xUARTs,
• General-purpose and vector drive applications
and SC interface (ISO7816)
• Consumer and industrial applications
STR910 ARM9E
• Performance up to 96 MIPs @ 96 MHz, 2.7 to 3.6V I/O,
STR730 ARM7
1.8V core, and -40 to +85°C
• Performance up to 32 MIPs @ 36 MHz, 4.5 to 5.5V,
• Highest performance (96 MHz ARM9E)
and -40 to +85°C, or up to +105°C
• Largest Flash/RAM memory size (544 KB/96 KB)
• The most timers (20)
• Ethernet connectivity
• The most CANs (3), UARTs (4), and the most I/Os (112)
• Designed to complement STR7 for bigger memory, higher
• Peripherals include 3xCANs, 4xUARTs, and up to 20 timers, 16 DMA
performance and Ethernet connectivity
• Industrial and automotive related applications
• Binary compatible with ARM7TDMI core code
• Peripherals include Ethernet, USB, CAN, and 3xUARTs
• Performance and connectivity applications
STR7 and STR9 Portfolio Diagram

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STR730F
Core: ARM7TDMI
STR730F Flash microcontrollers combine the industry standard ARM7TDMI® RISC

microprocessor with embedded Flash and powerful peripheral functions, including
up to 20 timers, 4xUARTs and 3xCANs. The STR730F MCUs are ideal for embedded
applications requiring a compact yet powerful MCU, as well as versatile, scalable
solutions such as user interfaces, factory automation systems and appliances.
Additionally, the STR730F family features a single 5V power supply particularly
suited to industrial applications.
Features c STR730F Block Diagram

• Largest choice of peripherals and interfaces including
4xUART, up to 20 timers and up to 3xCAN
• Flexible power and clock management
• Five low-power modes
• Low-power voltage regulator
• Extensive software and tools including the complete
STR7 library supporting all standard peripherals and CAN
• Dual APB buses architecture
• Single 5V power supply
• 16-channel DMA
Benefits c
• Reduces system cost with all peripherals in one chip
• Full control over your power consumption
and performance/power tradeoffs
• Precisely manage low-power vs. performance
• Built-in voltage regulator means fewer external components
• Software library dramatically reduces development time and
increases ease-of-use
• Increased overall performance due to dual buses
• Native 5V supply of industrial applications; no 3.3V
conversion needed
• DMA lowers CPU load, optimized access to memory
STR730F Family of Microcontrollers | STMicroelectronics
48 |
STR710F
Core: ARM7TDMI
The STR710F series is loaded with many communication interfaces including USB,
CAN, ISO7816 and four UARTs. It is endowed with the biggest RAM of all STR7
MCUs (up to 64 KB) and implements an optional external memory interface. This
makes it a perfect fit for consumer, point of sales and high-end industrial applications.
The STR710F also features high performance, very low power, and very dense code,
and ST's latest 0.18µ embedded Flash technology.
Features c STR710F Series Block Diagram

• Largest choice of peripherals and interfaces, including
USB and CAN
• Flexible power and clock management
• Superior RAM/FLASH ratio
• High-quality embedded Flash with 16 K extra Flash for
EE emulation (20 year retention at 85°C)
• Extensive package options including the space efficient
8x8 LFBGA64 and 10x10 LFBGA 144
• Extensive software and tool support including the complete
STR7 library for USB
Benefits c
• Reduces system cost with all peripherals on one chip
• Allows full control over power consumption and
performance/power tradeoffs
• Unlimited possibilities - up to 64 K RAM, and always above
16 K even with smallest Flash option
• 16 K extra Flash reduces system cost with no need for
external EEPROM
• Software and tools support dramatically reduces development time
and increases ease-of-use

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AR M7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | XS c a l e | A R M 1 1 | C o r t e x - A 8
STR710FZ1 144 32 -40 to +85 BGA144, LQFP144 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, CAN, SC 48 — Device 2.0 EMI
STR710FZ2 272 64 -40 to +85 BGA144, LQFP144 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, CAN, SC 48 — Device 2.0 EMI
STR711FR0 80 16 -40 to +85 BGA64, LQFP64 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, SC 30 — Device 2.0 —
STR712FR0 80 16 -40 to +85 BGA64, LQFP64 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, CAN, SC 32 — — —
STR715FR0 80 16 -40 to +85 BGA64, LQFP64 ARM7TDMI 66 12 4 4 16 4xUART, 2xSPI, 2xI2C, SC 32 — — —

REva Starter Kit - Raisonance The REva starter kit from Raisonance is a cost-effective and complete solution for evaluating and starting application development STR71X-SK/RAIS
IAR KickStart Kit™ with STR711 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware STR711-SK/IAR
and software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface for
application board connection; with STR711 target MCU
IAR KickStart Kit™ with STR712 IAR KickStart Kits™ are cost effective and complete evaluation and development systems in a single package; they are designed to help you to a flying start by providing all the necessary hardware STR712-SK/IAR
and software you need to design, implement and test your STR7 application; includes J-Link: In-circuit debugger/programmer, featuring USB host interface and industry standard JTAG interface for
application board connection; with STR712 target MCU
Hitex Starter Kit The Hitex Starter Kit for STR7 is a complete solution for evaluating and starting application development with ST ARM core-based microcontrollers; includes: application board; Tantino, in-circuit STR710-SK/HIT
debugger/programmer, featuring USB host interface and industry standard JTAG interface; HiTOP5, 16K code-size limited version of Hitex’s full-featured Integrated Development Environment;
plus GNU C/C++ Compiler
Keil STR710 kit The Keil starter kit, available from Keil, is a complete solution for evaluating and starting application development with the STR7; the package includes: application board with user LEDs, push buttons, STR710 kit
switches, potentiometer and interfaces for device specific peripherals; ULink, in-circuit debugger/programmer; uVision3, the full-featured Integrated Development Environment; RealView Compilation Tools,
16K code-size limited version of the optimizing C/C++ compiler
STR710F Series IAR, Raisonance, & Hitex Starter Kits
50 |
STR750F
Core: ARM7TDMI
The STR750F microcontrollers are the latest series in the STR7 family. These MCUs bring the
best integration with a balanced peripheral set, USB, CAN, and key innovations like clock failure
detection and advanced motor control timers. The STR750F supports either 3.3V or 5V systems,
and it is also available in an extended temperature range (-40°C to +105°C). This makes it a
genuine general purpose microcontroller, suitable for a wide range of applications such as
appliance, brushless motor drive, USB peripheral, UPS, alarm systems, programmable logic
controller, circuit breakers, inverters, and medical and portable equipment.

• Excellent low power performance through flexible clock
management and multiple low power modes with consumption
down to 10 µA in standby mode
• Innovative backup clock
• Fast startup and wakeup
• Auto wake-up
• Serial memory interface (SMI) and LIN support
• Single supply, 3.3V or 5V (3.3V for USB)
• Powerful timers and fast ADC
• Extensive firmware support and tools; the STR750F
library is freely distributed by ST
Benefits c
• Easy adjustment of performance/power consumption ratio;
suitable for battery operated applications
• Additional security due to backup clock
• Fast startup and wakeup adds responsiveness
• Auto wakeup improve power-savings
• Less external hardware needed
• 3.3V or 5V supply gives additional flexibility for customers;
no need for external regulator; real 5V drive on the I/Os
when 5V is used
• Perfect fit for tri-phase motor control applications
• Extensive library dramatically reduces development time
and increases ease of use

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A R M 7 | C o r t e x - M 3 | A R M 9 | C o r t e x - R 4 | Xs c a l e | A R M 1 1 | C o r t e x - A 8
Part To ta l To ta l Temp. °C Pa ckage Core Max. A/D A/D Timer Timer Serial Interface G PIO Ethernet US B Pe ripherals
Number Flash RAM Type Va riant ID Frequency Bits Channels Channels Bits Description
STR755FR0 80 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – – RTC, Motor Control
STR752FR0 80 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C, CAN 38 – – RTC, Motor Control
STR751FR1 144 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – Device 2.0 RTC, Motor Control
STR752FR1 144 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C, CAN 38 – – RTC, Motor Control
STR755FR1 144 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – – RTC, Motor Control
STR751FR2 272 16 -40 to +85 LQFP64, BGA64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – Device 2.0 RTC, Motor Control
STR752FR2 272 16 -40 to +85 LQFP64, BGA64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C, CAN 38 – – RTC, Motor Control
STR751FR0 80 16 -40 to +85 LQFP64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART 38 – Device 2.0 RTC, Motor Control
STR755FV2 272 16 -40 to +85 LQFP100, BGA100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C 72 – – RTC, Motor Control
STR750FV2 272 16 -40 to +85 LQFP100, BGA100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C, CAN 72 – Device 2.0 RTC, Motor Control
STR750FV1 144 16 -40 to +85 LQFP100, BGA100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C, CAN 72 – Device 2.0 RTC, Motor Control
STR755FV1 144 16 -40 to +85 LQFP100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C 72 – – RTC, Motor Control
STR750FV0 80 16 -40 to +85 TQFP100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C, CAN 72 – Device 2.0 RTC, Motor Control
STR755FV0 80 16 -40 to +85 LQFP100 ARM7TDMI 60 10 16 6 16 2xSSP, 3xHS-UART, I2C 72 – – RTC, Motor Control
STR755FR2 272 16 -40 to +85 LQFP64, BGA64 ARM7TDMI 60 10 11 6 16 2xSSP, 3xHS-UART, I2C 38 – – RTC, Motor Control

STR750 Full Evaluation Board STR750F full evaluation board with 2 x 16 LCD, LEDs, UART and CAN interfaces STR750-EVAL
Hitex Starter Kit for STR750 Hitex starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain STR750-SK/HIT
IAR KickStart™ Kit for STR750 IAR KickStart™ starter kit with STR750 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain STR750-SK/IAR
Keil Starter Kit for STR750 Keil starter kit with STR750F evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools STR750-SK/KEIL
REva Starter Kit - Raisonance Raisonance REva starter kit for STR750F with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR750F daughter, 16 KB code-size limited version of the RIDE software STR750-SK/RAIS
tool set and GNU C/C++ compiler for ARM
STR750 Motor Control Kit This motor control kit is ready to run within minutes for PMSM and induction 3-phase motors using STR750F for vector control drive. PMSM motor included STR750-MCKIT
ST750F Family of Microcontrollers | STMicroelectronics
52 |
STR910F
Core: ARM966E-S
The STR910F family of MCUs delivers up to 96 MIPS peak performance while

executing code directly from its Flash memory, executes single-cycle DSP instructions
within its ARM966E-S core, and includes Ethernet, USB, and CAN interfaces. These
features, combined with Flash memory sizes reaching 544 Kbytes and a vast 96 Kbyte
SRAM, make the STR910F an ideal single-chip solution to transform embedded control
applications into low cost nodes on a local network, or on the Internet.

• 96 MHz ARM966E-S CPU core with single-cycle DSP instructions
and independent internal 32-bit buses
• 10/100 Ethernet connectivity with optimized DMA data flow
• Plentiful SRAM and Flash memories
• Dual bank Flash
• Flexible power and clock management with multiple low
power modes
• Low power (< 1 µA) real-time clock with programmable
wake-up features
• Extensive firmware support and tools offering. The STR910F library
is freely distributed from ST
• Analog capability with 10-bit ADC and full supervisor functions
Benefits c
• Simultaneous access to both code and data, generating 96 MIPS
peak performance executing code from Flash memory, and at the
same time capable of up to 384 Mbytes/sec DMA data flow
between peripherals and SRAM
• Connect your product to a network and retain ample CPU
bandwidth to implement the embedded application
• Meet requirements of complex applications, real-time operating
systems (RTOSs), communication stacks and data storage
• Ideal for robust In-Application Programming (IAP) and
EEPROM emulation
• Tailor your system on the fly to balance performance and power
consumption as needed
• Ideal for battery operated applications
• Extensive firmware support dramatically reduces development time
and increases ease of use
• With so much inside, less is needed outside saving you space, cost
and logistic headaches

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STR911FM44 544 96 -40 to +85 LQFP80 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 40 – Device 2.0 RTC, Motor Control
2
STR912FW44 544 96 -40 to +85 LQFP128 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I C 80 MAC 10/100 Device 2.0 RTC, Motor Control, EMI
2
STR912FW42 288 96 -40 to +85 LQFP128 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I C 80 MAC 10/100 Device 2.0 RTC, Motor Control, EMI
STR911FM42 288 96 -40 to +85 LQFP80 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I2C 40 – Device 2.0 RTC, Motor Control
2
STR910FW32 288 64 -40 to +85 LQFP128 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I C 80 – – RTC, Motor Control
2
STR910FM32 288 64 -40 to +85 LQFP80 ARM966E-S 96 10 8 7 16 3xUART, 2x SPI, CAN, 2xFast I C 40 – – RTC, Motor Control

STR9 Full Evaluation Board An open-design evaluation platform for STR910F, which includes reference code and a range of hardware features for evaluation of device peripherals including USB, Ethernet, CAN, ADC and much more; STR910-EVAL
in addition to a JTAG standard interface for in-circuit debugging and programming, it includes an ETM interface for connection of a trace tool
IAR KickStart™ Kit for STR9 IAR KickStart starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 32 KB code-size limited version of EWARM software toolchain STR91X-SK/IAR
Keil STR9 Starter Kit Keil starter kit with STR9 evaluation board, USB-JTAG debugger and evaluation version of RealView Microcontroller Development Kit for ARM with uVision3 and ARM RealView Compilation Tools STR91X-SK/KEI
REva Starter Kit - Raisonance Raisonance REva starter kit for STR9 with RLink In circuit debugger/programmer (USB host interface), REva mother board, STR9 daughter board, 16 KB code-size limited version of the RIDE software STR91X-SK/RAI
tool set and GNU C/C++ compiler for ARM
Hitex Starter Kit for STR9 Hitex starter kit with STR9 evaluation board, USB-JTAG in-circuit debugger/programmer and 16 KB code-size limited version of HiTOP software toolchain STR91X-SK/HIT
IAR KickStart Kit
54 |
DaVinci™ TMS320DM644x
Digital Signal Processing SoCs
Core: ARM9 + TMS320C64x+
DaVinci™ technology makes break-through innovation possible in digital media devices

for the hand, home, and car. DaVinci is the first integrated portfolio of Digital Signal
Processing SoCs, software, tools, and support optimized for digital video systems.
These integrated components are the industry’s first complete offering of an open
platform.
Sampling today, the portfolio of DaVinci processors include the TMS320DM644x

digital media processors which are highly integrated SoCs based on an ARM926 processor and the TMS320C64x+
DSP core. The TMS320DM644x processors are ideal for applications such as videophones, automotive infotainment,
digital still cameras, streaming media, and IP set-top boxes.
Features c TMS320DM6446 DSP Block Diagram

• Integrated portfolio of Digital Signal Processing SoCs, software,
development tools, and support
• Optimized for digital video systems, DaVinci technology
accelerates innovation
• A complete portfolio of TI-developed digital media software
is now widely available to further simplify design; the software
portfolio includes multimedia codecs such as H.264, MPEG-4,
WMA9 and many more; for a free evaluation,
visit www.ti.com/digitalmediasoftware
• Supports several Operating Systems, appropriate for different
applications, including open source Linux, MontaVista™ Linux,
Green Hills INTEGRITY™, Green Hills VelOSity, QNX Neutrino
and Microsoft Windows® CE
Benefits c
• Save months of development time by leveraging integrated,
production-tested software and hardware components
• An open development platform enables OEM product
differentiation with a flexible, complete solution
• Lower system cost significantly and leverage IP across
multiple products
• Standard operating systems will allow developers with expertise
on these systems to work in an environment that is familiar
• Valued members of TI’s Third Party Network provide integral
components and tools that complement DaVinci™ technology;
they offer various levels of video system integration, optimization
and system expertise on DaVinci products worldwide

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Part Total Total Temp. °C Package Max. A/D A/D Timer Serial Interface GPIO Ethernet USB Peripherals
Number Flash RAM Type Frequency Bits Channels Channels Description
TMS320DM6441ZWT 16 176 (DSP), 0 to +85 361 Pb-free BGA 513/405 DSP, N/A 16 (ARM) 1 x 64-bit WD, ASP, I2C, SPI, 71 10/100 Mbps EMAC USB 2.0 Video port front end, video port back end, VICP, VLYNQ,
(ARM) 40 (ARM) 257/202 RISC 2 x 64-bit GP 3xUARTs NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD. This device
is similar to the TMS320DM6446BZWT
TMS320DM6443BZWT 16 176 (DSP), 0 to +85 361 Pb-free BGA 594 DSP, N/A 16 (ARM) 1 x 64-bit WD, ASP, I2C, SPI, 71 10/100 Mbps EMAC USB 2.0 Video port back end, VICP, VLYNQ, NAND Flash,
(ARM) 40 (ARM) 297 RISC 2 x 64-bit GP 3xUARTs SmartMedia/xD, ATA/CF, MMC/SD
TMS320DM6446BZWT 16 176 (DSP), 0 to +85 361 Pb-free BGA 594 DSP, N/A 16 (ARM) 1 x 64-bit WD, ASP, I2C, SPI, 71 10/100 Mbps EMAC USB 2.0 Video port front end, video port back end, VICP,VLYNQ,
(ARM) 40 (ARM) 297 RISC 2 x 64-bit GP 3xUARTs NAND Flash, SmartMedia/xD, ATA/CF, MMC/SD

Digital Video Evaluation Module The Digital Video Evaluation Module (DVEVM) allows developers to write production-ready application code for the ARM and provides access to the DSP core using DaVinci APIs to begin immediate TMDXEVM6446
application development for the TMS320DM6441, TMS320DM6443 and TMS320DM6446 digital media processors
Digital Video Software Development Kit The Digital Video Software Development Kit (DVSDK) is a software development kit designed to tune complex DaVinci-based digital video systems quickly and efficiently; the DVSDK significantly TMDSSDK6446-L
improves software integration and system visibility by incorporating tools such as the eXpressDSP™ Configuration Kit, TMS320DM644x SoC Visual Analyzer and MontaVistas Linux
Digital Video Software Development Kit Digital Video Evaluation Module
DaVinci™ Family of Microcontrollers | Texas Instruments, Inc.
58 |
IAR Embedded Workbench Version 4.41 for ARM ®

C/C++ Compiler and Debugger Tools for ARM
IAR Embedded Workbench® is a set of highly sophisticated and easy-to-use development tools
for programming ARM® embedded applications. It integrates the IAR C/C++ compiler, assembler,
linker, librarian, text editor, project manager, and C-SPY® debugger in one Integrated Development
Environment (IDE). With its built-in chip-specific code optimizer, IAR Embedded Workbench
generates very efficient and reliable FLASH/PROMable code for ARM devices. In addition to
this solid technology, IAR Systems provides professional, worldwide technical support.
The ARM Cortex-M3 processor offers significant benefits to

system and software developers.
• ARM7 (ARM7TDMI, ARM7TDMI-S, and ARM720T)
• ARM9 (ARM9TDMI, ARM920T, ARM922T, and ARM940T)
• ARM9E (ARM926EJ-S, ARM946E-S, and ARM966E-S)
• ARM11
• Cortex-M3
• Intel® XScale™ core
Key Components c
• IDE with project management tools and editor
• Highly-optimizing ARM compiler supporting C and C++
• Configuration files for ARM chips from Analog Devices,
Atmel, Freescale, Intel, Luminary Micro, NXP,
STMicroelectronics, and Texas Instruments
• Extensive JTAG and RDI debugger support
• Optional IAR J-Link and IAR J-Trace hardware debug Highlights in the Current Version c
probes
• IAR PowerPac bundled evaluation edition of
• Run-time libraries including source code
RTOS and file system for ARM
• Relocating ARM assembler
• Live watch on target hardware
• Linker and librarian tools
• Code coverage using IAR J-Trace
• C-SPY debugger with ARM simulator, JTAG support,
• Comprehensive Flash loader support
and support for RTOS-aware debugging on hardware
• I/O register definition files
• Evaluation edition of IAR PowerPac RTOS and file
• More than 400 sample projects for different
system bundle
evaluation boards
• RTOS plug-ins available from IAR Systems and
RTOS vendors
• Code templates for commonly used code constructs Supported ARM Cores and Devices c
• Sample projects for evaluation boards from many IAR Embedded Workbench supports ARM7, ARM9, ARM9E,
different manufacturers ARM11, Cortex-M3, and Intel® XScale™ devices from these
• User and reference guides, both printed and in manufacturers:
PDF format
• Analog Devices • Atmel
• Context-sensitive online help
• Freescale Semiconductor • Intel
• Luminary Micro • NXP
• STMicroelectronics • Texas Instruments
For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.

1-866-910-3650
| 59
Chip-Specific Support c • Trace utility to examine execution history: moving around

• Ready-made C/C++ and assembler peripheral register in the trace window updates the editor and disassembly
definition files windows to show the appropriate location
• Multiple code and data models (where applicable) • Terminal I/O emulation
• Extensive set of language features for PROMable • Interrupt and I/O simulation
embedded code, including memory keywords, intrinsic • C-like macro system to extend debugger functionality
functions, interrupt functions, memory-mapped I/O • Application program system calls emulated by the host
ports, etc. • Code coverage and profiling performance analysis tools
• Sample projects for evaluation boards from IAR Systems, • Support for the ARM Debug Communication Channel (DCC)
Analog Devices, ARM, Atmel, Freescale, Keil, LogicPD, • Generic Flash loader with API guide
Luminary Micro, Nohau, NXP, Phytec, STMicroelectronics, • Multiple Flash loaders supported
and Texas Instruments • Debugger software development kit for third-party
• Support for 4 Gbyte applications in ARM and extensions such as real-time operating systems and
Thumb® mode emulator drivers
• Each function can be compiled in ARM or Thumb mode • Command line debugger utility
• Vector Floating Point (VFP) coprocessor code generation
• Flash loaders included for devices from Analog Devices, Graphical IDE c
Atmel, Freescale, Luminary Micro, NXP, • Hierarchical project presentation
STMicroelectronics, and Texas Instruments • Multiple projects within the same workspace
• ARM Angel debug monitor support • Dockable windows and multiple views
• Source browser
Embedded Focus c • Library tools included for creating and
• Advanced generic and processor-specific optimizations maintaining libraries
for speed and memory footprint • Integration with source code control systems
• Lightweight runtime library: user-configurable to match • Text editor with multi-byte character support:
the needs of the application; full source included context-sensitive help system; syntax coloring; unlimited
• Flexible memory handling allows detailed control of undo/redo; find; search; replace; incremental search;
code and data placement bookmarks; error tags; previous/next navigation;
• Unnecessary functions and variables are removed matching brackets; smart indentation; code breakpoint
• Application-wide type checking of C/C++ variables set/clear/enable/disable; and multiple panes
and functions at link time • Command line build utility
• Optional flexible checksum generation for image
runtime verification Language and Standards c
• Automatic placement of code and data in non-contiguous • The C programming language, as standardized by
memory regions ISO/ANSI C94, with selected features from C99
• Powerful relocating macro assembler with a versatile set • Embedded C++ extended with templates, multiple and
of directives and operators virtual inheritance, namespaces, and other C++ features
that do not cause an overhead in size or speed; full
Embedded Debugging c Embedded C++ library containing string, streams, etc.,
• Fully integrated debugger for source and disassembly as well as the Standard Template Library (STL)
level debugging • IEEE-754 floating-point arithmetic
• Very fine granularity execution control (function • MISRA C checker
call-level stepping) • Supports a wide range of industry-standard debug and
• Complex code and data breakpoints image formats: compatible with most popular debuggers
• Versatile monitoring of data: locals, watch, auto, and emulators, including ELF/DWARF where applicable
live watch, and quick watch windows; register and
memory windows User Assistance c
• STL container awareness • Ready-made sample projects and project templates
• C/C++ call stack window that also shows the function • Context-sensitive online help with library function lookup
to be entered; double-click on any function in call • Printed user guides with extensive step-by-step tutorials
chain updates the editor, locals, register, watch, and • User friendly, detailed, and precise error messages
disassembly windows to display the state of that and warnings
particular function at the time of call
60 |
The Keil RealView Microcontroller Development Kit

Create Applications for ARM7, ARM9, or Cortex-M3 Based Microcontrollers
The RealView® Microcontroller Development Kit (MDK) shortens development cycles by
reducing the time spent configuring, testing, and debugging embedded applications.
The RealView MDK combines ARM RealView compilation tools with the Keil µVision®
Integrated Development Environment (IDE), providing developers with a feature-rich envi-
ronment optimized for ARM-Powered® microcontrollers.
The Keil µVision IDE includes c RealView

RealView Microcontroller Development Kit
Real-Time Library
• Project management and device and tool configuration
µVision Project Manager RTX Source Code
• A source code editor optimized for embedded systems
• Target debugging and Flash programming TCP/IP Suite
C/C++ Compiler Macro Assembler
• Accurate device simulation (CPU and peripheral) TCP, UDP, PPP, SLIP,
ARP, DNS Resolver,
Ethernet, DHCP Client,
RTX RTOS Libraries HTTP Server with CGL
TFTP Server, SMTP Client
ARM technology-based projects created under µVision are
automatically compiled and linked using the RealView Linker / Locator
Flash File System
compilation tools.
µVision Debugger USB Device Interface
The built-in microcontroller simulator models more than 50
ARM-Powered® devices, including the ARM instruction set, Device Simulation Target Hardware CAN Interface
on-chip peripherals, and the external signals used to
manipulate them.
ARM RealView compilation tools are recognized by the industry
for providing the best performance of all available ARM
technology-targeted compilers. Developed and tuned to deliver Project Management c
the tightest code density, the compiler produces the smallest
code size, which leads to significant product cost savings. File groups allow associated files to be grouped together. They
The compiler generates optimized code for both the 32-bit may be used to separate files into functional blocks or to identify
ARM and 16-bit Thumb® instruction sets while supporting engineers in your software team.
full ISO standard C and C++.
Project targets allow you to create several programs from a
single project. You may require one target for testing and
another target for a release version of your application. Each
Project Configuration c
target allows individual tool settings within the same project file.
The µVision IDE incorporates a device database of supported
ARM-Powered microcontrollers. In µVision projects, required
options are set automatically when you select the device from Editor c
the device database.
The µVision Editor includes all the standard features you
µVision displays only those options that are relevant to the expect in a professional editor. Color syntax highlighting and
selected device and prevents the selection of incompatible text indentation are optimized for editing C source files, while
directives. Only a few dialogs are required to completely document outlining allows you to collapse function blocks in
configure all the tools (assembler, compiler, linker, debugger, your source code. Most Editor functions are quickly accessed
and Flash download utilities) and memory map for your from the toolbars.
application.
While debugging, the Editor is available so you can easily make
changes to your source code.
For more information on Arrow's Development Tools, pricing and availability, visit www.arrowdevtools.com or call 1-866-910-3650.

1-866-910-3650
| 61
Debugger c Accurate Device Simulation c

The µVision Editor enables you to set simple breakpoints The µVision Debugger simulates a complete ARM-Powered
using the context menu (or Editor toolbar) while creating your microcontroller including the instruction set and on-chip
C or assembler source. Breakpoints you set while editing are peripherals. These powerful simulation capabilities provide
activated when you start the µVision Debugger. serious benefits and promote rapid, reliable embedded
software development.
In addition to simple breakpoints, the µVision Debugger
supports complex breakpoints (with conditional or logical • Simulation allows software testing on your desktop with
expressions) and memory access breakpoints (with read/write no hardware environment
access from an address or range). The Debugger also • Early software debugging on a functional basis improves
displays code coverage and execution profiling information overall software reliability
in the Editor windows. • Simulation allows breakpoints that are not possible with
hardware debuggers
• Simulation allows for optimal input signals (hardware
RealView Real-Time Library c
debuggers add extra noise)
• Signal functions are easily programmed to reproduce
The RealView Real-Time Library (RL-ARM) enables networking, complex, real-world input signals
communication, and real-time software. The RL-ARM is based on • Single-stepping through signal processing algorithms is
a real-time kernel that simplifies the design and implementation possible; external signals stop when the CPU halts
of complex, time-critical applications. A Flash file system, • It is easy to test failure scenarios that would destroy real
TCP/IP networking suite, and other communication protocols hardware peripherals
are included.
Today, microcontroller applications require simultaneous
execution of multiple jobs or tasks. For such applications,
the RL-ARM allows task management and flexible scheduling
of system resources (CPU, memory, etc.).
The RL-ARM is a full-featured real-time kernel with task
priorities, round-robin, preemptive context switching, and
support for multiple instances of the same task function.
It is royalty-free and is fully integrated into µVision.
Third-Party Utilities c
Third-party utilities extend the functions and capabilities of

µVision and are available from a wide variety of vendors.
62 |
RealView Tools by ARM

Tools that Span the Complete Development Process
RealView® tools by ARM® are unique in their ability to provide solutions that span
the complete development process from concept to final product deployment. Each
member of the RealView portfolio has been developed closely alongside IP, ensuring
that it maximizes the IP’s performance.
RealView Development Suite c Eclipse Plug-ins for RealView Development

Suite c
RealView Development Suite is the only complete, end-to-end
solution for software development that supports all ARM® RealView Development Suite integrates with the open-source
processors and ARM debug technology. These tools offer the Eclipse IDE. This integration combines Eclipse’s outstanding
highest-performance ARM C/C++ compilers and support the source code development tools and plug-in framework with the
most advanced debug technology available today for bringing best-in-class compilation and debug technology in the RealView
up the latest SoC and ASIC designs. DEVELOP family of tools. The RealView Eclipse Plug-in enables
developers to use Eclipse as a project manager to create, build,
Proven to deliver the highest return for the lowest risk on their
debug, and manage C and C++ projects for ARM targets. The
ARM-based ASICs, SoC, and FPGA designs, the RealView
plug-in provides project stationery to simplify the creation of
Developer Suite is a trusted source for ARM development
ARM, Thumb®, and ARM/Thumb architecture-based projects,
solutions. Today, the majority of the four billion ARM-Powered™
and provides comprehensive configuration panels to specify
devices worldwide have software created with RealView tools.
options for the RealView Development Suite.
Investing in the RealView solution is the clear choice for a safe,
reliable, and high-performance design.
Compilation Tools c
New Features of RealView Development Suite The compilation tools in RealView Development Suite are
3.0 and SP1 c recognized by the industry for providing the best performance
of all available ARM-processor targeted compilers. Developed
Key features of the RealView Development Suite 3.0 solution
and tuned to deliver the tightest code density, the compilers
include support for the full line of ARM processors, including
produce significantly smaller executables than other leading
the Cortex™-A8 processor, the Cortex-M3 processor, and
tool suites. The compilers generate optimized code for the
future Cortex family processors; support for CoreSight™
32-bit ARM and 16-bit Thumb and Thumb-2 instruction sets
advanced debug and trace technology; an intrinsics compiler
and support full ISO standard C and C++.
for the NEON™ SIMD technology; an enhanced compiler
optimization engine that provides a 10 percent performance
improvement; and interoperability with GNU tools, enabling
Debug Tools c
optimal compilation of Embedded Linux applications and
optional integration with Eclipse. Designed from the ground up to support complex single- and
multi-core SoC software development with Embedded OS, the
RealView Development Suite 3.0 Service Pack 1 provides
debugger in RealView Development Suite sets the standard for
a consolidation of enhancements since the original RealView
creating and debugging deeply embedded applications. No
Development Suite 3.0 release, including preliminary support
other debug environment provides interconnectivity with both
for Cortex-R4, improved compilation times and DWARF3
the RealView CREATE world of system-level modeling and the
debug data sizes, an expanded SIMD NEON assembler
RealView DEVELOP world of software development.
with Programmer’s notation, an improved user interface that
debugs a multi-processor MPCore target, and expanded Cortex-
M3 examples. Add-om Options c
The following components and abilities are offered by the The following are available as add-on options to the RealView
RealView Development Suite: Development Suite:
• Integrated Development Environment (IDE) • RealView SoC Designer
• A choice of IDEs • RealView ICE and RealView Trace
• RealView Development Suite can be integrated • Real-Time System Model (RTSM) for ARM1176JZ(F)-S
with the Industry-standard Eclipse IDE through a • Eclipse IDE plug-in
plug-in or CodeWarrior v5.7 IDE • Plug-ins for popular DSP support

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Supported Platforms: c • Support for variable JTAG clock frequencies, 2 kHz

to 20 MHz (standard cable) or 50 MHz (LVDS cable)
• Windows 2000, XP Professional
• Very low JTAG clock frequencies (sub-1 kHz) support
• Red Hat Enterprise Linux 3 and 4
ASIC-emulation environments
• SPARC Solaris 9 and 10
• Wide target-voltage support, from 1.0V to 5.0V
• Tightly coupled, synchronized multi-core control
• ETM trace data capture with plug-in RealView
RealView ICE c
Trace module
RealView ICE is ARM’s leading-edge JTAG run control • ETB trace data access via the JTAG port
hardware unit, delivering the high performance required by • Debug using GDB and KGDB capability
today’s developers working with sophisticated System-on-Chip • USB 1.1 and 2.0 compatible connection
(SoC) devices and large software images. (Windows platform only)
RealView ICE provides a universal-ARM solution, i.e., one • Ethernet 10/100baseT remote and local host connection
unit supports all ARM CPUs in single, multi-core, homogenous,
and heterogeneous architectures, offering an unparalleled depth
and breadth of support for ARM processor-based devices.
Supported ARM Processors: c
RVI-Supported cores include the following ARM processor-

RealView ICE is an essential tool in an ARM system debug
based families: ARM7™, ARM9™, ARM9E™, ARM10™,
environment for connection and access to devices that contain
ARM11™, and Cortex™
the EmbeddedICE® logic, Embedded Trace Macrocell™ (ETM™),
and Embedded Trace Buffer(ETB™) components for on-chip
trace data storage. The unit has the ability to be expanded
RealView Trace c
with additional modules for extended functionality, such as
RealView Trace for trace data capture. RealView Trace interfaces with ARM on-chip trace data storage
Embedded Trace Macrocell (ETM™) components for the
The recently released RealView ICE version 3.0 now enables
ARM7™, ARM9™, ARM9E™, ARM10™, and ARM11™ core
customers to connect to the new ARM Cortex family of
families, and in conjunction with RealView Debugger. RealView
processors and devices containing the new CoreSight™
Trace provides non-intrusive real-time tracing of instructions,
advanced debug and trace technology. RealView ICE and
data and profiling for performance analysis. It’s an optional
Trace fully complement the RealView Development Suite
add-on expansion module for RealView ICE.
in providing best-in-class integrated tools for
hardware/software co-development of optimized
ASIC, SoC, and FPGA-based systems.
Main Features c
• Non-intrusive real-time tracing of instructions and data up

Other New Features c to 250 MHz trace clock
• Up to eight million frames deep trace buffer (up to four
• JTAG run control for the new Cortex™-A8 and
million frame deep buffer with time stamps)
Cortex-M3 processors
• 4-/8-/16-bit data width trace port
• CoreSight DK11 run control support for the ARM1136,
• Trigger synchronization with external events
ARM1156, and ARM1176 processors
• Fully variable trigger position
• TrustZone® secure and non-secure code views for the
• Fast on-the-fly trace data upload
Cortex-A8 and ARM1176 processors
• Shares RealView ICE connection to the host computer
RealView ICE can be connected to most types of host platforms • ETM trace ports modes supported
by Ethernet for extended and remote connection, or locally by – ETM protocols v1.x, v2.x, v3.x for ETM7TM, ETM9TM,
USB, to provide the optimum debug coupling and performance ETM10TM, and ETM11TM
with the RealView Debugger. – Single and doubled-edged clocking
– Normal and multiplexed ports
• Time stamp (48-bit) 10 ns resolution with 32-day duration
Main Features c
• High-performance debug control

Platforms supported are Windows 2000 and XP
• Code download up to 1300 KBytes/sec with
the RealView Debugger Note: Cannot be used standalone. This product is designed to
• High-speed single-stepping; up to 100 steps/sec be used in conjunction with a RealView ICE
• JTAG Debug Communications Channel (DCC) support
Embedded Developer
lets you compare
more than and ...
S elect and compare ARM7 core-
based devices like the LPC2000
from NXP, the STR7 from
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ARROW ARM SOLUTIONS GUIDE

4 Arrow Services and Solutions

Arrow Electronics ARM Solutions

ARM Support from Concept through Production

Engineering Expertise—the Right Team Arrow Technical Solutions Forum (ATSF): c

Arrow Electronics ARM Solutions

Innovative Arrow Services

Arrow Consulting Engineering Services c Supply Chain Solutions c

Custom Logic Solutions c

For information on Arrow’s Innovative Services, visit www.arrownac.com/arm or call 1-866-910-3650.

ARM7TDMI and ARM7TDMI-S

The Instruction Pipeline c

The Instruction Pipeline c

Arrow Electronics ARM Solutions

EmbeddedICE-RT Logic c On execution, 16-bit Thumb instructions are transparently

ARM920T Application Support Features c

The ARM920T’s interface to the rest of the system is over

Arrow Electronics ARM Solutions

Applications c • MMU which supports operating systems including

• Industrial connectivity • Instruction and data caches: ARM920T = 16K/16K,

• 3G baseband and applications processor

• Set-top box • Multiple sourcing from industry-leading silicon vendors

• Code-compatible upward migration path to ARM10E

• 16-bit Thumb instruction set for increased code density

The ARM926EJ-S processor is a member of the ARM9 family of

The ARM926EJ-S processor supports the ARM debug architec- ARM926EJ-S

• Separate instruction and data AMBA AHB bus interfaces

• Separate instruction and data TCM interfaces

The ARM926EJ-S processor provides support for external

Arrow Electronics ARM Solutions

• Platform OS-based devices • Support for leading Java run-times

• Next-generation smart phones, communicators, • High-efficiency Java bytecode execution

• Jazelle support code has no increase in VM size

Features c • Simple single-processor software structure, no need

• ETM interface for real-time trace capability with ETM9

• Optional MOVE coprocessor delivers video encoding

The ARM966E-S processor has separate, directly connected

• Support for external TCM; a TCM interface is provided

Providing this complete high-frequency subsystem frees the SoC

Arrow Electronics ARM Solutions

• Industrial control • Deterministic performance from TCM memories

• Wireless devices • Single development toolkit: reduced development

• Multiple sourcing from industry-leading silicon vendors

The ARM1136JF-S processor incorporates an integer unit that

• An integer unit with integral EmbeddedICE-RT logic

• Branch prediction with return stack

Interface Interface Port

• Instruction and Data Memory Management Units (MMUs),

• Instruction and data caches, including a non-blocking

• High-speed Advanced Microprocessor Bus Architecture Registers c

Arrow Electronics ARM Solutions

Thumb Instruction Set c Memory System c

• Separate instruction and data RAMs

• MAC operations Applications c

The cache sizes are specified as InstructionCache/DataCache.

processor is enabled by new ARM Artisan® Advantage-CE

The processor is supported by a wide range of ARM

• The RealView® DEVELOP family of software

• CoreSight™ debug and trace technology as well MAC

The ARM Cortex-A8 processor’s sophisticated pipeline NEON

achieving 2.0 DMIPS/MHz.

Arrow Electronics ARM Solutions