DOC/LP/00/08.12.09 LESSON PLAN S0b C#'e 1 N*(e" CS22-.

-C#(%0te& #&,*$i2*ti#$ *$' A&c+itect0&e

B&*$c+ " CS Se(e!te& " B.E-I3 LP-CS 22-. LP" Re . N#" 00 D*te"10"12"09 P*,e 1 #) /

UNIT-I BASIC STRUCTURE OF COMPUTERS

Syllabus Functional Units-Basic Operational Units-Bus StructuresPerformance and metrics and Instructions and Instruction SequencingHardware-Software Interface-Instruction Set Architecture-Addressing modes- IS!-!IS!-A"U #esign-Fi$ed point and Floating point Operations%

Objecti e!" To understand the Functions and design of various units of digital computers to store and process the informations. Se!!i#$ $# 1 2 $ 5 ) + . 0 T#%ic! t# be c# e&e' Functional Units, Basic Operational Units Bus Structures, !erformance and metrics and "nstructions and "nstruction Se#uencing %ard&are,Soft&are "nterface "nstruction Set (rchitecture, (ddressing modes '"S*,*"S* (,U -esign Fi/ed point Operations Floating point Operations Ti(e i$ (i$. 50 50 50 50 50 50 50 50 50 Re). T1 T1 T1 '2 T1 '2,' '2,' '2,' '2,' Te*c+i$, (et+#' BB BB BB BB BB BB BB BB BB

DOC/LP/00/08.12.09 LESSON PLAN S0b C#'e 1 N*(e" CS22-.-C#(%0te& #&,*$i2*ti#$ *$' A&c+itect0&e
B&*$c+ " CS Se(e!te& " B.E-I3 LP-CS 22-. LP" Re . N#" 00 D*te"10"12"09 P*,e 2 #) /

UNIT II - BASIC PROCESSING UNIT

S455*b0!1 Fundamental concepts 2 3/ecution of a complete instruction 2 4ultiple 5us organi6ation 2 %ard&ired control 2 4icro programmed control 2 7ano programming. Objecti e!" To stud8 the Fundamental concepts of various processing units. Se!!i#$ $#. 10. 11. 12. 1 . 1$. 15. 1). 1+. 1.. T#%ic! t# be C# e&e' Fundamental concepts 3/ecution of a complete instruction 4ultiple 5us organi6ation "ntroduction a5out control units %ard&ired control 4icro programmed control 7ano programming 'evision for *(T " *(T 9 " Ti(e i$ (i$. 50 50 50 50 50 50 50 50 Re). T1 T1 T1 T1 T1 T1 '2 Te*c+i$, Met+#' BB BB BB BB BB BB BB

-O*:,!:00:0..12.00 LESSON PLAN S0b C#'e 1 N*(e" CS22-.-C#(%0te& #&,*$i2*ti#$ *$' A&c+itect0&e
B&*$c+ " CS Se(e!te& " B.E-I3 LP-CS 22-. LP" Re . N#" 00 D*te"10"12"09 P*,e . #) /

UNIT III - !"!3,"7"7;

S455*b0!" Basic concepts 2 -ata ha6ards 2 "nstruction ha6ards 2 "nfluence on instruction sets 2 -ata path and control considerations 2 !erformance considerations 2 3/ception handling. Objecti e!" To <no& and understand the various t8pes of ha6ards and 3/ception handling concepts.. Se!!i#$ $#. 22. 2 . 2$. 25. 2). 2+. 2.. 20. Basic concepts -ata ha6ards "nstruction ha6ards "nfluence on instruction sets -ata path control considerations !erformance considerations 3/ception handling. T#%ic! t# be c# e&e' Ti(e i$ (i$. 25 50 50 25 50 50 50 50 T1 T1 T1 T1 T1 T1 T1 '2 Re). Te*c+i$, Met+#' BB BB BB BB BB BB BB BB

LESSON PLAN S0b C#'e 1 N*(e" CS22-.-C#(%0te& #&,*$i2*ti#$ *$' A&c+itect0&e

B&*$c+ " CS Se(e!te& " B.E-I3

LP-CS 22-. LP" Re . N#" 00 D*te"10"12"09 P*,e 7 #) /

DOC/LP/00/08.12.09

U7"T "= 9 MEMOR6 S6STEM

S455*b0!" Basic concepts 2 Semiconductor '(4 2 'O4 2 Speed 2 Si6e and cost 2 *ache memories 2 "mproving cache performance 2 =irtual memor8 2 4emor8 management re#uirements 2 (ssociative memories 2 Secondar8 storage devices. Objecti e!" To stud8 and understand the concepts of various memor8 s8stem. Se!!i#$ $#. 0. 1. 2. . $. 5. ). +. .. 0 $0 Basic concepts Semiconductor '(4 'O4, Speed , Si6e and cost *ache memories "mproving cache performance =irtual memor8 4emor8 management re#uirements (ssociative memories Secondar8 storage devices 'evision for *(T "" *(T 9 "" T#%ic! t# be c# e&e' Ti(e i$ (i$. 50 50 50 50 50 50 50 50 50 50 T1 T1 T1 T1 T1 T1 Re). Te*c+i$, (et+#' BB BB BB BB BB BB !! BB BB

LP-CS 22-.

LESSON PLAN S0b C#'e 1 N*(e" CS22-.-C#(%0te& #&,*$i2*ti#$ *$' A&c+itect0&e

B&*$c+ " CS Se(e!te& " B.E-I3

LP" Re . N#" 00 D*te"10"12"09 P*,e - #) /

DOC/LP/00/08.12.09

U7"T =9 ":O O';(7">(T"O7

S455*b0!" (ccessing ":O devices 2 !rogrammed "nput:Output 9"nterrupts 2 -irect 4emor8 (ccess 2 Buses 2 "nterface circuits 2 Standard ":O "nterfaces ?!*", S*S", USB@, ":O devices and processors. Objecti e!1 To <no& the services and functions of the various "nterfaces and "nterrupts. Se!!i#$ T#%ic! t# be c# e&e' $#. $1. (ccessing ":O devices $2. $ . $$. $5. $). $+. $.. $.. $0. !rogrammed "nput:Output "nterrupts -irect 4emor8 (ccess Buses "nterface circuits Standard ":O "nterfaces ?!*", S*S", USB@ ":O devices and processors. 'evie& for *(T """ *(T """ Ti(e i$ (i$. 50 50 50 50 50 50 50 50 50 00 Re). T1 '2 T1 T1 T1 T1 T1 '2 Te*c+i$, (et+#' BB BB BB BB BB BB BB BB

LESSON PLAN S0b C#'e 1 N*(e" CS22-.-C#(%0te& #&,*$i2*ti#$ *$' A&c+itect0&e

B&*$c+ " CS Se(e!te& " B.E-I3

LP-CS 22-. LP" Re . N#" 00 D*te"10"12"09 P*,e / #) /

DOC/LP/00/08.12.09 Course Delivery Plan

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Unit 1 s

BOO8S FOR REFERENCE" TE9T BOO8S 1. *arl %amacher, >von<o =ranesic and Saf&at >a<8, A*omputer Organi6ationB, Fifth 3dition, Tata 4c;ra& %ill, 2002. REFERENCE 1. -avid (. !atterson and Cohn ,. %enness8, A*omputer Organi6ation and -esign1 The %ard&are:Soft&are interfaceB, Third 3dition, 3lsevier, 2005. 2. Dilliam Stallings, A*omputer Organi6ation and (rchitecture 2 -esigning for !erformanceB, Si/th 3dition, !earson 3ducation, 200 . . Cohn !. %a8es, A*omputer (rchitecture and Organi6ationB, Third 3dition, Tata 4c;ra& %ill, 100.. $. =.!. %euring, %.F. Cordan, A*omputer S8stems -esign and (rchitectureB, Second 3dition, !earson 3ducation, 200$.

P&e%*&e' b4 Si,$*t0&e N*(e De!i,$*ti#$ D*te Mi!!.P.3i$#t+i4*5*:!+(i; Mi!!.<.B0 *$* Lect0&e& 10"12"2009

A%%&# e' b4 D&.S0!*$ E5i*! =#';De%t. #) CSE 10"12"2009