Zynq-7000 - A Breakthrough in Integration of All Programmable Soc

Zynq-7000 A Breakthrough in Integration of All Programmable SoC
Guy Lampert Xilinx April 2013
Copyright 2013 Xilinx

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Demands of Today's Technology

ASIC
FPGA
ASSP
Structured
ASIC
Which Technology Should I Choose?

Page 2

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Current Selections Equal Compromise

2 Chip Solution
ASIC
System Performance Total Power Unit Cost BOM Cost TCO TTM Design Productivity
ASSP
+ + +
+ + + + +
+ +
Flexibility
Scalability Risk
+ + +
+ positive, - negative, neutral

Conflicting Demands Not Served
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BDTI HLS Tool Certification Program

Program Objectives
Expand the use of HLS for FPGAs by providing credible evidence of their capabilities Provide an accurate picture of the efficiency of HLS Provide tool vendors with reliable data on HLS strengths and weaknesses
NOTE: Maximum frame rate achieved (at 720p resolution) on the BDTI Optical Flow Workload (a video application) on a DSP processor and a Spartan3A DSP FPGA using HLS.
BDTI Key Findings:

For example, DSP applications that have high data rates and high computational workloads inherently well suited for FPGAs
FPGAs offer 40x better performance than mainstream DSPs C to FPGA requires different skill sets but similar level of effort as C to DSP HLS achieved comparable FPGA resource utilization to hand-coded RTL
NOTE: FPGA resource utilization on the BDTI DQPSK Workload (a wireless receiver) implemented using HLSTs (average result) versus hand-written RTL code.
Source: BDTI Results 2010 BDTI. See http://www.bdti.com/ for details. http://www.bdti.com/MyBDTI/pubs/AutoPilot.pdf http://www.bdti.com/MyBDTI/pubs/Xilinx_hlstcp.pdf
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Copyright 2013 Xilinx Copyright 2012 Xilinx

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Xilinx Technology Evolution
28nm
Programmable Logic Devices

Enables Programmable Logic
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All Programmable Devices

Enables Programmable Systems Integration

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Why All Programmable?
Reduce exploding design costs Dramatically increase flexibility Leverage broad technology portfolio
Logic & high-speed I/O S/W-programmable ARM systems 3-D IC Analog/mixed-signal System-to-IC design tools Intellectual property
Increased System Performance
Programmable Systems Integration
BOM Cost Reduction
Total Power Reduction
Accelerated Design Productivity
Build better electronic systems with fewer chips.faster!

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The First All Programmable SoC
2012
Production: NOW
350+ unique customers actively designing 100+ AP SoC specific partners All Major OSs supported and in use 20+ different development boards Won every award it entered
Page 7
2010

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Xilinx Pioneered the All Programmable SoC

Innovation with All Programmable SoC Innovated
a new class of all programmable SoC devices
Executed by delivering tools, samples and enabling eco-system Momentum

from first shipment, delivering boards, customer wins
Safe choice with a comprehensive offering already in existence today

ARM Partnership (AXI-4) Architecture Announcement 1st Zynq based product delivered by Customer
Zynq Product Announcement OS & Tools
First Customer Shipment
Security & Safety Enablement
Production Availability
2010
Emulation Platform Demonstrated and delivered
2011
Open Source Linux Public Push
2012
Dev. Boards Available 1 GHz Peak Processing Performance
2013
Segment Solutions
Page 8

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Zynq-7000 Block Diagram

Processing System
Static Memory Controller Quad-SPI, NAND, NOR Dynamic Memory Controller DDR3, DDR2, LPDDR2
Programmable Logic:
Multi-Standards I/Os (3.3V & High Speed 1.8V)
2x SPI 2x I2C
2x CAN 2x UART
I/O MUX
AMBA Switches
AMBA Switches
System Gates, DSP, RAM S_AXI_HP0 S_AXI_HP1 S_AXI_HP2 S_AXI_HP3 S_AXI_ACP
ARM CoreSight Multi-core & Trace Debug NEON/ FPU Engine Cortex-A9 MPCore MIO 32/32 KB I/D Caches
512 KB L2 Cache Timer Counters General Interrupt Controller
NEON/ FPU Engine Cortex-A9 MPCore 32/32 KB I/D Caches

Snoop Control Unit (SCU)
GPIO 2x SDIO with DMA 2x USB with DMA 2x GigE with DMA
256 KB On-Chip Memory

DMA Configuration
Switches Switches AMBA AMBA
EMIO
XADC
S_AXI_GP0/1
M_AXI_GP0/1
PCIe
Multi-Standards I/Os (3.3V & High Speed 1.8V)
Multi Gigabit Transceivers
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Complete ARM-based Processing System

Processor Core Complex
Dual ARM Cortex-A9 MPCore with NEON extensions Single / Double Precision Floating Point support Up to 1 GHz operation
High BW Memory
Internal
L1 Cache 32KB/32KB (per Core) L2 Cache 512KB Unified
On-Chip Memory of 256KB Integrated Memory Controllers

(DDR3, DDR3L, DDR2, LPDDR2, 2xQSPI, NOR, NAND Flash)
AMBA Open Standard Interconnect Integrated Memory Mapped Peripherals

2x USB 2.0 (OTG) w/DMA 2x Tri-mode Gigabit Ethernet w/DMA 2x SD/SDIO w/DMA 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 32b GPIO High bandwidth interconnect between Processing System and Programmable Logic ACP port for enhanced hardware acceleration and cache coherency for additional soft processors
Processing System Ready to Program

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Tightly Integrated Programmable Logic

Built with State-of-the-art 7 Series Programmable Logic
Artix-7 & Kintex-7 FPGA Fabric 28K-444K logic cells 430K-6.6M equivalent ASIC gates
Note: ASIC equivalent gates based on analysis over broad range of designs
Over 3000 Internal Interconnects

Up to ~100Gb of BW Memory-mapped interfaces
Integrated Analog Capability

Dual multi channel 12-bit A/D converter Up to 1Msps
Enables Massive Parallel Processing

Up to 2020 DSP blocks delivering over 2662 GMACs
Scalable Density and Performance

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Flexible External I/O

54 Dedicated Peripheral I/Os
Supports integrated peripherals Static memory (NAND, NOR, QSPI) More I/Os available though the Programmable Logic
73 Dedicated Memory I/Os

DDR3 / DDR3L / DDR2 / LPDDR2 Memory Interfaces Configurable as 16bit or 32bit
Up to 400 Multi-Standard and High Performance I/O

Up to 250 3.3V capable multi-standard I/O Up to 150 high performance I/O Up to differential 17 ADC inputs
High Performance Integrated Serial Tranceivers

( 7030 / 7045 / 7100) Up to 16 transceivers Operates up to 12.5Gbs Supports popular protocols Integrated PCIe Gen2 block
Flexibility Beyond Any Standard Processing Offering

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Zynq-7000 Device Portfolio

Scalable platform offers easy migration between devices
Zynq-7000 AP SoC Devices
Processor Core
Z-7010
Z-7020
Z-7030
Z-7045
Z-7100
Dual ARM Cortex-A9 MPCore

NEON & Single / Double Precision Floating Point 800 MHz Up to 1 GHz
Processing System
Processor Extensions Max Frequency Memory External Memory Support Peripherals
L1 Cache 32KB I / D, L2 Cache 512KB, on-chip Memory 256KB DDR3, DDR3L, DDR2, LPDDR2, 2x QSPI, NAND, NOR 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Programmable Logic
Approximate ASIC Gates Block RAM Peak DSP Performance (Symmetric FIR) PCI Express (Root Complex or Endpoint) Agile Mixed Signal (XADC) Processor System IO Multi Standards 3.3V IO Multi Standards High Performance 1.8V IO Multi Gigabit Transceivers
~430K (28k LC) 240KB 100 GMACS -
~1.3M (85k LC) ~1.9M (125k LC) 560KB 276 GMACS 1,060KB 593 GMACS Gen2 x4
~5.2M (350k LC) 2,180KB 1334 GMACS
~6.6M (444kLC) 3,020KB 2662 GMACS
Gen2 x8
2x 12bit 1Msps A/D Converter 130 100 200 100 150 4 212 150 16 250 150 16
I/O
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Zynq-7000 AP SoC is Solution Ready

Solution Ready means:
Platform Availability
Silicon and Board availability & maturity
Xilinx Development Elements

Documentation, Tools, Support,
Ecosystem Development Elements

Software, Hardware, IP, Training & Design Services
Platform Solutions
Safety & Security, Acceleration
Segment Solutions
Ecosystem Dev. Elements Xilinx Dev. Elements Platform Availability Platform Solutions
Segment Solutions
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Zynq Family in Full Production
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Large Board / Kits Ecosystem
Wide distribution of Zynq-7000 AP SoC based boards/kits

5000+ boards/kits shipped between Xilinx and Avnet. More from other partners
20+ Development Boards and SOMs from Xilinx and its partners
Use-Case and Market Specific Boards
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Platform Solutions
Segment Solutions
Segment Solutions
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Zynq-7000 AP SoC Configuration
Easily Configure the Processing System

Select and route the PS I/O
Configure clocks, memory controllers, timers, AXI interconnects
Drag and Drop to Add AXI IP Cores from the Xilinx catalog
Audio, video and image processing Communications and networking Digital Signal Processing Embedded system IP Memory interface and storage
Xilinx Platform Studio

Graphical Zynq-7000 All Programmable SoC Configuration
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Software Development and Debug
Develop Linux and Bare-Metal Applications
Project templates
Board Support Package Boot Loader C & C++ Memory & peripheral tests
Build, Deploy, Debug

Build with integrated compiler(s)
Automatically deploys to target, connects debugger, and begins program execution
Xilinx SDK
Turn-Key Application Development Environment
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Configure, Build, Deploy Linux
PetaLinux: Linux distribution and development environment for Xilinx devices

Boot loader, Linux kernel, file system, bitstream Full End-to-End Linux Development Tools
Customize, Configure, Build, Deploy, Debug, Trace
Xilinx Supported
Custom Hardware Aware
Integrated within the Xilinx hardware design flow

Fully configurable and modifiable for customer-specific designs
Integrates with Xilinx SDK

Adds PetaLinux tools for custom device drivers, BSP, libraries, and system configurations
PetaLinux SDK
Full Linux OS Development Environment

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Hardware IP Design
Design, Analyze, and Implement your Custom Hardware IP Enter your Design
Develop with VHDL/Verilog Add existing RTL Sources Define Pin & Timing Constraints
Analyze your Design

Analyze for placement and routing, power, timing and BER
Implement your Design

Generate Netlist and Bitstream
PlanAhead Design Tool

Rapid Design Entry, Analysis and Implementation
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Simulation & Hardware/Software Co-Debug
Simulators for every use case

Fast functional for software development Cycle accurate for hardware development HW/SW co-simulation for co-development
Xilinx SDK
Xilinx iSim
Simulation for hardware debug, power and timing
analysis
Xilinx ChipScope Pro

For concurrent HW/SW debug
Chipscope Analyzer
Simulation and HW/SW Co-support Across a Number of Use Cases

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Programmers View of Programmable Logic

Simple memory mapped Interface
Programmers View of Custom Accelerators & Peripherals
Start Address
0x0000_0000
Start Address
0x4000_0000
Description
Accelerator #1 (Video Scaler) Accelerator #2 (Video Object Identification) Peripheral #1 (Display Controller)
Description
0x6000_0000 External DDR RAM 0x8000_0000 Custom Peripherals (Programmable Logic including PCIe)
0x4000_0000
Code Snippet
int main() { int *data = 0x1000_0000; int *accel1 = 0x4000_0000;
0xE000_0000
Fixed I/O Peripherals Fixed Internal Peripherals (Timers, Watchdog, DMA, Interconnect) Flash Memory On-Chip Memory
// Pure SW processing
Process_data_sw(data);
0xF800_0000
0xFC00_0000 0xFC00_0000
// HW Accelerator-based processing
Send_data_to_accel(data, accel1); process_data_hw(accel1); Recv_data_from_accel(data, accel1); }
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Platform Solutions
Segment Solutions
Segment Solutions
Page 24

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Comprehensive Partnership Ecosystem
Software Tools
Intellectual Property
Software OS & Middleware
System Architecture
Design Services
Over 100 Zynq Specific Partners and Growing

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Comprehensive Operating Systems Offering
More than 95% of commercial embedded operating systems supported on Zynq-7000 Scalable solution ranging from Real Time Operating Systems to fully featured Operating Systems Safety critical certifications in key industry segments Multi-core support in SMP and AMP mode Robust open source initiative for Linux and Android
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Strong Embedded Linux Offering
Open Source
Available on Xilinx GIT tree since July 2010 (EA) Available on main GIT tree since October 2011 Wiki at http://wiki.xilinx.com Forums at http://forums.xilinx.com
from Xilinx
Petalinux WindRiver Linux Yocto Project Compatible
Commercial
from Partners
MontaVista Linux Carrier Grade Linux LinuxLink More to come
Xilinx Acquired Petalogix in Aug. 2012 to Strengthen its Linux Offering

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Numerous SW Development Tool Options
In addition to Xilinx free SDK

Highly optimized ARM compilers from partners Advanced software development tools from world-class partners offering software profiling and tracing solutions
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Platform Solutions
Segment Solutions
Segment Solutions
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Zynq Safety and Security

Safety and security are addressed across every system element and every operational phase Hardware
Anti-tamper Trust Information Assurance
Secure System Boot

ROM Code Boot loader OS Image
Software Execution
Protect real-time applications Protect secure processes & data Isolate accelerators & IP cores
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Vivado Electronic System Level Design

Fastest path from Algorithm to Implementation
Algorithmic Specification
Algorithm modeling
Algorithm implementation
Data type and interface abstraction
C, model based accelerated verification

.
Vivado High-Level Synthesis

C, C++ or SystemC
Algorithmic Specification
Micro Architecture Exploration
VHDL or Verilog
RTL Implementation
System IP Integration
Comprehensive Integration with the Xilinx Design Environment
Accelerates Algorithmic C to RTL IP integration

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HLS Accelerates Verification Productivity

Conventional HDL-based approach C-based Approach Seconds per iteration
Functional Verification Using HDL simulation
Functional Verification with C Compiler
Hours-days per iteration

RTL RTL
Final Validation
Verified RTL
Optical flow video example Input 10 frames of video data RTL Simulation Time ~2 days
Verified RTL
C Simulation Time 10 seconds
Acceleration ~12,000X
>100x Faster C-based Acceleration Verification

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Vivado HLS Support in System Generator

Generate C based block Add C based block Start designing with C based blocks
Integrate your algorithmic C based blocks in System Generator

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Platform Solutions
Segment Solutions
Segment Solutions
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Comprehensive Offering of Segment Solutions

Many segment solutions available from Xilinx and its partners
Base foundations of many customer designs
Leveraged / implement by customers across the globe
Solutions contain (part or all):

Boards (+ expansion modules)
FPGA IP cores
Application notes Reference designs Operating systems SW drivers
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Camera Based Driver Assistance

Zynq Zynq-7000 device function
Image Capture & Transform
Feature A,B,C,D Application SW

Object Classification Motion Estimation
Image Warp and Stitch Object Detection
System Interface & Control including vehicle communication, system state , diagnostics & application watch dog Feature Application Code including feature implementation, image analysis & manipulation coprocessing, 2D graphic/overlay generation
HW Acceleration
Available Solutions
Boards
ZC702, ZC706 Complete TDP with Xylons logiADAK Complete IP solution from Xilinx Premier Alliance Members Xylon & DDC inc. Surround View, Pedestrian Detection, Lane Departure Warning, Blind Spot Detection Full Design frame work from Xylon Calibration Software
Zynq Value Proposition

3 Chips 2 Chip
IP Cores
System Perf
BOM Cost
Total Power
>130%
- 25%
- 50%
Reference Designs OS and SW Drivers

Page 37
TDP Kit = Vehicle Demo in Weeks
SW drivers, APIs & post processing libraries all available from Xylon
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Accelerated Design Accelerated Design Productivity
Mid to Portable Ultrasound Platform

RAM SD
Zynq-7000 device function

Beamforming, image enhancement, HMI System Management Connectivity and display
A/D
Zynq-7000
LCD
Flash
HMI
Available Solutions
Boards
ZC702 and ZedBoard JESD204B DSP Function Library (CORDIC, CIC, FFT) DUC/DDC Design JESD204B Design WP378, Xilinx in Portable Ultrasound VxWorks, QNX Drivers for all IP Windows Embedded
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2 Chips 1 Chip
IP Cores
System Perf
BOM Cost
Total Power
Reference Designs & Application Notes OS and SW Drivers

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50%
10-25%
Use of Vivado HLS JESD204B
> 45%
Accelerated Design Accelerated Design Productivity
Xilinx Small Cell SoC Solutions

1x20MHz 2x2 LTE Picocell
Zynq-7045 Zynq-7000 device function
Memory
Mem if
Dual Core A9 Processor (L2/L3 stack)
DPD
DDC
CFR DUC
Flexible programmable logic for L1 baseband, DFE functions, and Ethernet backhaul & timing Fabric-based hardware acceleration for L2 offload High performance dual core ARM processors for L2/L3 protocol stack, modem control, O&M, custom applications (e.g. RRM/SON)
Optical Module Optical Module
GbE
JESD204 SerDes
Xilinx 7 Solution
GbE
L1 w/ L2 offload (IPSec, Cryto, etc)
JESD204 SerDes
Abundant I/O interfaces for GPS, Wi-Fi (11n & ac)
Available Solutions
Boards
ZC706 ADI RF Board LTE L1 Baseband DFE functions DUC/DDC, DPD, CFR JESD204A/B Ethernet Backhaul Management & Timing

3 devices 1 device
IP Cores
System Perf
BOM Cost
Total Power
Reference Designs OS and SW Drivers
2x
LTE Picocell reference design
-25%
-35%
Linux, OSE
Scalable & Flexible Modem, Comprehensive Baseband and IP Solutions, Reference Designs, and Design Services
Accelerated Design Productivity
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Zynq-7000 AP SoC Value Proposition

ASIC
Performance Power Unit Cost
ASSP
2 Chip Solution
Zynq-7000
+ + +
+ + +
+ +
TCO
Risk TTM Flexibility Scalability
+ + +
+ + + + +
negative, neutral
+ + + + +
+ positive, Page 40
Conflicting Demands Now Served by the Zynq-7000 Family

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Summary
Best match for conflicting demands
In most cases the chosen option
Strong Momentum in all Market Segments World Wide

Adoption beyond traditional FPGA users
Comprehensive Platform Offering Beyond Silicon

Xilinx and partner boards Broad OS offering with strong emphasis on Linux (commercial and open source) TDPs available for all key market segments
System solutions starting to rollout

Security and safety
Availability
Family is in full production
With Zynq-7000 AP SoC, Xilinx offers more than silicon it offers SOLUTIONS
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Zynq-7000 - A Breakthrough in Integration of All Programmable Soc

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Zynq-7000 A Breakthrough in Integration of All Programmable SoC

Guy Lampert Xilinx April 2013

Copyright 2013 Xilinx

Demands of Today's Technology

Which Technology Should I Choose?

Copyright 2013 Xilinx

Current Selections Equal Compromise

+ positive, - negative, neutral

Copyright 2013 Xilinx

BDTI HLS Tool Certification Program

BDTI Key Findings:

Copyright 2013 Xilinx Copyright 2012 Xilinx

Xilinx Technology Evolution

Programmable Logic Devices

All Programmable Devices

Copyright 2013 Xilinx

Why All Programmable?

Programmable Systems Integration

BOM Cost Reduction

Total Power Reduction

Accelerated Design Productivity

Build better electronic systems with fewer chips.faster!

Copyright 2013 Xilinx

The First All Programmable SoC

Copyright 2013 Xilinx

Xilinx Pioneered the All Programmable SoC

Executed by delivering tools, samples and enabling eco-system Momentum

Safe choice with a comprehensive offering already in existence today

Zynq Product Announcement OS & Tools

First Customer Shipment

Security & Safety Enablement

Copyright 2013 Xilinx

Zynq-7000 Block Diagram

System Gates, DSP, RAM S_AXI_HP0 S_AXI_HP1 S_AXI_HP2 S_AXI_HP3 S_AXI_ACP

NEON/ FPU Engine Cortex-A9 MPCore 32/32 KB I/D Caches

256 KB On-Chip Memory

Switches Switches AMBA AMBA

Multi-Standards I/Os (3.3V & High Speed 1.8V)

Multi Gigabit Transceivers

Copyright 2013 Xilinx

Complete ARM-based Processing System

On-Chip Memory of 256KB Integrated Memory Controllers

AMBA Open Standard Interconnect Integrated Memory Mapped Peripherals

Processing System Ready to Program

Copyright 2013 Xilinx

Tightly Integrated Programmable Logic

Over 3000 Internal Interconnects

Integrated Analog Capability

Enables Massive Parallel Processing

Scalable Density and Performance

Copyright 2013 Xilinx

Flexible External I/O

73 Dedicated Memory I/Os

Up to 400 Multi-Standard and High Performance I/O

High Performance Integrated Serial Tranceivers

Flexibility Beyond Any Standard Processing Offering

Copyright 2013 Xilinx

Zynq-7000 Device Portfolio

Dual ARM Cortex-A9 MPCore

Processor Extensions Max Frequency Memory External Memory Support Peripherals

~430K (28k LC) 240KB 100 GMACS -

~5.2M (350k LC) 2,180KB 1334 GMACS

~6.6M (444kLC) 3,020KB 2662 GMACS