Understanding the Desktop NanoBoard NB2DSK01 Constraint System

The process of mapping or constraining a design to its physical implementation is done by creating constraint files files that specify implementation detail such as the target device, the port-to-pin mapping, pin IO standards and so on. The minimum information required to synthesize a design is the device specification. Sets of constraint files are targeted to a design by creating a configuration, which is simply a named list of constraint files. Setting up to implement a design on the NB2DSK01 is simplified through provision of constraint files as part of the installation. These can be found in the \Library\Fpga\NB2 Constraint Files folder of the installation.

Summary
This application note provides information on the constraint system in place when targeting your design to a daughter board FPGA device, plugged-in to Altium's Desktop NanoBoard NB2DSK01.

For more information on the concept of configurations and constraints, and their role in design portability, refer to the article AR0124 Design Portability, Configurations and Constraints.

Constraint System Overview

The constraint system in place for the Desktop NanoBoard NB2DSK01 utilizes various constraint files covering: Resources and pin-mapping local to the NB2DSK01 motherboard and satellite peripheral and daughter boards Connection of a satellite board (peripheral boards and daughter boards) to the NB2DSK01 motherboard.

Figure 1 indicates the base set of constraint files used for a design targeting a daughter board FPGA device plugged into the NB2DSK01 motherboard and where that design utilizes additional peripherals located across all three plug-in peripheral boards.

E
HDR1 HDR_T

HDR_L

A F F
HDR_B

Peripheral Board Peripheral Board PBxx Peripheral Board PBxx PBxx

Daughter Board DBxx

EXTHDR3 HDR_T1 HDR_L1 EXTHDR1 EXTHDR2 HDR_B1

NB2DSK01 Motherboard

Figure 1. Constraint files used for a design targeted to the NB2DSK01. Version (v2.0) May 15, 2008

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Table 1 summarizes these base constraint files. Together, they ultimately map the resources available (on motherboard, daughter board and peripheral boards) to the physical pins of the daughter board FPGA. For information on the Desktop NanoBoard NB2-DSK1, refer to the document TR0143 Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01. For information on the complete range of peripheral boards and daughter boards currently available, and additional documentation specific to each, go to www.altium.com/nanoboard/resources.
Table 1. Constraint file descriptions.

Constraint File A B C D

Targets Peripheral board PBxx Peripheral board PBxx Peripheral board PBxx NB2DSK01 motherboard

Description Defines the peripheral board and its connector, as well as the mapping of all resources on that board to pins of that connector.

Defines the NB2DSK01 motherboard and its connectors (daughter board, peripheral board and user board); the mapping of pins between peripheral board connectors and daughter board connectors; and the mapping of all NB2DSK01 motherboard resources to pins of the daughter board connectors. Defines the daughter board and FPGA device, the connectors available on that board, and the pin mapping between those connectors and pins of the physical device. The mapping of any other resources on the daughter board, available for use by the FPGA design (e.g. memories), is also specified in this file. Declares the following: NanoBoard instance Daughter board instance Peripheral board instance(s) Daughter board-to-motherboard connector mapping Peripheral board-to-motherboard connector mapping.

Daughter board DBxx

Peripheral board-tomotherboard and daughter board-to-motherboard interfaces

Notes: 1. Additional constraint files may be included/used, such as a file for timing-related constraints. 2. Constraint file F in Figure 1 and Table 1 is commonly referred to as the 'Board Mapping constraint file'. It does not exist as part of the installation, but rather is created on-the-fly, in accordance with the hardware in the system. 3. Depending on the resources being used by your design and the number of peripheral boards plugged into the NB2DSK01 motherboard, your FPGA project may contain up to three peripheral board-related constraint files, one per board. 4. If your FPGA project has multiple configurations targeting different daughter board FPGA devices there will be a daughter board-related constraint file for each different device targeted. The different configurations will contain these different constraint files. A different mapping constraint file will also be generated for, and assigned to, each unique configuration.

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Configuring an FPGA Project Automatically

Although an FPGA design project targeting the Desktop NanoBoard NB2DSK01 can be configured manually by adding a configuration, assigning the required board constraint files and creating a mapping constraint file by hand the process is greatly simplified through use of an auto-configuration feature. Using this feature, a target configuration for the FPGA design project is automatically created. The required board-level constraint files are then automatically determined and added to this configuration, based on the hardware (motherboard, daughter board and peripheral boards) detected in your system. An additional board mapping constraint file is also generated and added to the configuration, which handles connection of the satellite boards detected in the system (daughter board and any peripheral boards), to the main motherboard.

Identifying System Hardware

Before taking a closer look at the auto-configuration procedure itself, it is a good idea to understand the technology by which such automatic configuration of the system is made possible. The key to being able to configure an FPGA design project automatically, is the ability of Altium Designer to identify the specific hardware you are currently using in your system. Identification is made possible through the use of memory devices, located on: the NB2DSK01 motherboard the daughter board each peripheral board the Desktop Stereo Speaker Assembly NB2DSK-SPK01 (though not used for auto-configuration purposes).

The device used on each board a DS2406 from Maxim is a 1-Wire compatible device. The NanoTalk Controller interrogates the DS2406 on each board over a single wire, resulting in the presence of six 1-Wire buses used for system identification purposes. Figure 2 illustrates the 1-Wire board identification system in place for the Desktop NanoBoard NB2DSK01.
Peripheral Board A ID Motherboard ID

PBxx.nn
1-Wire Memory

NB2DSKxx.nn
1-Wire Memory

Peripheral Board B ID

Speaker Board ID

PBxx.nn
1-Wire Memory

FIRMWARE

NB2DSK-SPKxx.nn
1-Wire Memory

NanoTalk Controller

Peripheral Board C ID

Daughter Board ID

PBxx.nn
1-Wire Memory

DBxx.nn
1-Wire Memory

Figure 2. 1-Wire board identification system for the NB2DSK01.

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Each 1-Wire memory device is pre-programmed with an Altium Board Identifier string. This string is 32 bytes long and can be represented as: <UniqueID><ClassID><BatchID><VendorID> The four components of the string are defined in the following sections.

UniqueID
<UniqueID> is an 8 byte code programmed by the manufacturer to guarantee a unique device. The 64 bits of this code are made up of three distinct parts. The first 8 bits provide the 1-Wire family code, the next 48 bits provide the serial number which is unique to each device. The last 8 bits provide a cyclic-redundancy-check of the first 56 bits. The full 64-bit code is stored in, and accessed from, a separate ROM within the device.

ClassID
<ClassID> is a 16 byte (hex-coded ASCII) ident for the board upon which the 1-Wire memory device resides. The string consists of the board code and the board revision, separated by a full stop. Right-padding using space characters (20h) ensures the length is kept to 16 bytes. These 16 bytes are stored in, and accessed from, Page 0 of the DS2406's data memory (EPROM) in the address range 0000h 000Fh. Table 2 illustrates example coding for the motherboard, a daughter board and a peripheral board.
Table 2. Example <ClassID> strings.

Board

<ClassID> Format

Example Information

Resulting 16 Bytes entered into DS2406's EPROM

Motherboard Daughter Board Peripheral Board Speaker Board

NB2DSKxx.nn DBxx.nn PBxx.nn NB2DSK-SPKxx.nn

NB2DSK01.08 DB30.06 PB01.07 NB2DSK-SPK01.07

4E 42 32 44 53 4B 30 31 2E 30 38 20 20 20 20 20 44 42 33 30 2E 30 36 20 20 20 20 20 20 20 20 20 50 42 30 31 2E 30 37 20 20 20 20 20 20 20 20 20 4E 42 32 44 53 4B 2D 53 50 4B 30 31 2E 30 37 20

BatchID
<BatchID> is a 4 byte ident for the production run. These four bytes are stored in, and accessed from, Page 0 of the DS2406's data memory in the address range 0010h 0013h.

VendorID
<VendorID> is a 4 byte ident for who made the board. This value is 00000001h for all Altium manufactured boards. These four bytes are stored in, and accessed from, Page 0 of the DS2406's data memory in the address range 0014h 0017h.
Note: The remaining 8 bytes in Page 0 of the device's data memory (address range 0018h - 001Fh) are left blank (contain FFh)

For more information on the DS2406 device, refer to the datasheet (DS2406.pdf) available at www.maxim-ic.com. For a high-level overview of the 1-Wire bus protocol, refer to the application note (AN3989.pdf), also available at www.maxim-ic.com. In terms of auto-configuration, it is the <ClassID> portion of the string that empowers the feature, as it is this string that determines the constraint file required in relation to a board. Information on how these IDs are used in populating a configuration with the necessary constraint files is covered in the next section.

Configuring the Project

Prior to using the auto-configuration feature, ensure the following:

The daughter board carrying the FPGA device to which the design is targeted is plugged into the NB2DSK01 motherboard. Any peripheral boards carrying resources used by the FPGA design are also plugged into the NB2DSK01 motherboard. Peripheral boards whose resources are not actually used can be left attached to the motherboard, or removed, as required. The NB2DSK01 is connected to the PC (via parallel or USB connection) and is powered-on.

The auto-configuration feature can be used to create the configuration for any chosen FPGA project that is currently open (in the Projects panel). Alternatively, it can be used to create the configuration and add it to a newly-created FPGA project.

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Access to the feature can be made in two ways:

Right-click on the icon for the NB2DSK01, in the NanoBoard chain of the Devices view (View Devices View). Use the Configure FPGA Project sub-menu to choose the specific FPGA design project to be configured, or choose New FPGA Project. In the latter case, a dialog will appear from which you can determine where, and under what name, the new project will be saved. From the NanoBoard Configuration dialog (Figure 4). To access Figure 3. Auto-configure direct from Devices view. this dialog, double-click on the icon for the NB2DSK01 to access its corresponding instrumentation in the Instrument Rack NanoBoard Controllers panel. Then click on the Board View button. Alternatively, right-click on the NB2DSK01 icon and choose View Configuration from the menu.

By using the dialog, you are presented with a visual summary of your current Desktop NanoBoard NB2DSK01 system. The image in the dialog displays the specific peripheral board(s) and daughter board that are physically plugged in to the NB2DSK01 motherboard. The dialog is dynamic refreshed on access. So if you remove the daughter board, or switch positions of peripheral boards, the new physical setup will be displayed when you next access the dialog. The dialog also provides information relating to the Altium Board Identifier string for:

The NB2DSK01 motherboard (located over the TFT LCD panel) The daughter board (if plugged in) The peripheral board plugged in to the 'PERIPHERAL BOARD A' connector (if present) The peripheral board plugged in to the 'PERIPHERAL BOARD B' connector (if present) The peripheral board plugged in to the 'PERIPHERAL BOARD C' connector (if present)

Figure 4. Accessing the NanoBoard Configuration dialog and its visual summary of the physical hardware present in the system. Version (v2.0) May 15, 2008

AP0154 Understanding the Desktop NanoBoard NB2DSK01 Constraint System

Use the Auto Configure FPGA Project drop-down at the bottom-left of the dialog to choose the existing (open) project to configure, or to create a new project to which the configuration will be added. Whichever method of access is used, the auto-configuration process proceeds in exactly the same way. First, a configuration is created and named using the format:
motherboard code_revision_daughter board code_revision
Figure 5. Auto-configure from the NanoBoard Configuration dialog.

For example, with a Desktop NanoBoard NB2DSK01 (revision 8), and a Xilinx Spartan-3 daughter board DB30 (revision 6), the configuration will be named NB2DSK01_08_DB30_06. Constraint files will then be added to the configuration for each of the detected boards in the system (motherboard, daughter board and peripheral board(s)). These are sourced from the \Library\Fpga\NB2 Constraint Files folder of the installation. In each case, the file used will be determined by the <ClassID> component of the board's Altium Board Identifier string. So if you are using peripheral board PB02 (revision 6), with <ClassID> = PB02.06, then the constraint file retrieved and added to the configuration will be PB02.06.Constraint. The constraint file that defines the mapping of daughter board and peripheral board(s) to the motherboard is also created, onthe-fly, and added to the configuration. This corresponds to constraint file F in Figure 1 and Table 1. The name of this file will simply be that of the configuration itself, with the additional suffix '_BoardMapping' (e.g. NB2DSK01_08_DB30_07_BoardMapping.Constraint). The file will be saved to the same location as the project file (*.PrjFpg) itself.
Note: _BoardMapping.Constraint files do not exist in the \Library\Fpga\NB2 Constraint Files folder of the installation. To manually create such files would be time-consuming, in addition to manually identifying which boards are present in the system and sourcing the relevant constraint files by hand. The auto-configuration feature delivers these files, and configuration, in literally a 'blink-of-an-eye', freeing you to concentrate on other important aspects of your design.

The configuration and assigned constraint files are listed in the subsequent Configuration Manager dialog that appears for the project (Figure 6).

Figure 6. Resulting configuration and constituent constraint files (auto-configuration-related files will be automatically assigned).

Use the dialog to add any other constraint files for the project as required, and assign them to the configuration. If you already had constraint files added to the project for example to handle timing constraints these will appear listed in the Configuration Manager dialog, but will not automatically be assigned to the configuration generated by the auto-configuration process.

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Following a Signal Trail

Perhaps the most useful way to illustrate the constraint system is by example. To highlight the mapping involved between each constituent part of the system, we will follow the trail of a couple of example signals, related to the video output resource on the peripheral board PB01:
VGA_VSYNC VGA_HSYNC

Let us assume that the NanoBoard system is comprised of the following: A Desktop NanoBoard NB2DSK01 (revision 8) A Xilinx Spartan-3 daughter board, DB30 (revision 6) An Audio-Video peripheral board, PB01 (revision 7) attached to the motherboard using the 'PERIPHERAL BOARD C' connector.

After using the auto-configuration feature (see Configuring an FPGA Project Automatically, earlier in this document), the configuration NB2DSK01_08_DB30_06 will be created, along with the following assigned constraint files:
NB2DSK01.08.Constraint DB30.06.Constraint PB01.07.Constraint NB2DSK01_08_DB30_06_BoardMapping.Constraint

The following sections take a closer look at each of these constraint files, while at the same time keeping track of our two example signals, as they are mapped from the PB01 to the physical pins of the FPGA device on the DB30.

Peripheral Board Constraint File

The PB01.07.Constraint file defines the peripheral board:
Record=Constraint | TargetKind=PCB | TargetId=PB01.07 | Image=PB01.07 | ImageOffsetX=10 | ImageOffsetY=13 | Description=Audio/Video Peripheral Board

its connector:
Record=Constraint | TargetKind=Connector | TargetId=HDR1

and the mapping of on-board resource signals to that connector. For our example signals, the entries in the file appear as:
Record=Constraint | TargetKind=Port | TargetId=VGA_VSYNC | ConnectTo=HDR1-100 Record=Constraint | TargetKind=Port | TargetId=VGA_HSYNC | ConnectTo=HDR1-98

Peripheral Board-to-Motherboard Interface Mapping

The NB2DSK01_08_DB30_06_BoardMapping.Constraint file contains information that is used to map the peripheral board to one of the peripheral board connectors on the NB2DSK01 motherboard. The file and its content is created on-the-fly, based on the actual physical location of the peripheral board (in our example, attached to the motherboard using the 'PERIPHERAL BOARD C' connector). The file includes a declaration for the motherboard and peripheral board instances:
Record=Constraint | TargetKind=PCBInstance | TargetId=NB2DSK01_08 | PCB=NB2DSK01.08 Record=Constraint | TargetKind=PCBInstance | TargetId=PB01_07 | PCB=PB01.07

and the connector mapping between the two:

Record=Constraint | TargetKind=ConnectorMap | TargetId=PB01_07.HDR1 | ConnectTo=NB2DSK01_08.EXT_C

Note: The PCB instance and connector names for the peripheral board and motherboard are the same as those defined in the PB01.07.Constraint and NB2DSK01.08.Constraint files respectively.

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With regard to our two example signals (VGA_VSYNC, VGA_HSYNC), we can see that they have left the peripheral board (HDR1100 and HDR1-98) and are now available on the motherboard's 'PERIPHERAL BOARD C' connector (EXT_C-100 and EXT_C-98).

Motherboard Constraint File

The NB2DSK01.08.Constraint file declares the NanoBoard:
Record=Constraint | TargetKind=PCB | PCB=NB2DSK01.08 | Image=NB2DSK01.08

the plug-in boards:

Record=Constraint | TargetKind=PlugIn | TargetId=DB ImageOffsetY=225 | ImageRotation=0 Record=Constraint | TargetKind=PlugIn | TargetId=EXT_A | IdIndex=2 | ImageOffsetX=17 ImageOffsetY=254 | ImageRotation=0 Record=Constraint | TargetKind=PlugIn | TargetId=EXT_B | IdIndex=3 | ImageOffsetX=183 | ImageOffsetY=254 | ImageRotation=0 Record=Constraint | TargetKind=PlugIn | TargetId=EXT_C | IdIndex=4 | ImageOffsetX=323 | ImageOffsetY=217 | ImageRotation=180 | | IdIndex=1 | ImageOffsetX=423 |

its connectors:
Record=Constraint | TargetKind=Connector | TargetId=HDR_T | PlugIn=DB | Index=0 Record=Constraint | TargetKind=Connector | TargetId=HDR_B | PlugIn=DB | Index=1 Record=Constraint | TargetKind=Connector | TargetId=HDR_L | PlugIn=DB | Index=2 Record=Constraint | TargetKind=Connector | TargetId=EXT_A | PlugIn=EXT_A Record=Constraint | TargetKind=Connector | TargetId=EXT_B | PlugIn=EXT_B Record=Constraint | TargetKind=Connector | TargetId=EXT_C | PlugIn=EXT_C Record=Constraint | TargetKind=Connector | TargetId=USER_A Record=Constraint | TargetKind=Connector | TargetId=USER_B

and the peripheral board connector-to-daughter board connector pin mapping. For our two signals we've been tracking, which arrive at EXT_C pin 100 (VGA_VSYNC) and EXT_C pin 98 (VGA_HSYNC), the constraint file entries appear as:
Record=Constraint | TargetKind=Connection | TargetId=EXT_C-100 | ConnectTo=HDR_T-2 Record=Constraint | TargetKind=Connection | TargetId=EXT_C-98 | ConnectTo=HDR_T-4

This constraint file also contains the mapping of resources local to the motherboard, to pins of the daughter board connectors, for example:
Record=Constraint | TargetKind=Port | TargetId=CAN_TXD | ConnectTo=HDR_T-16 Record=Constraint | TargetKind=Port | TargetId=CAN_RXD | ConnectTo=HDR_T-14

Daughter Board-to-Motherboard Interface Mapping

The NB2DSK01_08_DB30_06_BoardMapping.Constraint file is again used to map the docking connectors on the daughter board to the corresponding connectors on the NB2DSK01 motherboard. The file includes a declaration for the motherboard and daughter board instances:
Record=Constraint | TargetKind=PCBInstance | TargetId=NB2DSK01_08 | PCB=NB2DSK01.08 Record=Constraint | TargetKind=PCBInstance | TargetId=DB30_06 | PCB=DB30.06

and the connector mapping between the two:

Record=Constraint | TargetKind=ConnectorMap | TargetId=DB30_06.HDR_B | ConnectTo=NB2DSK01_08.HDR_B Record=Constraint | TargetKind=ConnectorMap | TargetId=DB30_06.HDR_L | ConnectTo=NB2DSK01_08.HDR_L Record=Constraint | TargetKind=ConnectorMap | TargetId=DB30_06.HDR_T | ConnectTo=NB2DSK01_08.HDR_T

Note: The PCB instance and connector names for the daughter board and motherboard are the same as those defined in the DB30.06.Constraint and NB2DSK01.08.Constraint files respectively.

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Daughter Board Constraint File

The DB30.06.Constraint file defines the daughter board:
Record=Constraint | TargetKind=PCB | TargetId=DB30.06 | Image=DB30.06 | ImageOffsetX=58 | ImageOffsetY=131 | Description=Xilinx Spartan 3 XC3S1500-FG676C

its physical FPGA device:

Record=Constraint | TargetKind=Part | TargetId=XC3S1500-4FG676C

its connectors:
Record=Constraint | TargetKind=Connector | TargetId=HDR_T | Index=0 Record=Constraint | TargetKind=Connector | TargetId=HDR_B | Index=1 Record=Constraint | TargetKind=Connector | TargetId=HDR_L | Index=2

and the mapping from pins of those connectors to pins of the physical FPGA device. For our two signals we've been tracking, which arrive at HDR_T pin 4 (VGA_HSYNC) and HDR_T pin 2 (VGA_VSYNC), the constraint file entries appear as:
Record=Constraint | TargetKind=Connection | TargetId=HDR_T-4 | FPGA_PINNUM=A8 Record=Constraint | TargetKind=Connection | TargetId=HDR_T-2 | FPGA_PINNUM=B8

This constraint file will also contain the mapping of resources local to the daughter board, and which are available for use by the FPGA design. For the Xilinx Spartan-3 daughter board, DB30, this includes the various on-board memories, for example:
Record=Constraint | TargetKind=Port | TargetId=BUS_RAM_NCS | FPGA_PINNUM=E12 | FPGA_SLEW=FAST Record=Constraint | TargetKind=Port | TargetId=BUS_NWE Record=Constraint | TargetKind=Port | TargetId=BUS_NOE | FPGA_PINNUM=L25 | FPGA_SLEW=FAST | FPGA_PINNUM=B19 | FPGA_SLEW=FAST

Overall Mapped Signal Path

By following the system's elemental constraint files in the correct sequence, we can easily piece together the full mapped signal path from any resource on a peripheral board, the motherboard, or a daughter board to the physical pin on the applicable daughter board's FPGA device. Table 3 summarizes the generic sequence of constraint files used to follow a signal, depending on where the corresponding resource is located.
Table 3. Constraint file sequences used to obtain fully mapped signal path.

For a resource located on...

Use the following constraint file sequence to obtain fully mapped signal path...

Peripheral Board NB2DSK01 Motherboard Daughter Board

Peripheral Board Board Mapping NB2DSK01 Board Mapping Daughter Board NB2DSK01 Board Mapping Daughter Board Daughter Board

Note: The specific peripheral board and daughter board constraint files used will depend on the peripheral board on which a resource resides, and the daughter board plugged into the NB2DSK01 motherboard. The Board Mapping constraint file generated is dependent on the boards used in your NanoBoard system.

For our underlying example used in the previous sections, the video resource is located on a peripheral board, meaning that the two signals under study pass through all four constraint files before ultimately arriving at the pins of the FPGA device. Figure 7 illustrates graphically, the overall path for these two signals, in terms of the relevant constraint files that they pass through.

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Peripheral Board Constraint File

Interface Mapping Constraint File

NB2DSK01 Motherboard Constraint File

Interface Mapping Constraint File

Daughter Board Constraint File

HDR1

EXT_C

HDR_T

HDR_T

VGA_HSYNC Video Output VGA_VSYNC

98 100

98 100

4 2

4 2

A8 B8

Xilinx Spartan-3 FPGA

Figure 7. Fully mapped signal paths for the example signals (VGA_HSYNC and VGA_VSYNC).

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Revision History
Date 01-Nov-2007 17-Dec-2007 15-May-2008 30-Aug-2011 Version No. 1.0 1.1 2.0 Revision Initial release Updated for Altium Designer 6.9 Updated for Altium Designer Summer 08 Updated template.

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