CHAPTER 1 INTRODUCTION

Microprocessors and Microcontrollers have traditionally been designed around two philosophies: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). The CISC concept is an approach to the Instruction Set Architecture (ISA) design that e phasi!es doing wide variety o" addressing ore with each Instruction using a odes# variable nu ber o" operands in various locations in

its Instruction Set. As a result# the Instructions are o" widely varying lengths and e$ecution ti es thus de anding a very co ple$ Control %nit# which occupies a large real estate on chip. &n the other hand# the RISC 'rocessor wor(s on reduced nu ber o" Instructions# "i$ed instruction length# si pli"ied addressing ore general)purpose registers# load)store architecture and a(es individual instructions e$ecute "aster# achieve ore roo to add on)chip a(e the odes which

a net gain in per"or ance and an overall si pler design with less silicon consu ption as co pared to CISC. This gives the RISC Architecture peripherals# interrupt controllers and progra ar(et * the +system-on-a-chip+. &ur ain ob,ective is to design an -.)/it Microprocessor. The Instruction cycle able ti ers. The above "eatures

RISC design ideally suited to participate in a power"ul trend in the e bedded 'rocessor

consists o" three stages na ely "etch# decode and e$ecute. A"ter every instruction "etch# Control %nit generate signals "or the selected Instruction. &ur architecture supports .0 instructions. They can be broadly classi"ied into Arith etic# 1ogical# Shi"ting and Rotational Instructions.

1.1 Aim of the Project The ob,ective o" the pro,ect is to design a -.)bit 3loating 'oint RISC processor. It is to be designed to per"or operations. This processor processor between the design and the ust incorporate a a co plete set o" -.)bit arith etic "loating point e ory within it to restrict the peripheral interaction ust e$ecute all the operations in a single cloc( cycle. The e ory. This is to achieve "aster e$ecution o" cycles.

In order to I ple ent the -.)/it 3loating point RISC 'rocessor# the "ollowing e$peri ental procedure has been adopted 2. 3or the devised logic 4561 code "or various Resetter# C1%# A1%# 'C# IR# M%8 is developed. .. /y using Active 561 Si ulation so"tware tool# the code developed has been si ulated. odules li(e Cloc( 7enerator#

1.2 Technical Approach Architectural design o" a -.)bit "loating point RISC processor "ro 9 /ehavioral odeling o" 6esign bloc(s. odules to test the "unctionality o" 6esign bloc(s. Speci"ications.

9 6esign o" sti ulus

9 Synthesi!e design to e$tract 7ate level net list. This RISC 'rocessor is designed to incorporate .0 basic instructions

involving Arith etic# 1ogical# 6ata Trans"er# Control instructions and 3loating 'oint arith etic operations. To i ple ent these instructions the design incorporates various design bloc(s li(e Control 1ogic %nit (C1%)# Arith etic 1ogic %nit (A1%)# Multiple$er# Accu ulator# 'rogra Counter ('C)# Instruction Register (IR)# Me ory# Cloc( 7enerator# Resetter and additional glue logic li(e bu""er# &R gate. The Instruction "or at contains "irst "ive MS/:s as &'C&6; and re aining .< bits as A66R;SS /%S. It can address 2.= Mbytes o" /i)directional 6ata bus. e ory locations and a -.)bit

The 'rocessors includes the "ollowing instructions: Arith etic 1ogical Control 6ata trans"er 3loating 'oint To su : : : : : A66# S%/# I>R# 6CR. A>6# &R# 8&R# 8>&R# 1S5I3T# RS5I3T# CMA ?%M'# S@I'# 51T 16A# STA 3A66# 3S%/# 3M%1# 36I4.

ari!e# the RISC is designed to enhance processor per"or ance by (eeping the ind. ust use si ple constructs and

"ollowing design goals in

The RISC (Reduced Instruction Set Co puter)

have s all instruction set co pared to CISC (Co ple$ Instruction Set Co puter) 'rocessors. It is designed to achieve "aster e$ecutions. The stri(ing "eature o" a RISC is that# it e$ecutes each instruction within one cloc( cycle. This is achieved by carrying out ost o" the operations within the 'rocessor and ini i!ing the use o" operations reAuiring slower peripherals. Its architecture si pli"ies the instruction set and encourages the opti i!ation o" register anipulation. Al ost all instructions have si ple Register addressing. An i portant aspect o" the instruction set is that it is easy to decode (3i$ed length instruction "or at). Thus the &pcode and Instruction Register "ields can be accessed si ultaneously. 6ue to the si pli"ication o" instructions and their "or at# control logic design is "urther si pli"ied.

1.3 Or ani!ation of The"i" This thesis is divided into "ive parts. Chapter 1 is introduction. Chapter 2 is -.) /it RISC 'rocessor# here the concepts are discussed RISC "eatures# Introduction to 'rocessors and Co parative studies o" CISC and RISC. Chapter 3 is design aspectsB this chapter presents indetail o" RISC 'rocessor i.e. /loc( 6iagra Me ory# /u""er. Along these o" RISC 'rocessor# Counter# odule Cloc( 7enerator# Resetter# Control 1ogic 6ecoder# IR# A1%# M%8# 'rogra si ulation results# introduction o" 4561 language# -.)/it RISC 'rocessor "inally appendi$ and bibliography included.

odules the 4561 Code included. Chapter 4 is

results and description. Chapter 5 is conclusion and "uture scope o" the wor(. And

CHAPTER 2 32 # $IT RI%C PROCE%%OR

2.1 Intro&'ction This chapter presents "eatures o" RISC processor# when they ca e into real environ ent and speed with accuracy. 6i""erences between RISC processor and CISC processor and detailed description o" the -.)bit RISC processor. Advantages and 6isadvantages o" both RISC processor and CISC processor

2.2 RI%C (eat're") 'rocessors are uch "aster than e ories. 3or e$a ple# a processor cloc(ed at ight reAuire D0 e ory

200 M5! would li(e to access cloc(. %n"ortunately# the

e ory in 20 nanoseconds# the period o" its 200 M5!

e ory inter"aced to the processor

nanoseconds "or an access. So# the processor ends up waiting during each access# wasting e$ecution cycles. To reduce the nu ber o" accesses to data and the address o" the data is stored. "ro cache ain atches the address being used "or the ain

e ory# designers added instruction

and data cache to the processors. A cache is a special type o" high speed RAM where Ehenever the processor tries to read data e ory read (called a hit)# the cache will e ory# the cache is e$a ined "irst. I" one o" the addresses stored in the

supply the data instead. Cache is co only ten ti es "aster than ain e ory# so you can see the

advantage o" getting data in 20 nanoseconds instead o" D0 nanoseconds. &nly when we iss (i.e.# do not "ind the reAuired data in the cache)# does it ta(e the "ull access ti e o" D0 nanoseconds. /ut this can only happen once. Since a copy o" the new data is written into the cache a"ter a iss. The data will be there the ne$t ti e we need it. Instruction cache is used to store "reAuently used instructions.

6ata cache is used to store "reAuently used data. I ple enting "ewer instructions and addressing odes on silicon reduces the co ple$ity o" the instruction achine to be decoder# the addressing logic# and the e$ecution unit. This allows the

cloc(ed at a "aster speed# since less wor( needs to be done each cloc( period.

RISC typically has large set o" registers. The nu ber o" registers available in a processor can a""ect per"or ance the sa e way a calculation e ory during the calculations# during calculations will be any e ory access does. A co ple$ ust be used to utili!e the . ay reAuire the use o" several data values. I" the data values all reside in e ory accesses

I" the data values are stored in the internal registers o" the processor instead# their access uch "aster. It is good then to have lot o" internal registers.

Eith

icroprocessors getting "aster every year#

e ory architectures

ust also

i prove to enhance overall syste

per"or ance. Se iconductor based electronics is the

"oundation to the in"or ation technology society we live in today. ;ver since the "irst transistor was invented way bac( in 2GC=# the se iconductor industry has been growing at a tre endous pace. Se iconductor e ories and icroprocessors are two a,or "ields# which are

bene"ited by the growth in se iconductor technology. The technological advance ent has i proved per"or ance as well as pac(ing density o" these devices over the years

(i 're 1) Increa"in *emor+ capacit+ o,er the +ear"

7ordon Moore

ade his "a ous observation in 2GDF# ,ust "our years a"ter the

"irst planar integrated circuit was discovered. 5e observed an e$ponential growth in the nu ber o" transistors per integrated circuit in which the nu ber o" transistors nearly doubled every couple o" years. This observation# popularly (nown as *oore-" .a/# has been aintained and still holds true today. @eeping up with this law# the se iconductor e ory capacity also increases by a "actor o" two every year.

(i 're 2) *oore0" .a/

2.3 Intro&'ction to Proce""or" The 'C processor business shoo( o"" a wea( econo ic cli ate to grow -.2 percent in unit ship ents in the ?une Auarter# but intense price co petition drove revenues down C.F percent# according to the latest nu bers "ro Corp. Intel Corp. drove International 6ata ost o" the growth# I6C said. +IntelHs processor ship ents alone

grew nearly C.- percent Auarter)to)Auarter and .0.= percent year)on)year# while AM6Hs processor ship ents were about "lat#+ said Shane Rau# director o" I6CHs 'C chip research in a press state ent. The second Auarter is usually a low point "or the year# Rau added. >evertheless# C'% ship ents were up 2D.2 percent "ro the sa e Auarter a year ago# showing the strength o" the de and in the current period. 1oo(ing "orward# I6C predicts 'C
<

processor sales "or all .00= will grow by ,ust <.F percent to about I-..= billion. Rau cited concerns about the broader econo y despite IntelHs aggressive approach to pricing and new product introductions. Intel is on the cusp o" introducing its "irst CFn line debuting at the Intel 6eveloper 3oru o" the 'C processor processors# the des(top Core i<

later in August. Intel captured <G.< percent

ar(et on a unit basis in the Auarter# up 0.G percent. Archrival

Advanced Micro 6evices had 2G.< percent# a loss o" 2.. percent. AM6 has been losing share to Intel steadily since the third calendar Auarter o" .00< when it had .-.F percent o" the ar(et# according to I6C. Intel recorded gains in the noteboo( seg ent that now represents one o" the largest and "astest growing 'C sectors. Intel had an =D.F percent share o" the noteboo( C'% ar(et in the Auarter# up 2.- percent. 3or its part AM6 logged a 2..D percent share# down 2.G percent# and TaiwanHs 4IA Technologies had 0.G percent# up 0.< percent. AM6 had odest gains in the s aller but pro"itable wor(station ar(et rising

0.= percent to a 2-.= percent share co pared to Intel down the sa e a ount to =D.. percent. Shares stayed at <-.- percent "or Intel and .D.C percent "or AM6 in the des(top space.

2.1 Proce""or Architecher) A processor (as stated earlier) processes bits (binary digits) o" data# in its si plest "or # the processor will retrieve so e data# per"or and then store the result in either its own internal e ory. so e process on that data# e ory (cache) or the syste s

Jou

ay have seen processors advertised as -.)bit or DC)bit# this basically a(e a DC)bit processor twice as "ast as its -.)bit

eans that the processor can process internally either -. bits or DC bits o" data at any one ti e. This would theoretically counterpart.

So"tware can also be de"ined as either 2D)bit# -.)bit or DC)bit# you can probably see that theoretically i" you are using DC)bit so"tware with a -.)bit processor then it would ta(e two cloc( cycles (-.)bits at a ti e) to process any one set o" DC)bits# this is re"erred to as a bottlenec(. This 6esign veri"ication and i ple entation will be done using ;6A tools "ro the "ollowing vendors. A16;C Inc.

Simulation Tools: Active 561 "ro

2.2 Comparati,e %t'&ie" of CI%C an& RI%C) CI%C) CISC is an acrony "or co ple$ instruction set co puter.

The rea"on" to ha,e the lar e in"tr'ction "et are) CISC syste s are co ple$ as the architecture and the instructions are as per the technology and hence there is a reAuire ent "or and there"ore will have The any addressing odes. odi"ied

ore nu ber o" instructions

ain "unction o" any a

icroprocessor is to "etch the data and process it. The e ory i.e.# e ory is e$ternal. As e ory or "ro IK& peripherals there is a necessary

chip as such doesn:t have any provision "or process needs to access data "ro "or ore instructions.

Dra/3ac4" 3ehin& ha,in the lar e in"tr'ction "et) The large instruction set is responsible "or a very co plicated control logic that generates a host o" control signals and interrupts that are i portant "or the wor(ing o" the processor. This large instruction set creates proble s "or the co piler as it has to write code "or each individual instruction. It beco es di""icult to debug i" there is any ista(e in the code o" the co piler. The 1arge instruction set has a very co plicated decoding logic which is responsible "or a ore nu ber o" stages or "or an increased propagation delay o" the control logic. This is because an increase in the nu ber o" stages leads to proportionate increase in the nu ber o" gates.
G

Transistor has a rise ti e# a "all ti e contributing to the propagation delay o" the signal. So at every gate the signal gets delayed and this cu ulative delay in propagation adds up# to decrease the processing speed o" the data.They have a variety o" instruction "or ats li(e one byte# two byte# three byte. They have a large nu ber o" addressing odes. In general the pipelining is used to increase the speed o" e ory operations with

separate control over the bus. They are di""icult to handle i" there is a considerable di""erence between instruction lengths and e$ecution cycle o" di""erent instructions then the pipeline design will be RI%C) RISC is an acrony uch ore co plicated.

"or reduced instruction set co puter.

The a&,anta e" of in"tr'ction "et of RI%C are a" follo/") In the RISC based syste and it is there"ore ini i!es the the "reAuently used instructions are hardware reali!ed e ory access ti e and the decoding ti e. It is easy achine language progra s. ay be possible to

to write code "or "i$ed instruction set# so the co piler supports "or e""icient translation o" high level language progra s into

As the architecture supports pipeline in di""erent seg ents# it to load accu ulator and store accu ulator instructions only.

e$ecute nu ber o" instructions in a single instruction cycle. Me ory access is li ited

20

CHAPTER 3 DE%I5N A%CEPT% 3.1 Intro&'ction This chapter 'rogra used. The RISC 'rocessor Consists o" the "ollowing Co ponents: 2) .) -) C) F) D) <) =) G) 20) Cloc( 7enerator Resetter Control 1ogic 6ecoder Arith etic 1ogic %nit 'rogra Counter ainly concentrating on the design o" -.)bit RISC 'rocessor

(Individual Modules li(e# Cloc( 7enerator# Resetter# Control 1ogic 6ecoder# A1%# Counter# Instruction Register# Multiple$er# Me ory# Accu ulator and /u""er). odule# here used 4561 language and "or Si ulation Active)561 tool To design each

Instruction Register Multiple$er Me ory Accu ulator /u""er

22

(i 're 3) $loc4 Dia ram of 3263it RI%C Proce""or

2.

3.2 Cloc4 5enerator) The bloc( diagra o" Cloc( 7enerator Module is shown in 3igure. C

(i 're 1) Cloc4 5enerator Module Description: ;very processor has its own built)in cloc(# this cloc( dictates how "ast the processor can process the data (0Hs and 2Hs)# you will see processors advertised as having a speed o" say .75!# this A easure ent re"ers to the internal cloc(. are provided "or sel")ti ed processing. An operation is

ethod and syste

e$ecuted with a "unctional unit. A ti ing o" the operation e$ecution is si ulated with a trac(ing ele ent# and a trac(ing signal is output. A seAuencing signal is varied to the "unctional unit in response to the trac(ing signal. These a,or cloc(s drive large grids over the instruction "etch# integer# "loating

point# loadKstore# and bus inter"ace units# as well as the pads. They also drive local cloc(s and local conditional cloc(s. The reasons "or i ple enting this cloc(ing hierarchy are to i prove per"or ance and to save power. Multi)level bu""ering in the cloc( path allows circuit designers to re edy critical paths and race proble s by ad,usting the nu ber o" bu""ers between driving and receiving state ele ents and thus +borrow+ ti e "ro te porally ad,acent cloc( cycles.

The cloc( hierarchy saves power through cloc( driver place ent and conditional cloc(s. The local cloc( drivers can be placed near their loads# reducing the routing

2-

capacitance and per itting s aller drivers. Conditional cloc(ing reduces pea( power when e$ecution e$clusivity is e$ploited. I" a processor is advertised as having a speed o" .75! this eans that it can

process data internally . billion ti es a second (every cloc( cycle)# so i" the processor is a -.)bit processor running at .75! then it can potentially process -. bits o" data si ultaneously# . billion ti es a second. The cloc( generator is a co binational circuit that generates cloc( signals that are responsible "or the "unction o" the entire processor. The cloc( signal gets its input "ro a crystal oscillator that is connected "ro an e$ternal source. This is not shown in this odule. The connection is understood to be i plicit. The three cloc(s are generated as per the "ollowing logic. The "irst cloc( Cloc(2 synchroni!es with the e$ternal crystal oscillator. Ehile Cloc(. changes at the negative edge o" Cloc(2. So it has a period twice that o" Cloc(2 and changes "or the negative edge o" Cloc(2. The third cloc( 3etch changes at the positive edge o" Cloc(.. So it has a period twice that o" Cloc(.# or e""ectively it has a period C ti es that o" Cloc(2# and changes only "or every other negative edge o" the e$ternal crystal oscillator.This sort o" pattern is generated so that# eight distinct control signals can be generated by ta(ing di""erent co binations o" these cloc(s.

7HD. Co&e for Cloc4 5enerator) --***************************************************************** --Entity Name: ClkGen --Entity Description: The Clock Generator generates Clock Signals that are -responsible or the unction o the entire !rocessor" --****************************************************************** library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input and utput !eclarations********************* entity Cl(7en is
2C

port ( Cl(2

: in stdLlogicB Rst : in stdLlogicB Cloc(2 : out stdLlogicB Cloc(. : out stdLlogicB 3etch : out stdLlogic

)B end Cl(7enB architecture Cl(gen o" Cl(7en is --*********************Si"nal !eclarations************************* signal Cl(.#3etch2:stdLlogicB begin Cloc(2MNCl(2B Cloc(.MNCl(.B 3etchMN3etch2B --***************************************************************** --Cloc#1 is Synchroni$ed %ith Cl#1& --Cloc#2 chan"es at the 'e"ati(e )d"e o* Cloc#1& --***************************************************************** process(Cl(2#Rst) begin i" (RstNH0H)then Cl(.MNH0HB elsi" (Cl(2NH0H and Cl(2Hevent)then Cl(.MNnot Cl(.B end i"B end processB --***************************************************************** --*+etch chan"es at the ,ositi(e )d"e o* Cloc#2& --***************************************************************** process(Cl(.#Rst) begin i" (RstNH0H)then 3etch2MNH0HB elsi" (Cl(.NH2H and Cl(.Hevent)then 3etch2MNnot 3etch2B end i"B end processB end Cl(7enB

2F

3.3 Re"etter) The bloc( diagra o" Resetter Module is shown in 3igure. F

(i 're 2) Re"etter Module Description: The Resetter is a co ponent that generates the internal reset signal. In Rst ta(ing the e$ternal reset reAuest "ro the e$ternal world. The output "ro this odule supplies all the co ponents with the reset signal that initiali!es all the hardware co ponents in the syste . %nder RISC &S -.< and earlier a nu ber o" special types o" reset were available to the user. ;ach o" these reset types was triggered by holding a (ey during a reset.

Eith RISC &S D.0. and later# the only operations o" these which re ain are the 6elete# Shi"t and (eypad)9. In order to support con"igure the display which the syste ultiple displays# it is possible to i" the odule has been will start up using. This can be a proble

display con"igured is no longer present ("or e$a ple# because the session) be "orced to display nu ber 0.

re oved). I" the 0 (ey (not the (eypad)0) is held during startup# the display will ("or this

2D

7HD. Co&e for Re"etter) --******************************************************************* --Entity Name : #es --Entity Description : This Module generates the internal #eset Signal taking -the e$ternal #eset Signal --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input and utput !eclarations****************** entity Res is port ( RstReA : in ST6L1&7ICB Cl(. : in ST6L1&7ICB 3etch: in ST6L1&7ICB Rst : out ST6L1&7IC )B end ResB --******************************************************************* --The Rst Si"nal initiali$es all the hard%are Components in the system& --******************************************************************* architecture Res o" Res is begin --******************************************************************* --Resetter operates at 'e"ati(e )d"e o* Cl#2& --******************************************************************* process(Cl(.) begin i"(RstReANH0H)then RstMNH0HB else RstMNH2HB end i"B end processB end ResB

3.1 Control .o ic Deco&er)

2<

The bloc( diagra

o" Control 1ogic 6ecoder Module is shown in 3igure. D

(i 're 8) Control .o ic Deco&er Module Description: The Control 1ogic 6ecoder is the is central nervous syste ost i portant part o" the RISC processor. It

o" the entire processor as it outputs the critical control signals

that are responsible "or the "unction o" the processor. It has the three cloc( signals and the F)bit &pcode as inputs.

6epending on the &pcode generated an individual set o" control signals are generated that a(es the RISC processor wor( li(e it does. The end user speci"ies this pattern o" control signals that decides how the processor should "unction.

The control logic is nothing but a decoder that generates di""erent co binations based on di""erent inputs given. The bit)pattern o" the control signals is speci"ied in the "ollowing page.

('nctionalit+

2=

C1&C@ CJC1; Address Setup 2 Instruction 3etch Instruction 1oad Idle Address Setup . &perand 3etch )) Add# 3add# 3 ul Sub# 3sub# 3div A>6 8&R 16A 8>&R ?%M' S@I' All &thers A1% ))) Add# 3add# 3 ul Sub# 3sub# 3div &R 8&R 8>&R 16A A>6 ?%M' S@I' STA All &thers

Rd 0 2 2 2 0 2 2 2 2 2 2 0 0 0 2 2 2 2 2 2 2 0 0 0 0

1dir 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Inc'c 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0

1d'c 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0 0

1dAcc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 0 0 0 0

E r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0

Ta3le 1) ('nctionalit+ of C.D

7HD. Co&e for Control .o ic Deco&er) --******************************************************************* --Entity Name : Control-%ogic --Entity Description : Control %ogic is the Central Ner&ous System o the entire -!rocessor" 't produces si$ control signals that are -responsible or the (unction o the !rocessor" --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB entity ControlL1ogic is

2G

--******************************************************************* --Input and utput !eclarations :- It has three Cloc# Si"nals and 5 -it pCode as -Inputs& .dIr/.d,c/.d0cc/Inc,c/Rd/1r as ut,uts --******************************************************************* port ( Cl(2 : in stdLlogicB Cl(. : in stdLlogicB 3etch : in stdLlogicB Rst : in stdLlogicB &pCode : in stdLlogicLvector(C downto 0)B 1dIr : out stdLlogicB Inc'c : out stdLlogicB 1d'c : out stdLlogicB 1dAcc : out stdLlogicB Rd : out stdLlogicB Er : out stdLlogic )B end ControlL1ogicB architecture ControlL1ogic o" ControlL1ogic is --*********************Si"nal !eclaration************************ signal Con :stdLlogicLvector (. downto 0)B begin ConMN(Cl(2OCl(.O3etch)B process(con#rst#opcode) --*********************Constant !eclarations************************ constant A66R;SSLS;T%'2 : stdLlogicLvector(. downto 0):N+022+B constant I>STR%CTI&>L3;TC5 : stdLlogicLvector(. downto 0):N+222+B constant I>STR%CTI&>L1&A6 : stdLlogicLvector(. downto 0):N+002+B constant I61; : stdLlogicLvector(. downto 0):N+202+B constant A66R;SSLS;T%'. : stdLlogicLvector(. downto 0):N+020+B constant &';RA>6L3;TC5 : stdLlogicLvector(. downto 0):N+220+B constant A1% : stdLlogicLvector(. downto 0):N+000+B constant ST&R;LR;S%1T : stdLlogicLvector(. downto 0):N+200+B --******************************************************************* --!ependin" on the pCode "enerated an indi(idual set o* --Control Si"nals are "enerated --******************************************************************* constant A66 constant S%/ constant I>R : stdLlogicLvector(C downto 0):N+00000+B : stdLlogicLvector(C downto 0):N+00002+B : stdLlogicLvector(C downto 0):N+00020+B

.0

constant 6CR constant A>6L&' constant &RL&' constant 8&RL&' constant CMA constant 1S5I3T constant RS5I3T constant 16A constant STA constant ?%M' constant S@I' constant 5A1T constant 8>&RL&' constant 3A66 constant 3S%/ constant 3M%1 constant 36I4 begin

: stdLlogicLvector(C downto 0):N+00022+B : stdLlogicLvector(C downto 0):N+00200+B : stdLlogicLvector(C downto 0):N+00202+B : stdLlogicLvector(C downto 0):N+00220+B : stdLlogicLvector(C downto 0):N+00222+B : stdLlogicLvector(C downto 0):N+02000+B : stdLlogicLvector(C downto 0):N+02002+B : stdLlogicLvector(C downto 0):N+02020+B : stdLlogicLvector(C downto 0):N+02022+B : stdLlogicLvector(C downto 0):N+02200+B : stdLlogicLvector(C downto 0):N+02202+B : stdLlogicLvector(C downto 0):N+02220+B : stdLlogicLvector(C downto 0):N+02222+B : stdLlogicLvector(C downto 0):N+20000+B : stdLlogicLvector(C downto 0):N+20002+B : stdLlogicLvector(C downto 0):N+20020+B : stdLlogicLvector(C downto 0):N+20022+B

i"(RstNH0H)then 1dIr MNH0HB 1dAcc MNH0HB Rd MNH0HB 1d'c MNH0HB Inc'c MNH0HB Er MNH0HB else case Con is --******************************************************************* -- Initiali$in" all the Control Si"nals to $ero --******************************************************************* when A66R;SSLS;T%'2 NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB --******************************************************************* --2y ma#in" Rd as 313 Instruction can -e +etched *rom the 4emory --******************************************************************* when I>STR%CTI&>L3;TC5 NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB

.2

--****************************************************************** -2y ma#in" Rd and .dIr as 313 !ata is .oaded into the Instruction Re"ister* --******************************************************************* when I>STR%CTI&>L1&A6 NP 1dIr MNH2HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB

--******************************************************************* --*'o peration is ,er*ormed and allo%s the processor to Connect --******************************************************************* when I61; NP 1dIr MNH2HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB --******************************************************************* --*2y ma#in" Inc,c as 313 the ,ointer points to the next 4emory .ocation * --******************************************************************* when A66R;SSLS;T%'. NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH2HB Rd MNH0HB Er MNH0HB --******************************************************************* --* ,)R0'! +)TC5:--* ne o* the perand is stored in the 0ccumulator and Result o* an * --* peration is also stored in 0ccumulator& --******************************************************************* when &';RA>6L3;TC5 NP CAS; &'C&6; IS when A66 NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB

when 3A66

NP

..

Inc'c MNH0HB Rd MNH2HB Er MNH0HB when 3S%/ NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB

when 3M%1

NP

when 36I4 NP

when S%/ NP

when A>6L&' NP

when &RL&' NP

when 8&RL&' NP

.-

1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB when 8>&RL&' NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB when 16A NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB

--******************************************************************* --*2y ma#in" .d,c as 313 the ,ro"ram Counter is .oaded %ith the (alue on Ir ut* --******************************************************************* when ?%M' NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH2HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB

--******************************************************************* --*2y ma#in" Inc,c as 313 the next Instruction is s#ipped * --******************************************************************* when S@I' NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH2HB Rd MNH0HB Er MNH0HB when &T5;RS NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB end caseB

.C

--******************************************************************* --* --***0rithmetic .o"ic 6nit***---******************************************************************* when A1% NP CAS; &'C&6; IS when A66 NP 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB

when 3A66

NP

when 3S%/

NP

when 3M%1

NP

when 36I4 NP

when S%/ NP

when A>6L&' NP

.F

1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB when &RL&' NP 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB

when 8&RL&' NP

when 8>&RL&' NP 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB when 16A NP 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH2HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH2HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB

when ?%M' NP

--******************************************************************* --Instructions li#e S7I,/50.T/I'R/!CR/C40/.S5I+T/RS5I+T directly %or# on --0ccumulator and Result is stored in 0ccumulator only& --******************************************************************* when S@I' NP 1dIr MNH0HB

.D

1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH2HB Rd MNH0HB Er MNH0HB when 5A1T NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB

when I>R NP

when 6CR NP

when CMA NP

when 1S5I3T NP

when RS5I3T NP

.<

when &T5;RS NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB end caseB --******************************************************************* --* --***ST R)8R)S6.TS***---******************************************************************* when ST&R;LR;S%1T NP case &pCode IS when ?%M' NP 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH2HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB 1dIr MNH0HB 1dAcc MNH0HB 1d'c MNH0HB Inc'c MNH2HB Rd MNH0HB Er MNH0HB --******************************************************************* -2y ma#in" the Result is stored in 4emory location speci*ied -y perand 0ddress --******************************************************************* when STA NP 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH2HB when others NP 1dIr MNH0HB 1dAcc MNH2HB 1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB when S@I' NP

end caseB when others NP 1dIr MNH0HB 1dAcc MNH0HB

.=

1d'c MNH0HB Inc'c MNH0HB Rd MNH0HB Er MNH0HB end caseB end i"B end processB end ControlL1ogicB

3.2 Arithmetic .o ic Unit) The bloc( diagra o" Arith etic 1ogic %nit Module is shown in 3igure. <

(i 're 9) Arithmetic .o ic Unit Module Description:

.G

The A1% is an internal part o" the processor which is used "or all and logical operations# the basic operations o" an A1% include adding and algorith s "or per"or ing these

athe atical ultiplying

binary values as well as per"or ing logical operations such as A>6# &R and 8&R. The athe atical and logical operations are hard coded (stored per anently) within the A1%.

The Arith etic logic unit per"or s all the operations speci"ied in the speci"ications o" the processor. It per"or s around .0 instructions. The logic "or all the instructions is entioned in this odule.

The various circuits used to e$ecute data)processing instructions are usually co bined in a single circuit called an arith etic logic unit or A1%. A1% is the part o" a co puter processor (C'%) that carries out arith etic and logic operations on the operands in co puter instruction words. A1% per"or s operations such as addition# subtraction and ultiplication o"

integers and bitwise A>6# &R# >&T# 8&R and other /oolean operations. The C'%Hs instruction decode logic deter ine which particular operation the A1% should per"or # the source o" the operands and the destination o" the result. In so e processors# the A1% is divided into two units# an arith etic unit (A%) and a logic unit (1%). Co puter arith etic is co only per"or ed on two very di""erent types o" the negative

nu bers integer and "loating point. Co puter progra s calculate both positive and negative nu bers. So a representation that distinguishes the positive "ro co ple ent binary nu bers. In arith etic unit# -.)bit A1% (addition and subtraction) design will be constructed based on 4561. The 4561 hardware description language is used to provide a gate level odel and si ulation o" each design. A nu ber o" di""ering con"igurations o" binary adders e$ist "or inclusion into A1% design. is reAuired. ;very co puter today uses twos)co ple ent binary representation "or

-0

&ne o" the

ost popular

ethods to reduce delay is to use a carry loo()ahead echanis # the propagation delay is reduced to

echanis . /y using carry loo()ahead

"our)gate level irrespective o" the nu ber o" bits in the adder. The "loating point instructions in the processor are written in this odule as

"unctions. They don:t involve the cloc( or the reset signal. They are ,ust co binational circuits that are i ple ented by internal registers# counters and other s all co binational circuits. The arith etic logic unit consists o" a te porary register that is used "or operations between the Accu ulator and the data on the data bus. This register is later assigned to the Accu ulator.

The A1% as in this

odule can be progra

ed to wor( in any "ashion desired.

Any application or control desired can be obtained by writing a "unction o" the application and running it in the A1% the Control 1ogic 6ecoder. The 3'% is also an internal part o" odern processors# the 3'% is designed to handle odule with the appropriate control signals "ro

any "loating point calculations and li(e the A1% it has its algorith s hard coded (stored per anently) inside the unit. Eith the Intel "a ily o" processors up until the =0C=D68 the "loating point unit was an e$ternal unit (co subseAuent processors such as the 'entiu only called a ath coprocessor)# have the 3'% built in. Intel you would

3or e$a ple i" you had the (now old) =0-=DS8 processor "ro &pcode developed "or each instruction is tabulated in Table ..C.2. Ta3le 2) Corre"pon&in Opco&e for each In"tr'ction
6eci al ;Auivalent 0 2 . &pcode 00000 00002 00020 00022 Instruction A66 S%/ I>R 6CR

be able to purchase the =0-=< coprocessor which was in "act the "loating point unit. The

-2

C F D < = G 20 22 2. 22C 2F 2D 2< 2= 2G

00200 00202 00220 00222 02000 02002 02020 02022 02200 02202 02220 02222 20000 20002 20020 20022

A>6 &R 8&R CMA 1S5I3T RS5I3T 16A STA ?%M' S@I' 5A1T 8>&R 3A66 3S%/ 3M%1 36I4

7HD. Co&e for A.U) --******************************************************************* --Entity Name : )lu *)rithmetic %ogic +nit, --Entity Description : This Module per orms ollo-ing .perations" --)rithmetic : )DD/S+0/'N#/DC#" --%ogical : )ND/.#/1.#/%S2'(T/#S2'(T/CM)" --Control : 3+M!/S4'!/2)%T" --Data Trans er : %D)/ST)" --(loating !oint : )DD/S+0/M+%/D'5" --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB use I;;;.stdLlogicLunsigned.allB --****************** Input9 utput !eclarations ************************ entity Alu is port ( 6ata : in stdLlogicLvector(-2 downto 0)B Acc&ut : in stdLlogicLvector(-2 downto 0)B &pCode : in stdLlogicLvector(C downto 0)B Cl( : in stdLlogicB Rst : in stdLlogicB

-.

Aluout : out stdLlogicLvector(-2 6&E>T& 0) )B end AluB architecture Alu o" Alu is --******************************************************************* --This +unction per*orms +loatin" ,oint 0ddition& --******************************************************************* 3unction "loatLadd(Accout#6ata:in stdLlogicLvector(-2 downto 0)) return stdLlogicLvector is --******************************************************************* --This +unction to con(ert :--it -inary to inte"er& --******************************************************************* 3unction toLinteger($:in stdLlogicLvector(D downto 0)) return integer is --******************(aria-le !eclararions****************************** variable su :integer:N0B variable Te p :StdLlogicLvector(D downto 0)B begin te p:N$B --*********;eneratin" loop to con(ert :--it 2inary to inte"er********** $$$: "or i in 0 to D loop i" (te p(i)NH2H)then su :Nsu Q.99iB else Su :NSu B end i"B end loopB return su B end "unctionB --*********************<aria-le !eclarations*************************** variable MaIn : stdLlogicLvector(.. downto 0)B )) Internal Register variable MbIn : stdLlogicLvector(.. downto 0)B )) Internal Register variable ;a#;b : stdLlogicLvector(< downto 0)B )) Two ;$ponents including Sign variable IR : stdLlogicLvector(.. downto 0)B )) Resultant Mantissa variable I; : stdLlogicLvector(D downto 0)B )) Resultant ;$ponent variable >s : integerB )) >u ber &" Shi"ts

--

variable Ma#Mb : stdLlogicLvector(.. downto 0)B )) Mangitude &" Two antissas variable ;S : stdLlogicB )) Sign &" Resulant ;$ponent variable a#b : stdLlogicB )) Sign &" Two e$ponents variable s2#s. : stdLlogicB )) Sign &" Two antissas variable Sign : stdLlogicB )) Sign &" Resultant Mantissa variable E#R : stdLlogicLvector(2 downto 0)B variable 8 : stdLlogicLvector(-2 downto 0)B )) 3inal Result begin MaIn:NAcc&ut(.. downto 0)B MbIn:N6ata(.. downto 0)B ;a :NAcc&ut(-0 downto .-)B ;b :N6ata(-0 downto .-)B a :NAcc&ut(-0)B b :N6ata(-0)B R :N(aOb)B --******************************************************************* --*)=uali$ation o* )xponents includes t%o steps& --*1&Su-traction o* )xponents& --*2&0li"nement o* 4antissas& --******************************************************************* scase R is when +00+ NP Mb:NMbInB Ma:NMaInB i"((;a(D downto 0))M(;b(D downto 0))) then >S:NtoLinteger(;b(D downto 0));a(D downto 0))B "or $ in 2 to >s loop Ma :N (H0H O Ma(.. downto 2))B

end loopB I;:N;b(D downto 0)B ;s:N;b(<)B elsi"((;b(D downto 0))M(;a(D downto 0))) then >S:NtoLinteger(;a(D downto 0));b(D downto 0))B "or $ in 2 to >s loop Mb:N(H0H O Mb(.. downto 2))B end loopB I;:N;a(D downto 0)B ;s:N;a(<)B else >S:N>sB Ma:NMaB

-C

Mb:NMbB I;:NI;B ;S:N;a(<)B end i"B when +02+ NP Mb:NMbInB Ma:NMaInB >S:NtoLinteger(;a(D downto 0)Q;b(D downto 0))B "or $ in 2 to >s loop Mb:N(H0H O Mb(.. downto 2))B end loopB I;:N;a(D downto 0)B ;S:N;a(<)B Mb:NMbInB Ma:NMaInB >S:NtoLinteger(;b(D downto 0)Q;a(D downto 0))B "or $ in 2 to >s loop Ma:N(H0H O Ma(.. downto 2))B end loopB I;:N;b(D downto 0)B ;S:N;b(<)B when +22+ NP Mb:NMbInB Ma:NMaInB i"((;a(D downto 0))M(;b(D downto 0))) then >S:NtoLinteger(;b(D downto 0));a(D downto 0))B "or $ in 2 to >s loop Mb:N(H0H O Mb(.. downto 2))B end loopB I;:N;a(D downto 0)B ;S:N;a(<)B elsi"((;b(D downto 0))M(;a(D downto 0))) then >S:NtoLinteger(;a(D downto 0));b(D downto 0))B "or $ in 2 to >s loop Ma:N(H0H O Ma(.. downto 2))B end loopB I;:N;b(D downto 0)B ;S:N;b(<)B else >S:N>sB Ma:NMaB Mb:NMbB I;:NI;B ;S:N;a(<)B end i"B when others NP >ullB

when +20+ NP

-F

end caseB --******************0ddition o* 4antissas****************************** IR:NMaQMbB --***********.o"ic *or the Si"n o* the 4antissa*************************** s2:NAcc&ut(-2)B s.:N6ata(-2)B E :N(s2Os.)B case E is when +00+ NP sign:NH0HB when +22+ NP sign:NH2HB when +02+ NP i"(;aP;b) then sign:NH0HB elsi"(;aM;b) then sign:NH2HB elsi"(;aN;b) then i"(MaPMb) then sign:NH0HB elsi"(MaMMb) then sign:NH2HB elsi"(MaNMb) then sign:NH0HB else sign:NsignB end i"B else sign:NsignB end i"B when +20+ NP i"(;aP;b) then sign:NH2HB elsi"(;aM;b) then sign:NH0HB elsi"(;aN;b) then i"(MaPMb) then sign:NH2HB elsi"(MaMMb) then sign:NH0HB elsi"(MaNMb) then sign:NH0HB else sign:NsignB end i"B else sign:NsignB end i"B when others NP nullB

-D

end caseB --***********+inal Result 0*ter 0ddition******************************* 8:N(sign O ;S O I; O IR(.. downto 0))B return 8B end "unctionB --******************************************************************* This +unction per*orms +loatin" ,oint Su-traction& --******************************************************************* 3unction "loatLsub(Accout#6ata:in stdLlogicLvector(-2 downto 0)) return stdLlogicLvector is --************+unction to con(ert :--it -inary to inte"er************** 3unction toLinteger($:in stdLlogicLvector(D downto 0)) return integer is --*********************<aria-le !eclarations*************************** variable su : integer:N0B variable Te p : StdLlogicLvector(D downto 0)B begin te p:N$B $$$: "or i in 0 to D loop i" (te p(i)NH2H)then su :Nsu Q.99iB else Su :NSu B end i"B end loopB return su B end "unctionB --*********************(aria-le !eclarations*************************** variable MaIn#MbIn: stdLlogicLvector(.. downto 0)B )) Internal Register variable ;a#;b : stdLlogicLvector(< downto 0)B )) Two e$ponents Including Sign variable IR : stdLlogicLvector(.. downto 0)B )) Resultant Mantissa variable I; : stdLlogicLvector(D downto 0)B )) Resultant ;$ponent variable >s : integerB )) >u ber &" Shi"ts variable Ma#Mb : stdLlogicLvector(.. downto 0)B )) Mangitude &" Two Mantissas variable ;S : stdLlogicB )) Sign &" Resulant ;$ponent variable a#b : stdLlogicB )) Sign &" Two ;$ponents variable s2#s. : stdLlogicB )) Sign &" Two Mantissas variable sign : stdLlogicB )) Sign &" Resultant Mantissa

-<

variable E#R variable 8 begin

: stdLlogicLvector(2 downto 0)B : stdLlogicLvector(-2 downto 0)B )) 3inal Result

MaIn:NAccout(.. downto 0)B MbIn:N6ata(.. downto 0)B ;a :NAccout(-0 downto .-)B ;b :N6ata(-0 downto .-)B a :NAccout(-0)B b :N6ata(-0)B R :N(aOb)B --******************************************************************* --*)=uali$ation o* )xponents includes t%o steps& --*1&Su-traction o* )xponents& --*2&0li"nement o* 4antissas& --******************************************************************* case R is when +00+ NP Mb:NMbInB Ma:NMaInB i"((;a(D downto 0))M(;b(D downto 0))) then >S:NtoLinteger(;b(D downto 0));a(D downto 0))B "or $ in 2 to >s loop Ma:N(H0H O Ma(.. downto 2))B end loopB I;:N;b(D downto 0)B ;S:N;b(<)B elsi"((;b(D downto 0))M(;a(D downto 0))) then >S:NtoLinteger(;a(D downto 0));b(D downto 0))B "or $ in 2 to >s loop Mb:N(H0H O Mb(.. downto 2))B end loopB I;:N;a(D downto 0)B ;S:N;a(<)B else >S:N>sB Ma:NMaB Mb:NMbB I;:NI;B ;S:N;a(<)B end i"B

-=

when +02+ NP

Mb:NMbInB Ma:NMaInB >S:NtoLinteger(;a(D downto 0)Q;b(D downto 0))B "or $ in 2 to >s loop Mb:N(H0H O Mb(..

downto 2))B end loopB I;:N;a(D downto 0)B ;S:N;a(<)B when +20+ NP Mb:NMbInB Ma:NMaInB >S:NtoLinteger(;b(D downto 0)Q;a(D downto 0))B "or $ in 2 to >s loop Ma:N(H0H O Ma(.. downto 2))B end loopB I;:N;b(D downto 0)B ;S:N;b(<)B when +22+ NP Mb:NMbInB Ma:NMaInB i"((;a(D downto 0))M(;b(D downto 0))) then >S:NtoLinteger(;b(D downto 0));a(D downto 0))B "or $ in 2 to >s loop Mb:N(H0H O Mb(.. downto 2))B end loopB I;:N;a(D downto 0)B ;S:N;a(<)B elsi"((;b(D downto 0))M(;a(D downto 0))) then >S:NtoLinteger(;a(D downto 0));b(D downto 0))B "or $ in 2 to >s loop Ma:N(H0H O Ma(.. downto 2))B end loopB I;:N;b(D downto 0)B ;S:N;b(<)B else >S:N>sB Ma:NMaB Mb:NMbB I;:NI;B ;S:N;a(<)B end i"B

-G

when others NP nullB end caseB --******************Su-traction o* 4antissas*************************** IR:NMa)MbB --***********lo"ic *or the si"n o* the mantissa************************ s2:NAccout(-2)B s.:N6ata(-2)B E:N(s2Os.)B case E is when +00+NP sign:NH0HB when +22+NP sign:NH2HB when +02+NP i"(;aP;b)then sign:NH0HB elsi"(;aM;b) then sign:NH2HB elsi"(;aN;b) then i"(MaPMb) then sign:NH0HB elsi"(MaMMb) then sign:NH2HB elsi" (MaNMb) then sign:NH0HB else sign:NsignB end i"B else sign:NsignB end i"B when +20+NP i" (;aP;b)then sign:NH2HB elsi" (;aM;b) then sign:NH0HB elsi" (;aN;b) then i"(MaPMb) then sign:NH2HB elsi"(MaMMb) then sign:NH0HB elsi" (MaNMb) then sign:NH0HB else sign:NsignB end i"B else

C0

sign:NsignB end i"B when othersNP nullB end caseB ))999999999993inal Result A"ter Subtraction9999999999999999999999999999 8:N(sign O ;S O I; O IR(.. downto 0))B return 8B end "unctionB --******************************************************************* -This +unction per*orms +loatin" ,oint !i(ision& --******************************************************************* 3unction "loatLdiv(Accout#6ata:stdLlogicLvector(-2 downto 0)) return stdLlogicLvector is --*********************<aria-le !eclarations*************************** variable 2# . :stdLlogicLvector(.. downto 0)B )) Magnitude Two Mantissas variable e2#e. :stdLlogicLvector(< downto 0)B )) Two ;$ponents Including Sign variable s2#S. :stdLlogicB )) Sign &" Two Mantissas variable S :stdLlogicB )) Sign &" Resultant Mantissa variable a#b :stdLlogicB )) Sign &" Two ;$ponents variable ;a#;b :stdLlogicLvector(D downto 0)B )) Magnitude &" Two ;$ponents variable c :stdLlogicB )) Sign &" Resultant ;$ponent variable e :stdLlogicLvector(D downto 0)B )) Resultant ;$ponent variable te p2 :stdLlogicLvector(.. downto 0)B )) Te porary Register variable te p :stdLlogicLvector(CF downto 0)B )) Te porary Register variable S :stdLlogicLvector(.. downto 0)B )) Suotient variable Re i :stdLlogicLvector(.. downto 0)B )) Re ainder variable r2#r. :stdLlogicLvector(.. downto 0)B variable E#R :stdLlogicLvector(2 downto 0)B variable 8 :stdLlogicLvector(-2 downto 0)B )) 3inal Result variable i :integerB begin 2:NAccout(.. downto 0)B .:N6ata(.. downto 0)B e2:NAccout(-0 downto .-)B e.:N6ata(-0 downto .-)B --************lo"ic *or the si"n o* mantissa************************** s2:NAccout(-2)B s.:N6ata(-2)B E:N(s2Os.)B case E is when +00+NP s:NH0HB

C2

when +22+NP s:NH0HB when othersNP s:NH2HB end caseB --******************************************************************* --*+loatin" ,oint !i(ision includes +i(e steps& --*1&Chec# *or >eros& --*2&)(aluate the si"n& --*3&0li"n the !i(idend& --*4&Su-traction o* )xponents& --*5&!i(ide the 4antissas& --*************************1&Chec#in" *or >eros******************** i"(( 2N+00000000000000000000000+) and ( .N+00000000000000000000000+)) then report +>on Arith etic >u bers:'lease 4eri"y Inputs+B elsi"( .N+00000000000000000000000+) then report +>on Arith etic >u bers:'lease 4eri"y Inputs+B else 2:N 2B .:N .B end i"B --***************************************************************** --*!i(idend 0li"nment :--*I* !i(idend is "reater than or e=ual to the !i(isor/then --*the !i(idend *raction is Shi*ted to the Ri"ht and --*its )xponent is incremented -y 313 --***************************************************************** r2:N 2B r.:N .B i" ( 2P .) then r2:Nr2(.. downto 2)OH0HB ;a:N;aQ2B Te p:N(r2 O +00000000000000000000000+)B Te p2:NTe p(CF downto .-)B --******************************************************************* --;eneratin" the loop:--1&I* !i(idend is smaller than the !i(isor then le*t shi*t until -- it -ecomes "reater or e=ual /#eep those many $eros in ?uotient& --2& nce !i(idend -ecame "reter then su-tract !i(isor *rom the -- !i(idend and #eep 313 in ?uotient& --3&Continue the procedure until num-er o* -its in ?uotient -ecome -- 23/-ecause the Remainder ne(er -ecomes >ero& --******************************************************************* "or i in .. downto 0 loop i"(Te p2Pr.) then

C.

Re i:NTe p2)r.B Re i:N(Re i(.2 downto 0) O H0H)B Re i(0):NTe p(i)B S(i):NH2HB elsi"(Te p2Mr.) then Re i:NTe p2)+00000000000000000000000+B Re i:NRe i(.2 downto 0)OH0HB Re i(0):NTe p(i)B S(i):NH0HB else Te p2:NRe iB end i"B end loopB elsi"( 2Nr.) then ))999Since /oth 6ividend and 6ivisor are ;Aual Suotient is S:N+00000000000000000000002+B elsi"( 2M .)then --******************************************************************* --;eneratin" the loop:--1&I* !i(idend is smaller than the !i(isor then le*t shi*t until -- it -ecomes "reater or e=ual /#eep those many $eros in ?uotient& --2& nce !i(idend -ecame "reter then su-tract !i(isor *rom the -- !i(idend and #eep 313 in ?uotient& --3& Continue the procedure until num-er o* -its in ?uotient -ecome -- 23/-ecause the Remainder ne(er -ecomes >ero& --******************************************************************* Te p:N(r2 O +00000000000000000000000+)B Te p2:NTe p(CF downto .-)B "or i in .. downto 0 loop i"(Te p2PNr.) then Re i:NTe p2)r.B Re i:N(re i(.2 downto 0) O H0H )B Re i(0):NTe p(i)B S(i):NH2HB elsi"(Te p2Mr.) then Re i:NTe p2)+00000000000000000000000+B Re i:N(re i(.2 downto 0) O H0H)B Re i(0):NTe p(i)B S(i):NH0HB end i"B Te p2:NRe iB ade H2H99

C-

end loopB end i"B --**************.o"ic *or the Si"n o* )xponent**************** ;a:Ne2(D downto 0)B ;b:Ne.(D downto 0)B a :Ne2(<)B b :Ne.(<)B R :N(aOb)B case R is when +00+ NP i"(;aP;b) then c:NH0HB e:N;a);bB elsi"(;aM;b) then c:NH0HB e:N;b);aB else c:NH0HB e:N+0000000+B end i"B when +22+ NP i"(;aP;b) then c:NH2HB e:N;a);bB elsi"(;aM;b) then c:NH0HB e:N;b);aB else c:NH0HB e:N+0000000+B end i"B when +02+NP i"(;aP;b) then c:NH0HB e:N;aQ;bB elsi"(;aM;b) then c:NH0HB e:N;bQ;aB else c:NH0HB e:N+0000000+B end i"B when +20+NP i"(;aP;b) then c:NH2HB e:N;aQ;bB elsi"(;aM;b) then

CC

c:NH2HB e:N;bQ;aB else c:NH0HB e:N+0000000+B end i"B when othersNP nullB end caseB --***********+inal Result 0*ter !i(ision*************************** 8:N(S O C O e(D downto 0) OS(.. downto 0))B return 8B end "unctionB --***************************************************************** This +unction per*orms +loatin" ,oint 4ultiplication --***************************************************************** 3unction "loatL ul(Accout#6ata:in stdLlogicLvector(-2 downto 0)) return stdLlogicLvector is --*********************(aria-le !eclarations*********************** variable e2#e. : stdLlogicLvector(< downto 0)B )) Two ;$ponents Icluding Sign variable 2# . : stdLlogicLvector(20 downto 0)B )) Magnitude & Two Mantissas variable s : stdLlogicB )) Sign &" Resultant Mantissa variable a#b : stdLlogicB )) Sign Two ;$ponents variable s2#s. : stdLlogicB )) sign Two Mantissas variable ;a#;b : stdLlogicLvector(D downto 0)B )) Magnitude &" Two ;$ponents variable c : stdLlogicB )) Sign &" Resultant ;$ponent variable e : stdLlogicLvector(D downto 0)B )) Resultant e$ponent variable : stdLlogicLvector(.2 downto 0)B )) Resultant Mantissa variable carry : stdLlogicB )) Carry variable E#R : stdLlogicLvector(2 downto 0)B variable $ : stdLlogicLvector(-2 downto 0)B )) 3inal Result begin Carry:NH0HB e2 :NAccout(-0 downto .-)B e. :N6ata(-0 downto .-)B 2 :NAccout(20 downto 0)B . :N6ata(20 downto 0)B --***************************************************************** --+loatin" ,oint 4ultiplication includes T%o steps --1&0ddtion o* )xponents

CF

--2&4ultiplication o* 4antissas --***************************************************************** s2:NAccout(-2)B s.:N6ata(-2)B R :N(s2Os.)B --************lo"ic *or the si"n o* the 4antissa******************* case R is when +00+ NP s:NH0HB when +22+ NP s:NH0HB when othersNP s:NH2HB end caseB --************lo"ic *or the si"n o* the exponent******************* ;a:Ne2(D downto 0)B ;b:Ne.(D downto 0)B a :NAccout(-0)B b :N6ata(-0)B E :N(aOb)B case E is when +00+ NP when +22+ NP when +02+ NP i"(;aP;b) then c:NH0HB e:N;a);bB elsi"(;aM;b) then c:NH2HB e:N;b);aB else c:NH0HB e:N+0000000+B end i"B when +20+ NP i"(;aP;b) then c:NH2HB e:N;a);bB elsi"(;aM;b) then c:NH0HB e:N;b);aB else c:NH0HB e:N+0000000+B c:NH0HB e:N;aQ;bB c:NH2HB e:N;aQ;bB

CD

end i"B when others NP nullB end caseB --*************lo"ic *or multiplication********************************** :N 29 .B --***********+inal Result 0*ter 4ultiplication***************************** $:N(s O c O e(D downto 0) OCarry O return $B end "unctionB begin process(Cl(#Rst) begin i" (RstNH0H) then Alu&utMN+00000000000000000000000000000000+B --*******0.6 is .oaded at the 'e"ati(e )d"e o* Cl#*************** elsi"(Cl(Hevent and Cl(NH0H)then --*************0.6 per*orms around 2@ instructions*************** case &pCode is Ehen +00000+ NP Alu&ut MN Acc&utQ6ataB Ehen +00002+ NP Alu&ut MN Acc&ut)6ataB Ehen +00020+ NP Alu&ut MN Acc&utQ+00000000000000000000000000000002+B Ehen +00022+ NP Alu&ut MN Acc&ut)+00000000000000000000000000000002+B Ehen +00200+ NP Alu&ut MN Acc&ut and 6ataB Ehen +00202+ NP Alu&ut MN Acc&ut or 6ataB Ehen +00220+ NP Alu&ut MN Acc&ut $or 6ataB Ehen +00222+ NP Alu&ut MN not Acc&utB Ehen +02000+ NP Alu&ut MN (Acc&ut(-0 downto 0)OH0H)B Ehen +02002+ NP Alu&ut MN (H0HOAcc&ut(-2 downto 2))B Ehen +02020+ NP Alu&ut MN 6ataB Ehen +02022+ NP Alu&ut MN Acc&utB Ehen +02200+ NP Alu&ut MN Acc&utB when +02202+ NP Alu&ut MN Acc&utB Ehen +02220+ NP Alu&ut MN Acc&utB Ehen +02222+ NP Alu&ut MN Acc&ut $nor 6ataB --************************************************************ --The +loatin" ,oint Instructions in the processor are %ritten as +unctions --************************************************************ when +20000+ NP Alu&ut MN 3loatLAdd(Acc&ut#6ata)B Ehen +20002+ NP Alu&ut MN 3loatLsub(Acc&ut#6ata)B when +20020+ NP Alu&ut MN 3loatL ul(Acc&ut#6ata)B Ehen +20022+ NP Alu&ut MN "loatLdiv(Acc&ut#6ata)B (.2 downto 0))B

C<

when others

nullB end caseB end i"B end processB end AluB

NP

3.8 Pro ram Co'nter) The bloc( diagra o" 'rogra Counter Module is shown in 3igure.=.

(i 're :) Pro ram Co'nter Module Description: The progra counter is one o" the essential parts o" the RISC processor. It (eeps

on incre enting the address o" the ne$t address location. It is nothing but a si ple counter that (eeps on incre enting when the control signal I>C'C appears at the input. Ehen the 16'C signal is given# the progra counter is loaded with the value or IR&%T. This ta(es place at the negative edge o" the 3etch signal.

C=

The 'rogra

Controller was originally developed as a seAuential control device ainly bit type data ade o"

to replace electro) echanical replays. 'Cs are reAuired to use a

structure# in general Microprocessors are used to handle byte or word type data. The 'C reads# interprets and e$ecutes 'C instruction by "ir ware subroutines that are the instructions o" the general icroprocessors.

The RISC architecture is a dra atic "ro analysis o" progra

the historical trend in C'%

architecture. The RISC syste s have a li ited and si ple instruction set through e$ecution characteristics# and e phasi!e on opti i!ing the instruction e$ecution pipeline "or i prove ent o" the per"or ance. The 'C:s "unction is to put the ne$t instruction:s address on the e$ternal e ory device address port. The 'C also contains the "or incre enting the address. 7HD. Co&e for PC) --******************************************************************* --Entity Name : !c *!rogram Counter, --Entity Description : !rogram Counter keeps on incrementing the address -register contents a ter etching the 'nstruction rom memory" --******************************************************************** library I;;;B use I;;;.stdLlogicL22DC.allB use I;;;.stdLlogicLunsigned.allB --***************Input and utput !eclarations*************************** entity 'c is port( Irout: in stdLlogicLvector(.D downto 0)B Rst : in stdLlogicB Inc'c: in stdLlogicB 1d'c : in stdLlogicB 'cout: out stdLlogicLvector (.D downto 0) )B end 'cB echanis reAuired to per"or the ,u p instruction (one o" the instructions which are not e$ecuted by the A1%) and

CG

architecture 'c o" 'c is begin process(Rst#Inc'c) --*********************(aria-le !eclarations**************************** variable 'out:stdLlogicL4ector(.D downto 0)B begin i"(RstNH0H)then 'out:N+000000000000000000000000000+B 'coutMN'outB --******************************************************************* --,ro"ram Counter increments at the ,ositi(e )d"e o* Inc,c --******************************************************************* elsi" (Inc'cHevent and Inc'cNH2H)then i" (1d'cNH2H)then 'out:NIroutB 'coutMN'outB else 'out:N'outQ+000000000000000000000000002+B 'coutMN'outB end i"B end i"B end processB end 'cB

3.9 In"tr'ction Re i"ter) The bloc( diagra o" Instruction Register Module is shown in 3igure.G

F0

(i 're ;) In"tr'ction Re i"ter

Module Description: The instruction register is a -.)bit register that is used to store the instruction address a"ter it is "etched "ro the the e ory. This is used to go to the address location in e ory that contains the &pcode and the operand. This synchroni!es with the

cloc( 2 and InRst. 3or the positive edge o" the Cloc( 2 when 16IR is one# the instruction is loaded into the instruction register. IR Consists o" two registers * one "or storing the op)code and the second "or storing the operand. The RiSC)2D is an =)register# 2D)bit co puter. All addresses are short word)addresses (i.e. address 0 corresponds to the "irst two bytes o" address 2 corresponds to the second two bytes o" ain e ory# etc.). ain e ory#

1i(e the MI'S instruction)set architecture# by hardware convention# register 0 will always contain the value 0. The achine en"orces this: reads to register 0 always return 0# irrespective o" what has been written there. The RISC)2D is very si ple# but it is general enough to solve co ple$ proble s.

7HD. Co&e for IR) --******************************************************************* --Entity Name : 'r*'nstruction #egister,

F2

--Entity Description : 'nstruction #egister stores the instruction address a ter it is -: etched rom the Memory" -: 'nstruction #egister synchroni6es -ith Clk7 8 #st --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input and utput !eclarations*************************** entity Ir is port ( 6ata : in stdLlogicLvector(-2 downto 0)B Cl(2 : in stdLlogicB 1dIr : in stdLlogicB Rst : in stdLlogicB Irout : out stdLlogicLvector (.D downto 0)B &pCode : out stdLlogicLvector(C downto 0) )B end IrB --******************************************************************* --Instruction address is used to "o to the address location in the 4emory --that contains the pCode and perand& --****************************************************************** architecture Ir o" Ir is begin process(Cl(2#Rst) --*********************(aria-le !eclarations************************ variable Iout : stdLlogicLvector(.D downto 0)B variable &code : stdLlogicLvector(C downto 0)B begin i" (RstNH0H)then Iout :N +000000000000000000000000000+B &code :N +00000+B Ir&utMNIoutB &pCodeMN&codeB elsi" (Cl(2Hevent and Cl(2NH2H)then i" (1dIrNH2H)then &code:N6ata(-2 downto .<)B Iout:N6ata (.D downto 0)B Ir&utMNIoutB &pCodeMN&codeB else Iout:NIoutB &code:N&codeB Ir&utMNIoutB

F.

&pCodeMN&codeB end i"B end i"B end processB end IrB

3.: *'ltiple<er The bloc( diagra o" Multiple$er Module is shown in 3igure.20.

(i 're 1=) *'ltiple<er

F-

Module Description: The Multiple$er is used to progra to cloc( cycle (3etch) the ultiple$ the outputs o" the instruction register and

counter i.e. IR&%T and 'C&%T respectively. This is done as# during the sa e e ory is accessed by both these registers. As a result we need

ultiple$ both o" the .

7HD. Co&e for *'ltiple<er) --******************************************************************* --Entity Name : Mu$*Multiple$er, --Entity Description : Multiple$er Multiple$es the outputs o 'nstruction #egister -*'r.ut, and !rogram Counter*!c.ut," --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input and utput !eclarations*************************** entity Mu$ is port ( Irout : in stdLlogicLvector(.D downto 0)B 'cout : in stdLlogicLvector (.D downto 0)B 3etch : in stdLlogicB Address : out stdLlogicLvector (.D downto 0) )B end Mu$B --******************************************************************* --'eed +or 4ultiplexin":--!urin" the same Cloc# Cycle the 4emory is accessed -y -oth Instruction --and ,ro"ram Counter Re"isters&5ence 1e need to 4ultiplex them& --******************************************************************* architecture Mu$ o" Mu$ is begin process(3etch#Irout#'cout) begin case 3etch is when H2H NP Address MN'coutB when H0H NP Address MNIroutB when others NP nullB end caseB end processB

FC

end Mu$B

3.; *emor+ The /loc( diagra o" Me ory Module is shown in 3igure. 22

(i 're 11) *emor+

Module Description: The Me ory in the RISC processor is located inside the processor. decreases the only two instructions that are used to access the This

e ory access ti es and i proves the speed o" the syste . There are e ory# the load and Store e ory.

accu ulator instructions. This is basically a RAM that is present inside the

The RISC &S physical. The logical the actual

achines wor( with two di""erent types o" e ory is the achine.

e ory ) lo"ical and er. e ory is

e ory as seen by the &S# and the progra

Jour application begins at O=000 and continues until O$$$$$. The physical e ory in the

FF

%nder RISC &S#

e ory is bro(en into pages. &lder e ory)# and newer

achines have a page o" ost li(ely

=K2DK-.@ (depending on installed

achines have a "i$ed C@ page.

I" you were to e$a ine the pages in your application wor(space# you would e ory# co bined to provide you with $$$$ bytes o" logical e ory.

see that the pages were see ingly rando # not in order. The pages relate to physical

The count how

e ory controller is constantly shu""ling

e ory around so that each tas( uch is

that co es into operation HbelievesH it is loaded at O=000. Erite a little application to any wi p polls occur every second# youHll begin to appreciate how going on in the bac(ground. 7HD. Co&e for *emor+) --******************************************************************* --Entity Name : Mem --Entity Description : The Memory in the #'SC !rocessor is located inside the -!rocessor" This decreases the Memory access times -and impro&es the speed o the system" --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input9 utput !eclarations****************************** entity Me is port ( Address : in stdLlogicLvector(.D downto 0)B Rd : in stdLlogicB Er : in stdLlogicB 6ata : inout stdLlogicLvector(-2 downto 0) )B end Me B --******************************************************************* --The only t%o Instructions that are used to access the 4emory are .oad --and Store 0ccumulator& --*******************************************************************

architecture Me o" Me is type e ory is array (0 to F00) o" stdLlogicLvector(-2 6&E>T& 0)B

FD

--****************************************************************** --+unction to con(ert 2:--it -inary to inte"er --******************************************************************* "unction toLinteger($ : in stdLlogicLvector(.D downto 0)) return integer is --********************(aria-le !eclararions***************************** variable Su : integer :N 0B variable Te p : StdLlogicLvector(.D downto 0)B begin Te p:N$B --******************************************************************* --;eneratin" the .oop to con(ert 2:--it -inary to inte"er --******************************************************************* $$$: "or i in 0 to .D loop i" (Te p(i)NH2H)then Su :N Su Q.99iB else Su :NSu B end i"B end loopB return Su B end "unctionB --******************************************************************* --The 4emory di(ided in to t%o sections& -- ne section is *or storin" the Instructions and another is *or !ata& --Results are also stored in !ata section only& --******************************************************************* ))Instruction 6eci al "or signal e : e ory:N( 8+F00000-.+# ))16A F0 8+000000--+# ))A66 F2 8+F=0000CD+# ))STA <0 8+F00000-.+# 8+.00000--+# 8+F=0000C<+# 8+F00000-.+# 8+-00000--+# 8+F=0000C=+# 8+F00000-.+# 8+.=0000--+# 8+F=0000CG+# ))16A ))A>6 ))STA ))16A ))8&R ))STA ))16A ))&r ))STA F0 F2 <2 F0 F2 <. F0 F2 <-

F<

8+F00000-C+# $+C0000000+# 8+C=000000+# 8+F=0000CA+# 8+F00000-.+# 8+<=0000--+# 8+F=0000C/+# 8+F00000-F+# 8+20000000+# 8+20000000+# $+2=000000+# 8+2=000000+# $+F=0000CC+# 8+F00000-.+# 8+-=000000+# 8+F=0000C6+# 8+F00000-D+# $+200000-<+# $+F=0000C;+# 8+F00000-D+# 8+220000-<+# $+F=0000C3+# 8+F00000-=+# 8+G00000-G+# 8+F=0000F0+# 8+F00000-=+# 8+G=0000-G+# $+F=0000F2+# 8+<0000000+# 8+<0000000+# 8+<0000000+# 8+<0000000+# 8+<0000000+# 8+<0000000+# 8+33330000+# 8+00003333+# 8+AAAAAAAA+# 8+00003333+# 8+0-CC00/=+# 8+020.C;C<+# 8+0-=0000C+#

))16A ))1S ))RS ))STA ))16A ))8>&R ))STA ))16A ))I>R ))I>R ))6CR ))6CR ))STA ))16A ))CMA ))STA ))16A ))3A66 ))STA ))16A ))3S%/ ))STA ))16A ))3M%1 ))STA ))16A ))36I4 ))STA

F0 )) )) <C F0 F2 <F F)) )) )) )) <D F0 )) << FC FF <= FC FF <G FD F< =0 FD F< =2 ))C0

))F0 ))F2 ))F. ))F))FC ))FF ))FD

F=

8+C2=0000F+# othersNP(othersNPH0H))B begin

))F<

process(Rd#Er) begin --******************************************************************* --%rittin" Results in to the 4emory --******************************************************************* i"(ErNH2Hand RdNH0H)then e (toLinteger(Address))MN 6ataB 6ataMN +RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR+B --******************************************************************* --Readin" Instructions and !ata *rom the 4emory --******************************************************************* elsi"(ErNH0H and RdNH2H) then 6ataMN e (toLinteger(Address))B else 6ataMN+RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR+B end i"B end processB end Me B 3.1= Acc'm'lator The bloc( diagra o" Accu ulator Module is shown in 3igure. 2.

(i 're 12) Acc'm'lator

FG

Module Description: The accu ulator is a -. bit register that is used to store one o" the operands or the result o" an operation. It is connected to both the A1% and the 6ata bus through a bu""er. All Accu ulator operations are synchroni!ed with the Cloc( 2 and InRst. Ehen the 16ACC is one with Cloc( 2 going through its positive edge# the Accu ulator is loaded "ro I" one the A1%&%T or the data "ro the Accu ulator is put on the 6ata /us.

odi"ies the basic RISC instruction so that the instructions do even less#

by having the operate instruction always wor( with operands in accu ulators# so that separate load and store instructions are reAuired even to access a register# one can actually obtain an architecture that is nearly eAuivalent to the CISC architecture# the three)address In one general aspect# a The ultiply unit includes a achine. icroprocessor ost co ple$ "or o"

ultiply unit is provided "or use in a

having at least one general)purpose register "or storing a predeter ined nu ber o" bits. ultiplier and an e$tended)precision accu ulator including ore bits than each o" the general)purpose registers. I ple entations include using the whereby operands to the and a polyno ial ultiply unit are e$tended)precision accu ulator. The ultiplier. ultiplier i ple entation# a ultiply)add operation ultiplies ultiplier to provide a ultiply)add operation ultiplier

ultiplied and added to the contents o" the ay include an arith etic

ultiplier

In a polyno ial

two operands and adds the result to the contents o" the e$tended)precision accu ulator using an e$clusive)or operation. In so e i ple entations# the e$a ple# the result logic ay be i ple ented as a ultiple$er. ultiplier includes result logic "or selecting which values to load into the e$tended)precision accu ulator. 3or

In so e i ple entations# the e$tended)precision accu ulator includes an e$tended register# a high)order register# and a low)order register. 3or e$a ple# the e$tended register ay store =)bit values and the other two registers ay store -.)bit

D0

values. Instructions are provided "or precision accu ulator. &ne instruction oves a value "ro

anipulating the contents o" the e$tended)

the e$tended)precision accu ulator into a oves a value "ro a general)

general)purpose register and an inverse instruction ay shi"t the contents o" the e$tended)precision register. 7HD. Co&e for Acc'm'lator)

purpose register into the e$tended)precision accu ulator. The instructions additionally

--****************************************************************** --Entity Name : )cc --Entity Description : )ccumulator stores one o the .perands or #esult o an --.peration" 't is connected to both the )%+ and Data 0us through 0u er --******************************************************************** library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input and utput !eclarations************************* entity Acc is port ( Alu&ut: in stdLlogicLvector(-2 downto 0)B Rst : in stdLlogicB 1dAcc : in stdLlogicB Cl(2 : in stdLlogicB Acc&ut: out stdLlogicLvector (-2 downto 0) )B end AccB ))99999999999999999999999999999999999999999999999999999999999999999999 ))All Accu ulator &perations are Synchroni!ed with the Cl(2 and Rst ))9999999999999999999999999999999999999999999999999999999999999999999 architecture Acc o" Acc is begin process(Cl(2#Rst) --*********************(aria-le !eclaration**************************** variable Ac&ut:stdLlogicLvector( -2 downto 0)B begin i"(RstNH0H) then Ac&ut:N8+00000000+B Acc&utMNAc&utB
D2

elsi"(Cl(2Hevent and Cl(2NH2H)then i"(1dAccNH2H)then Ac&ut:NAlu&utB Acc&utMNAc&utB else Ac&ut:NAc&utB Acc&utMNAc&utB end i"B end i"B end processB end AccB

3.11 $'ffer The bloc( diagra o" /u""er Module is shown in 3igure. 2-

(i 're 13) $'ffer

D.

Module Description: The /u""er is used between the A1%&%T and the 6ata /us. %nder nor al circu stances the A1%&%T is connected to the Accu ulator. /ut when ER is 2 then# A1%&%T is a pli"ied and put on the 6ata /us. &therwise the A1%&%T is connected to the Accu ulator. 7HD. Co&e for $'ffer) --******************************************************************* --Entity Name : 0u *0u er, --Entity Description : 0u er acts as intermediary bet-een )lu.ut and the Data 0us --******************************************************************* library I;;;B use I;;;.stdLlogicL22DC.allB --***************Input and utput !eclarations*************************** entity /u" is port ( ;nb : in stdLlogicB Aluout : in stdLlogicLvector(-2 downto 0)B 6ata : out stdLlogicLvector(-2 downto 0) )B end /u"B --******************************************************************* --6nder normal Conditions 0lu ut is al%ays connected to the 0ccumulator& --2u**er is made acti(ated %hen %e %ant to store the Results in 4emory& --******************************************************************* architecture /u" o" /u" is begin process(;nb#Aluout) begin i"(;nbNH2H)then 6ataMNAluoutB elsi"(;nbNH0H)then 6ataMN+RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR+B end i"B end processB end /u"B

D-

3.12 TOP *o&'le 7HD. Co&e for TOP *o&'le) library I;;;B use I;;;.stdLlogicL22DC.allB entity Top. is port ( Cloc(2 :in stdLlogicB Cloc(. : in stdLlogicB 3etch : in stdLlogicB RstReA : in ST6L1&7ICB con :out stdLlogicLvector(. downto 0)B ldpc : inout stdLlogicB Incpc : inout stdLlogicB ldir : inout stdLlogicB ldacc : inout stdLlogicB &pCode : inout stdLlogicLvector(C downto 0)B Irout : inout stdLlogicLvector (.D downto 0)B

DC

pcout : inout stdLlogicLvector (.D downto 0)B 6ata : inout ST6L1&7ICL4;CT&R(-2 downto 0)B Address : inout ST6L1&7ICL4;CT&R(.D downto 0)B Rd : inout ST6L1&7ICB Er : inout ST6L1&7ICB cl( : inout stdLlogicB aluout : inout stdLlogicLvector(-2 6&E>T& 0)B accout : inout stdLlogicLvector(-2 6&E>T& 0) )B end Top.B architecture Top. o" Top. is co ponent Res is port ( RstReA : in ST6L1&7ICB Cl(. : in ST6L1&7ICB 3etch : in ST6L1&7ICB Rst : out ST6L1&7IC )B end co ponentB co ponent ControlL1ogic is port ( Cl(2 : in ST6L1&7ICB Cl(. : in ST6L1&7ICB 3etch : in ST6L1&7ICB Rst : in ST6L1&7ICB &pCode : in ST6L1&7ICL4;CT&R (C downto 0)B 1dIr : out ST6L1&7ICB Inc'c : out ST6L1&7ICB 1d'c : out ST6L1&7ICB 1dAcc : out ST6L1&7ICB Rd : out ST6L1&7ICB Er : out ST6L1&7IC )B end co ponentB co ponent Acc is port ( Alu&ut : in ST6L1&7ICL4;CT&R (-2 downto 0)B Rst : in ST6L1&7ICB 1dAcc : in ST6L1&7ICB Cl(2 : in ST6L1&7ICB Acc&ut : out ST6L1&7ICL4;CT&R (-2 downto 0))B end co ponentB co ponent 'c is port ( Irout Rst

: in ST6L1&7ICL4;CT&R (.D downto 0)B : in ST6L1&7ICB

DF

Inc'c 1d'c 'cout )B end co ponentB

: in ST6L1&7ICB : in ST6L1&7ICB : out ST6L1&7ICL4;CT&R (.D downto 0)

co ponent Ir is port ( 6ata : in ST6L1&7ICL4;CT&R (-2 downto 0)B Cl(2 : in ST6L1&7ICB 1dIr : in ST6L1&7ICB Rst : in ST6L1&7ICB Irout : out ST6L1&7ICL4;CT&R (.D downto 0)B &pcode : out ST6L1&7ICL4;CT&R(C downto 0) )B end co ponentB co ponent Mu$ is port ( Irout : in ST6L1&7ICL4;CT&R(.D downto 0)B 'cout : in ST6L1&7ICL4;CT&R(.D downto 0)B 3etch : in ST6L1&7ICB Address : out ST6L1&7ICL4;CT&R(.D downto 0) )B end co ponentB co ponent /u" is port ( ;nb : in ST6L1&7ICB Aluout : in ST6L1&7ICL4;CT&R (-2 downto 0)B 6ata : out ST6L1&7ICL4;CT&R (-2 downto 0) )B end co ponentB co ponent Me is port ( Address :in ST6L1&7ICL4;CT&R (.D downto 0)B Rd : in ST6L1&7ICB Er : in ST6L1&7ICB 6ata : inout ST6L1&7ICL4;CT&R (-2 downto 0) )B end co ponentB co ponent Alu is port ( 6ata : in ST6L1&7ICL4;CT&R (-2 downto 0)B Acc&ut : in ST6L1&7ICL4;CT&R (-2 downto 0)B &pCode : in ST6L1&7ICL4;CT&R (C downto 0)B Cl( : in ST6L1&7ICB

DD

Rst : in ST6L1&7ICB Aluout : out ST6L1&7ICL4;CT&R (-2 6&E>T& 0) )B end co ponentB signal Rst : stdLlogicB begin a:Res port ap (RstReA#Cloc(2#3etch#Rst)B b:ControlL1ogic port ap (cloc(2#Cloc(.#3etch#Rst#&pCode#1dIr#Inc'c#1d'c#1dAcc#Rd#Er)B c:Acc port ap (Alu&ut#Rst#1dAcc#Cloc(2#Acc&ut)B d:'c port ap (Irout#Rst#Inc'c#1d'c#'cout)B e:Ir port ap (6ata#Cloc(2#1dIr#Rst#Irout#&pCode)B ":Mu$ port ap (Irout#'cout#3etch#Address)B g:/u" port ap (wr#Aluout#6ata)B h:Alu port ap (6ata#Acc&ut#&pCode#cl(#Rst#Alu&ut)B i:Me port ap (Address#Rd#Er#6ata)B cl(MNcloc(2 or cloc(. or "etch B con MN cloc(2Ocloc(.O"etchB end top.B

CHAPTER 1 %I*U.ATION RE%U.T%

1.1 Intro&'ction This chapter concentrates on the -.)/it RISC processor code is Si ulate in Active)561 tool (A16;C). The -.)/it RISC processor can be si ulated using the structural. Source code -.)/it RISC processor "ound in the si ulation directory (i.e.# Active)561 directory).

D<

1.2 Cloc4 5enerator %im'late& >a,eform

D=

(i 're 11) Cloc4 5enerator >a,eform The above wave"or re"ers to the Cloc( 7enerator. 3or the Cloc( 7enerator the ainly depends upon the Rst.

inputs are Cl(2 and Reset ReAuest (Rst). The output De"cription)

Ehenever Rst is high# a"ter one cloc( pulse Cloc(. and 3etch is high# at the sa e ti e 3etch2 and Cl(. is also sa e as that o" Cloc(. and 3etch. Ehenever cloc( is high the 3etch is going to be 3etch the instruction# and send to the instruction register. Ehenever Rst is low# a"ter one cloc( pulse Cloc(. and 3etch is low# at the sa e ti e 3etch2 and Cl(. is also sa e as that o" Cloc(. and 3etch (i.e.# 1ow).

1.3 Re"etter %im'late& >a,eform

DG

(i 're 12) Re"etter >a,eform The above wave"or RstReA. De"cription) Ehenever RstReA is high# a"ter one cloc( pulse o" Cl(.# then only Rst is high. It doesnTt depends on the 3etch signal. Ehenever RstReA is low# a"ter one cloc( pulse Cl(.# then Rst is low. re"ers to the Resetter Eave"or . 3or the Resetter the ainly depends upon the

inputs are Cl(.# 3etch and Reset ReAuest (Rst). The output

1.1 Control .o ic Deco&er %im'late& >a,eform

<0

(i 're 18) Control .o ic Deco&er >a,eform The above wave"or re"ers to the Control 1ogic 6ecoder Eave"or . 3or the ainly

C16 the inputs are Cl(2# Cl(.# 3etch# &pcode and Reset(Rst). The output depends upon the Rst and &pcode. De"cription)

Ehenever Cl(2# Cl(.# Rst and 3etch is high# then the instruction is going to be load into the Instruction Register. Ehen the 3etch is low# whatever the value is "etched# that value is going to be loaded in the Accu ulator continuously.

1.2 Arithmetic .o ic Unit %im'late& >a,eform

<2

(i 're 19) Arithmetic .o ic Unit /a,eform The above wave"or re"ers to the Arith etic 1ogic %nit Eave"or . 3or the ainly

A1% the inputs are 6ata# Accout# Cl(# &pcode and Reset(Rst). The output depends upon the Rst and &pcode. De"cription)

%ser asserting the values on 6ata# Accu ulator out# Cl( and &pcode# whenever Rst is high# then the instruction is going to be e$ecuted by the &pcode Instruction# then the data will be appeared in Arith etic 1ogic %nit out.

<.

1.8 Pro ram Co'nter %im'late& >a,eform

(i 're 1:) Pro ram Co'nter >a,eform The above wave"or and Inc'c. De"cription) Ehenever Irout# Inc'c and Rst is high# then 'cout is incre ented by one location. I" Rst is low the 'cout is going to be previous state (i.e.# initial position o" 'cout). re"ers to the 'rogra Counter Eave"or . 3or the 'C the ainly depends upon the Rst# Irout

inputs are Ir&ut# Rst# Inc'c# and 1d'c. The output

<-

1.9 In"tr'ction Re i"ter %im'late& >a,eform

(i 're 1;) In"tr'ction Re i"ter >a,eform The above wave"or re"ers to the Instruction Register Eave"or . 3or the Ir the ainly depends upon the Rst and 1dir.

inputs are 6ata# Cl(2# 1dir and Rst. The output De"cription)

5ear input is -.)bit data# in this -.)bit data .<)bit is assigning to the Irout and re aining bits assigning to &pcode. This is possible only when the Rst# 1dIr and Cl(2 are in high state. &therwise the data will be not split# even though 1dIr and Cl(2 is high (it is possible when Rst is in 5igh state).

<C

1.: *'ltiple<er %im'late& >a,eform

(i 're 2=) *'ltiple<er >a,eform The above wave"or re"ers to the Multiple$er Eave"or . 3or the Mu$ the ainly depends upon 3etch.

inputs are Irout# 'cout and 3etch. The output De"cription)

Ehenever 3etch is low# then Address is assigning the Irout value. I" 3etch is high the Address is going to be assigned 'cout. The co plete operation o" the Mu$ depends on 3etch state.

<F

1.; *emor+ %im'late& >a,eform

(i 're 21) *emor+ >a,eform The above wave"or re"ers to the Me ory Eave"or . 3or the Me ory the ainly depends upon Rd.

inputs are Address# Rd and Er. The output De"cription)

Ehenever the Address value is given# Rd value is high# then the Address value is assigned to the 6ata and Me ory input. The output will be stored in Me ory location# and the result will be displayed in 6ata.

<D

1.1= Acc'm'lator %im'late& >a,eform

(i 're 22) Acc'm'lator >a,eform The above wave"or 1dAcc. De"cription) Ehenever the Aluout value is given# Rst# 1dAcc and Cl(2 value is high# then the Aluout value is assigned to the Accout. The Accu ulator is behave li(e as Aluout data pointer a"ter all the states is satis"ied and one cloc( pulse. Ehen the Reset value is low the Accout value will go to initial state (i.e.# assigned !ero value). re"ers to the Accu ulator Eave"or . 3or the Accu ulator ainly depends upon Rst and

the inputs are Aluout# Rst# 1dAcc and Cl(2. The output

<<

1.11 $'ffer %im'late& >a,eform

(i 're 23) $'ffer >a,eform The above wave"or re"ers to the /u""er Eave"or . 3or the /u""er the inputs ainly depends upon ;nb.

are ;nb and Aluout. The output De"cription)

Ehenever the ;nb value is high# then the Aluout value is assigned to the 6ata. The /u""er will stores the data "or te porarily. Ehen the ;nb value is 1ow# then the 6ata will be shows as 5igh I pedance value (i.e.# RRR).

<=

1.12 Top *o&'le %im'late& >a,eform

(i 're 21) Top *o&'le >a,eform The above wave"or RstReA. De"cription) Ehen Cloc(2N0# Cloc(.N0# RstReAN2 and 3etchN2# then Rd is high# 1dir is high and at the sa e ti e the data will be appear on the 6ata bus. Ehen Cloc(2N2# Cloc(.N2# RstReAN2 and 3etchN2# then Rd is high# 1dir is low and at eh sa e ti e the previous data will be appear on the Irout. I" RstReA is low even though other signals are high# the output will be initial state(i.e.#all are !eroTs). re"ers to the Top Module Eave"or . 3or the Top Module ainly depends upon

the inputs are Cloc(2# Cloc(.# 3etch and RstReA. The output

<G

CHAPTER 2 CONC.U%ION% ? (UTURE %COPE

2.1 Concl'"ion In this pro,ect it is observed that the RISC based syste 4561. The overall syste is si ulated using

is si ulated and synthesi!ed# a"ter synthesi!ing the syste

we could get a statistical data about the nu ber o" input)output bu""ers# the nu ber o" registers# nu ber o" "lip)"lops and latches were used in the usage o" 3'7A tool. The odules si ulated are Accu ulator# /u""er# Cloc( 7enerator# Instruction Register# Multiple$er# 'rogra Counter# Resetter# Control 1ogic 6ecoder# Arith etic 1ogic %nit

and the overall syste . 3ew instructions were e$ecuted and their ti ing seAuences were analy!ed. It is "ound that an each instruction ta(en C0ns.It shows that the di""erent operations o" the instruction including the decoding and e$ecution co es to C0ns in the overall syste . There"ore we conclude that the behavior shows# the syste as RISC as instruction will be e$ecuted within a single cloc( cycle. is wor(ing

=0

2.2 ('t're %cope of the Project The "loating)point incorporates only an 22)bit ultiplication is not a co plete -.)bit operation as it antissa. This can be i proved by ultiple$ing the result

or# by using the concept o" pipelining. A co piler to this processor can be reali!ed in so"tware to "acilitate easy input and output to this processor. The -.)bit processor can be ade to a DC)bit processor a(ing inor odi"ications to the code. This increases the

data handling capability o" the A1%. It also increases the range o" nu bers that can be operated by the processor. The e$ception cases in the arith etic operations can be "lashed to the user using seven seg ent displays. %sing the co piler can "acilitate these operations.

=2

APPENDI@ A

Intro&'ction to 7HD.) It is noticed "ro the available literature that the %nited States organi!ed a In 2G=-# 6epart ent o" 6e"ense (6&6) endation o" the wor(shop. o"

wor(shop in 2G=2 to search "or a standard design and docu entation tool "or the very high)speed integrated circuits (45SIC). established a standard 4561 based on the reco

;""orts "or de"ining the new version o" 4561 started in 2GG0 by a tea volunteers wor(ing under the I;;; 6ASC (6esign Auto ation Standards Co review. A"ter balloting group inor

ittee).

In &rder o" 2GG.# a new 4561 re"erred as 4561 G- was co pleted and released "or odi"ications# this new version was approved by the 4561 e bers and beca e the new 4561 language standard. "or 4ery 5igh Speed Integrated Circuits 5ardware odel a digital syste at any The the algorith ic level to the 7ate level. odeled would vary "ro

4561 is an acrony

6escription 1anguage. The language can be used to levels o" abstraction ranging "ro co ple$ity o" the digital syste being

that o" a si ple gate to

a co plete digital electronic syste . The 4561 1anguage can be regarded as an integrated a alga ation o" seAuential language# concurrent language# net list language# ti ing speci"ications and wave"or The co ple$ and laborious generation language. anual procedures "or the design o" the hardware

have paved the way "or the develop ent o" languages "or high level description can serve as docu entation "or the part as well as an entry point into the design process. The high level description can be processed through various steps in order to si ulate the hardware in the "or o" layout# printed circuit board or gate arrays using the synthesis tools o" hardware description languages. The I;;; standard 4561 hardware description language is such a language. 4561 was designed as a solution to provide an integrated design and docu entation to co unicate design data between various levels o" abstraction.

=.

De"i n Unit" in 7HD.) 4561 provides "ive di""erent types o" pri ary constructs called design units. They are: 2. .. -. C. F. ;ntity declaration Architecture body Con"iguration declaration 'ac(age declaration 'ac(age body An entity is odeled using an entity declaration and at least one architecture is called an entity). odeled and lists unicates with

body (A hardware abstraction o" the digital syste

The ;ntity declaration speci"ies the na e o" the entity being the set o" inter"ace ports. 'orts are signals through which the entity co the other odels in its e$ternal environ ent. e$ternal view o" the entity.

So entity declaration describes the

The architecture body contains the internal description o" the entity.

3or

e$a ple# as a set o" concurrent or seAuential state ents that represents the behavior o" the entity. ;ach style o" representation can be speci"ied in a di""erent architecture body or i$ed within a single architecture body. There"ore an architecture body using any o" odeling styles speci"ies the internal details o" an entity. 3ig. 2.2 shows odel. the "ollowing

an entity and one possible

A con"iguration declaration is used to create a con"iguration "or an entity. It speci"ies the binding o" one architecture body "ro ay be associated with the entity. It di""erent con"igurations. A pac(age declaration encapsulates a set o" related declarations# such as type declarations# subtype declarations and subprogra across two or ore design units. declarations# which can be shared the any architecture bodies that ay have any nu ber o" ay also speci"y the bindings o" co ponents used

in the selected architecture body to other entities. An entity

=-

A pac(age body contains the de"initions o" sub progra s declared in a pac(age declaration.

(i 3) Pac4a e Declaration

A&,anta e" of 7HD.) The "ollowing are the a,or capabilities that the language provides along with other hardware description languages. unication ediu between di""erent

the "eatures that di""erentiate it "ro

2) The language can be used as a co

Co puter Aided 6esign (CA6) and Co puter Aided ;ngineering (CA;) tools. .) The language supports hierarchy i.e.# a digital syste inter connected sub co ponents. -) The language supports "le$ible design or i$ed. odel can ethodologies i.e.# top)down# botto )up can be odeled as a set o" odeled as a set o"

inter connected co ponents# each co ponent in turn can be

C) The language is technology independent and hence the sa e behavior be synthesi!ed into di""erent vendor libraries. F) It supports both Synchronous and Asynchronous ti ing odel.

=C

D) 4arious digital language.

odeling techniAues such as "inite)state

achine descriptions# odeled using the

algorith ic descriptions and /oolean eAuations can be

<) It is an I;;; and A>SI standard. There"ore

odels described using these aintaining ay beco e easier.

languages are portable. The govern ent also has strong interest in this as standard so that reprocure ent and second sourcing =)

There are no li itations that are i posed by the language on the si!e o" the design. The sa e odel can be synthesi!ed into di""erent vendor libraries. a(e large)scale design odeling easier. 3or

G) The language has ele ents that

e$a ple co ponents# "unctions# procedures and pac(ages. 20) The language supports three basic di""erent description styles i.e.# structural# data "low and behavioral. A design o" these three descriptive styles. 22) It supports a wide range o" abstraction levels ranging "ro descriptions to very precise gate level descriptions. abstract behavioral ay also be e$pressed in any co bination

(loatin Point ('nction") 2) 3loating 'oint 3unctions are incorporated into the design by writing the odule. .) Care should be ta(en that all the inputs given should be in the I;;;)<FC standard. The outputs obtained will also be in this "or at. -) The Co piler o" the operating syste will do the conversion "ro the I;;; into

A1%. They are written as "unctions and are called at the beginning o" the

"or at to the deci al "or at we are acAuainted to. C) The inputs should be given ta(ing the physical li itations o" the registers into consideration. They should not be overloaded# lest the data lose its legiti acy by getting truncated.

=F

F) The carry generated in operations is displayed through part by one.

essage and it is ad,usted antissa

in the result by incre enting the e$ponent value and right shi"ting the

(loatin Point IEEE # 921 %tan&ar& (ormat") A "loating * point nu ber is the one# which is capable o" representing real and deci al nu bers. The "loating)point operations are incorporated into the design as "unctions. The logic "or these is di""erent "ro the ordinary arith etic "unctions.

The nu bers in convention have to be "irst converted into the standard I;;; <FC "loating point standard representation be"ore any sort o" operations are conducted on the . The I;;;)<FC standard represents the real nu ber > given by the "or ula >N()2)S .;)2.< (2.M) The "loating * point representation "or a standard single precision nu ber is.

A single precision nu ber is a -.)bit nu ber that is seg ented to represent the "loating * point nu ber. The above representation is the I;;;)<FC standard representation. The MS/ is the sign)bit i.e.# the sign o" the "loating point nu ber. The ne$t eight bits are that o" the e$ponent. The e$ponent in this I;;; standard is represented in e$cess * 2.< "or at i.e.# the e$ponent obtained by balancing operations is added to 02222222. There"ore !ero is represented by 02222222. 'ositive nu bers are represented by binary values greater than 02222222 and negative nu bers are represented by binary values less than it. The logic "or "loating point addition# subtraction# presented in the "ollowing pages. ultiplication and division is

=D

(loatin Point A&&ition)

2) The real nu ber is "irst represented in the I;;;)<FC standard "loating point representation. .) These nu bers are stored into the processed. -) >ow the nu bers "ro bus. C) These nu bers are distinct. So to add their their e$ponents. F) So# we co pare the e$ponents and incre ent the e$ponent o" the lower e$ponent while right shi"ting its beco es eAual to the higher one. D) &nce the e$ponents are nor ali!ed. The antissas are then added to each other antissa. This is done till the lower e$ponent antissas# we have to "irst nor ali!e the e ory are loaded into two registers# na ely e ory "ro which they are read and

Accu ulator and the Te p register that loads the value appearing on the data

and the result is then stored in a te porary register. <) The e$ponent that is now nor ali!ed is concatenated with the resulting and the sign o" the result that is calculated separately. antissa

=<

(i 18) (loatin Point A&&ition or %'3traction

==

(loatin Point %'3traction)

2) The real nu ber is "irst represented in the I;;;)<FC standard "loating point representation. .) These nu bers are stored into the processed. -) >ow the nu bers "ro bus. C) These nu bers are distinct. So to subtract their nor ali!e their e$ponents. F) So# we co pare the e$ponents and incre ent the e$ponent o" the lower e$ponent while right shi"ting its beco es eAual to the higher one. D) &nce the e$ponents are nor ali!ed. The result is stored in a te porary register. <) The e$ponent that is now nor ali!ed is concatenated with the resulting and the sign o" the result that is calculated separately. =) 3loating point addition and subtraction have been possible due to the "act that /inary single)bit addition and subtraction are de"ined in 4561. G) The a,or di""erence between Addition and subtraction is in the sign o" the "inal the there is no di""erence in the antissa antissas are then subtracted and the antissa. This is done till the lower e$ponent antissas# we have to "irst the e ory are loaded into two registers# na ely e ory "ro which they are read and

Accu ulator and the Te p register that loads the value appearing on the data

result that is calculated separately. Apart "ro subtraction is carried out.

procedure o" nor ali!ing the nu bers be"ore the business o" Addition or

=G

(loatin Point *'ltiplication)

2) 5ere the e$ponents and nor ali!ed. .) In

antissas o" the nu bers in convention don:t have to be

ultiplication the operations are done si ultaneously and separately on the

antissa and the e$ponent. -) /inary ultiplication is de"ined "or single bit nu bers in 4561# so the antissas are ultiplied

e$ponents are ,ust added and the individual bits in the to get the "inal result.

C) The "inal output is obtained by concatenating the product o" the

antissas# the

resulting e$ponent and the sign o" the result that is calculated separately. F) There is however a li itation to this operation. I" two nu bers o" >)bits are ultiplied then the resulting nu ber will be o" .>)bits thereby decreasing the nu erical scope o" the inputs. D) So each input should not e$ceed 2.)bits in length# so that the result is restricted to not ore than .C bits.

G0

(i 19) (loatin Point *'ltiplication

G2

(loatin Point Di,i"ion)

2) This is antissa.

ore co plicated than Multiplication# owing to the "act that apart "ro

ta(ing care o" the e$ponent we have to consider the cases o" dealing with the

.) The logic "or "loating point division is as "ollows. -) 3irst the e$ponents are directly added or subtracted depending on which is bigger. Apart "ro that the "inal sign o" the division is calculated separately.

C) >ow both the nu bers in the I;;;)<FC standard "or at are co pared. The convention here is that the >u erator should be always less than the 6eno inator. This is to ensure that whatever co es as the result is a"ter the deci al point. The deci al is assu ed to be be"ore the MS/ o" the resulting Auotient. F) >ow since the greater o" the two nu bers is decided# i" the >u erator is less than the 6eno inator then we proceed to append the value o" the nu erator to .C !eros and load it into an internal register say Te p that consists o" CG)bits. >ow the "irst .C)bits "ro D) I" the divisor is the MS/ are co pared with the divisor.

ore than the dividend then we le"t shi"t the dividend by 2 and

add it to the two:s co ple ent o" the divisor. <) The result is stored in Te p# i" the MS/ or the CG th bit is one than we add a one in the Auotient. And i" it is !ero# we put a !ero in the Auotient. =) Ee initiate a counter and carry this process "or .C ti es till the Auotient is "ull. G) &nce the Auotient is "ull# we append it with the e$ponent value and the Sign o" the division that are calculated separately.

G.

(i 1:) (loatin Point Di,i"ion

G-

aA A&&re"" %et'p 1) 5ere all control signals load Accu ulator (16ACC)# 1oad 'rogra Incre ent 'rogra Erite (ER) are initiali!ed to Rero. 3A In"tr'ction (etch) In this stage UR6: control signal is "etching o" an instruction is over. cA In"tr'ction .oa&) At the positive edge o" the cloc( 2 and when both R6 and 16IR are bit instruction is "etched "ro the ade high the -.) ade high so that opcode and operand address are the e ory which eans Counter (16'C)#

Counter (I>'C)# 1oad Instruction Register (16IR)# Read (R6)#

placed on the data bus i.e.# reading an instruction "ro

e ory and is loaded into Instruction Register. 3irst

"ive MS/ acts as &pcode which is connected to both A1% and Control 1ogic 6ecoder# Re aining .<)bits represent the address o" the operand. &A I&le) In this stage no operation is per"or ed but the cloc( is running which will be ter ed as idle state appro$i ately Fns. eA A&&re"" %et'p 2) As shown in the /loc( 6iagra at the Control 1ogic 6ecoder the pin I>C'C is e ory location as already

elevated to high level and then the pointer points to the ne$t an instruction has been "etched early. The above said stages are very co

on "or the "etching o" an instruction.

GC

fA Operan& (etch) %nder nor al conditions the output o" the A1% is always connected to the Accu ulator. operation. 3or ;$a ple the instructions li(e A66# S%/# 3A66# 3S%/# 3M%1# 36I4# A>6# &R# 8&R# 8>&R# etc. second operand is loaded into Accu ulator by a(ing the control signals such as 1oad Accu ulator 16ACC and Read R6 as high as possible. 3or special instructions such as ?u p# S(ip# 51T the "ollowing are the procedures adopted to e$plain the operation. iA BU*P In"tr'ction) /y a(ing load progra counter (16'C) signal as unity# the value present in the output counter. The address o" So# that the second operand is loaded into Accu ulator "or "urther

o" the Instruction Register# IR&%T is loaded into the progra the progra e$ecuted. iiA %CIP In"tr'ction) 7enerally progra is counter (eeps on incre enting by

counter is changed to the ,u p address where the current instruction to be

a(ing Incre ent 'rogra

Counter Signal# I>C'C as unity in Address setup . stage. &nce again when the I>C'C ade unity during the operand "etch stage the i ediate ne$t location is s(ipped and points to the ne$t address location. iiiA H.T In"tr'ction) The processor is halted "or so e ti e and no operation is per"or ed during that ti e. The &pcode "or the 51T operation is U02220: (;).

GF

A Arithmetic an& .o ic Unit DA.UA) 3ew instructions were tried and e$ecuted using the A1%. The "loating point "unctions are also carried out to si ulate the test signals. Two operands "etched "ro the e ory are stored in Accu ulator and Te porary Register o" A1%. 'articular operation is per"or ed on these two operands depends upon the &pCode given. The result is always stored in Accu ulator only. Suppose "or every instruction i" new operand is not given# then the operation will be per"or ed on the previous value stored in the Accu ulator. hA %tore Re"'lt") /u""er is inter"ace between the output o" the A1% (A1%&%T) and 6ata /us. %nless and otherwise it is speci"ied the results will be in the Accu ulator. &therwise the results will be stored in e ory via bu""er by a(ing write (ER) control signal as high.

There is a necessity to access the

e ory location si ultaneously by both 'rogra There"ore we need the Counter and Instruction Register. The

Counter and Instruction Register during the 3etch Cycle. ultiple$er "or both the &utput o" 'rogra

selection o" IR&%T and 'C&%T depends upon the 3etch Cycle. /y way o" si ulating the di""erent the end. odules and the overall circuit results were obtained

and the sa e was reali!ed by synthesis tools and the synthesis results also tabulated at

GD

APPENDI@ $

CISC RISC C1% A1% M%8 'C IR 45SIC 6&6 6ASC CA6 CA; 16ACC 16'C 16IR I>'C R6 ER C'% A% 1%

) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )

Co ple$ Instruction Set Co puter Reduced Instruction Set Co puter Control 1ogic %nit Arith etic 1ogic %nit Multiple$er 'rogra Counter Instruction Register 4ery 5igh)Speed Integrated Circuits 6epart ent o" 6e"ense 6esign Auto ation Standards Co Co puter Aided 6esign Co puter Aided ;ngineering 1oad Accu ulator 1oad 'rogra Counter Counter 1oad Instruction Register Incre ent 'rogra Read Erite Co puter 'rocess %nit Arith etic %nit 1ogic %nit ittee

G<

/asic 6esign Methodology

G=

3lowchart o" 561 6esign ;ntity

;$a ple o" 6u ping 'rogra

into 5ardware @it

GG

0'0%.G#)!29

2) .) -) C) F) D)

A 4561 'ri er -rd edition by ?. /has(er. 6igital Syste 6esign %sing 4561 by Charles 5 Roth ?r.

4561 by 6ouglas 1. 'erry. A 4561 Synthesis 'ri er by ?./has(er. Co puter Architecture and &rgani!ation by ?ohn '. 5ayes. Co puter &rgani!ation and Architecture by Eillia Stallings.

Eebsites: 2) .) -) C) F) D) <) 8) www.aldec.co KproductsKtutorials. www.toolbo$.$ilin$.co Kdocsan. www.csold.cs.ucr.eduKcontentKesdKlabsKtutorialKvhdlLpage.ht l. www.psc.eduKgeneralKso"twareKpac(ages KieeeKieee.ht l.. www.leepoint.netKnotes)co pKdataKnu bersKieee<FC.ht l. www.cs.ber(ely.eduK www. ecaulay.ac.u"K"earlusK"loating)point www.carlstedt.seKhyldoKdatorar(ite(turKtidigare

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