Analog Layout

OUTLINE
Introduction The CMOS Technology Layout of MOS Transistors Layout of Resistors Layout of Capacitors
IC Technology & Layout
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INTRODUCTION
Integrated Circuit: single component including a large number of active and passive devices and their interconnections to realize complex functions Monolithic Technology: all devices are realized on the same silicon crystal Planar Technology: all processing steps act on a very thin surface layer of the wafer " all ICs on the same wafer are realized simultaneously " fabrication costs are largely reduced
PROCESSING STEPS
Modication of surface electrical characteristics of the wafer or deposition of lms of various materials thermal oxidation ion implantation thermal diffusion epitaxy lm deposition Photolithographic processes masking selective etching
THE CMOS TECHNOLOGY

Available devices: n-channel MOS transistors p-channel MOS transistors resistors capacitors diodes (typically used for ESD protection) vertical bipolar transistors
Silicon gate Source Drain Thin oxide Metal Field oxide p-channel n-channel p-well
n-substrate
TYPICAL CMOS P-WELL PROCESS

Tox= 100nm SiO 2
thermal oxidation
Photoresist
Boron 80 keV; 3 x 1012/cm2
+++++++++
p-well implant
300 nm 3 m p-well
p-well diffusion oxidation

20 nm 100 nm Si 3N4 p-well
thin oxide growth active area definition
Boron 100 keV
++ n Phosphorus 40 keV
p-well
++
p-implant isolation
++
p-well
++
n-implant isolation

600 nm
n n p p
p-well
field oxide growth
Boron 30 keV; 2 x 1011/cm2
p-well
additional implant to adjust threshold voltages
50 nm
polysilicon
n p p
p-well
definition of polysilicon gates and capacitor bottom plates

arsenic 100 keV; 3 x 1015/cm2
- -
n-channel source & drain implant and diffusion
p-well
boron 50 keV; 2 x 1015/cm2
++
++
n+
n+
p-channel source & drain implant and diffusion
n polysilicon 2
n
p+ p+
p-well
n+
n+
definition of capacitor top plate
p-well

contact opening metal deposition possibly: thermal oxidation via opening second metal layer deposition final passivation using silicon nitride (Si3N4) (typical thickness 1 m)
aluminium
p+ p+ n+ n+
p-well
DIFFERENCES LAYOUT - CIRCUIT

Why a designed layout and its corresponding real circuit are different? lateral diffusion etching under protection boundary dependent etching three-dimensional effects and the errors and limitations associated with mask production and mask alignment.
SiO2 protection
L
MASK
MASK
L1
x etched layer
0.6 - 0.8 x LATERAL DIFFUSION
undercut
more active
less active
THREE-DIMENSIONAL EFFECTS
ETCHING UNDER PROTECTION
BOUNDARY DEPENDENT ETCHING
LAYOUT OF MOS TRANSISTORS

In the layout of a digital transistor the speed, the load driving capability and the area optimization are key issues Matching, accurate aspect ratio (W/L), noise are not very important
Drain Gate
Source
Source
Gate Drain
Active Area Poly
Metal Contact
Extreme situation of a layout of a digital transistor

LAYOUT OF MOS TRANSISTORS

In the layout of analog transistors it is important to: have an accurate aspect ratio (straight structures) minimise the stray resistance in series with source and drain reduce the gate series resistance For wide transistors it is worthwhile to split the layout into the parallel connection of many elements (stacked configuration) Layout of an analog transistor
Source
Drain
Gate
Active Area Poly
Metal Contact
TRANSISTOR MATCHING
Orientation Boundary conditions
Different undercut
Current flow direction
Multiple contacts (reliability issue)
Metal
Oxide
SUBSTRATE BIASING
Biasing must be as close as possible to the active devices Any noisy signal affecting the substrate or the well should be sinked by the biasing and not affecting the circuit itself
Metal Contact Poly gate Active area
n-Well n+ Diffusion Well bias p+ Diffusion Substrate bias
p-channel transistor
n-channel transistor
ABSOLUTE & RELATIVE ACCURACIES

Transistors parameters Parameter Symbol threshold mobility (n) mobility (p) oxide cap. length width Vth n p Cox L W Typical value 0.8 V 463 cm2/V sec 167 cm2/V sec 2.16 fF/m2 Absolute accuracy 0.2 V 15 % 15 % 6% 0.3 m 0.3 m Matching accuracy 5 mV (100m dist.) 1 % (100m dist.) 1 % (100m dist.) 0.1 % (100m dist.) 0.04 (20m dist.) 0.04 (20m dist.)
LAYOUT OF RESISTORS
Integrated resistors are made of thin strips of resistive layer a resistive strip is contacted at the two terminals by ohmic contacts (metal p+ or n+) insulation from the surrounding is made by oxide layers or by reversely biased junctions
metal Insulator metal
W L
R = 2 R cont
L L - ----R # = 2 R cont + ---+ ----W x j W-
R# sheet resistance
LAYOUT OF RESISTORS
Metal
n+ diffusion p+ diffusion n-well

n+
n+ p-substrate
Diffusion n+ Well
p+ n-well p-substrate
n+ n-well p -substrate
pinched n-well
n+
p+ n-well p-substrate polysilicon
n+
polysilicon
p-substrate
ACCURACY OF RESISTORS
The sheet resistance is pretty low long strips must be used Serpentine shapes are commonly used Problems of corners (estimated half a square) Undercut (width reduction) Boundary dependent undercut Parameters gradient
2 2 2 2 2 x R L W j ------- = ------ + --------- + ------ + -------- R L W xj
LAYOUT OF ACCURATE RESISTORS

Use of rounded or 45 corners Use of dummy strips to get the same boundaries Large width to limit the random component of the undercut Suitable endings
1 0.5 0
terminals
FACTORS AFFECTING ACCURACY

Stress Variation is anisotropic Minimum at 45 Temperature Temp. gradients affect accuracy Elements symmetrical with respect to the power device
POWER DEVICE
POWER DEVICE
T 1 T2 T3
T 1 T2 T3
INTERDIGITIZED RESISTORS
Absolute accuracy is poor because of the large parameter drift Ratio or matching accuracy is better because it depends on the local variation of parameters Use of interdigitized structures (common centroid) minimizes errors due to gradient in the parameters value
R1 R2
Dummy strip
R1
R2
Dummy strip
RESISTOR FEATURES
Type of layer n+ diff p+ diff n-well p-well pinch. n-well pinch. p-well first poly second poly Sheet Res. /# 20-35 25-60 1K-1.4K 3K-6K 6K-10K 9K-13K 20-28 21-33 Accuracy % 20-40 20-40 15-30 15-30 25-40 25-40 15-30 15-30 Temp. C. ppm/C 1800 1700 6.5K 6.5K 10K 10K 900 800 Volt. C. ppm/V 50-300 50-300 10K 10K 20K 20K 20-200 20-200
SHIELDING
Mixed analog-digital systems are affected by the problem of noisy interference between the analog and the digital sections The most critical source of coupling are the resistances It is important to guarantee possible shielding toward the substrate (or possibly the top side)
n+ diffusion Metal 2 Metal 1 Metal 1 polysilicon p+ p-well Metal Metal Poly-2 resistor shield
n-well p-substrate p+ diffusion
Poly - 1 resistor
n-well n+ diffusion p-substrate
SHIELDING
p+, Substrate bias Resistor ending n+, Well bias Well under the resistor Contact Metal line
RESISTOR GUIDELINES
For matching: use of equal structures not too narrow (W > Wmin) interdigitize thermal effect compensation 45 orientation if stressed For good TC: use of n+ or p+ layers use of poly layers For absolute value: use of diffused layers; suitable endings
INTEGRATED CAPACITORS
Electrodes: Insulator: metal, polysilicon, diffusion silicon oxide, polysilicon oxide, CVD oxide 0 r - WL C = --------t ox A normal capacitance is 1 pF
polysilicon polysilicon 1 polysilicon 2
tox = 16 nm C = 2.16 fF/m2
p+ or n+ diffusion
shielding well (well biasing not visible)
INTEGRATED CAPACITORS
Integrated capacitors are made by structures very close to the silicon substrate parasitic capacitances are not negligible and affect any integrated capacitor
Poly-poly capacitor
TOP PLATE BOTTOM PLATE
Poly-diffusion capacitor
TOP PLATE BOTTOM PLATE
Poly-poly capacitor: Cp,b = 0.01 C Cp,t = 0.001 C Poly-diff capacitor: Cp,b = 0.1 C Cp,t = 0.01 C
Substrate Substrate C Bottom C Substrate p,b Top C p,t Reversely biased junction
INTEGRATED CAPACITORS ACCURACY

C
r -------: r 2 2 2 2 2 2 t C L W r ox - + ---------- + ------ = ------- + --------- = ------ r t ox C L W L W ----- ; --------L W
oxide damage impurities stress temperature bias condition bias history (for CVD)
: etching alignment
t ox ----------: t ox
oxide grow rate poly grain size
UNDERCUT EFFECT
The value of the area is given by the smaller plate or by the thin oxide area (fringing components are neglected) The actual area is less than the designed area because of the undercut effect A = W L WL 2 ( L + W ) x P -x A A 1 -- A the same proportional reduction if the perimeter-area ratio is kept constant
Designed Achieved Undercut x L' L
W' W
W = W 2x L = L 2x
LAYOUT OF CAPACITORS
Capacitors are used as matched elements to dene precise ratios They are often connected to the virtual ground of op-amps careful layout matching good shielding to limit injection of noisy signals
poly 1 metal contact poly 2 poly 1 contact area without poly 1 (thick oxide) poly 2 on thick oxide
CAPACITOR FEATURES
Type poly-diff poly1-poly2 metal-poly metal-diff tox nm 15-20 18-21 600-700 1200-1400 Accuracy % 7-14 6-12 6-12 6-12 6-12 Temp. C. ppm/C 20-50 20-50 50-100 50-100 50-100 Volt. C. ppm/V 60-300 40-200 40-200 60-300 40-200
metal1-metal2 750-1250
CAPACITOR MATCHING
Matched capacitors should have the same perimeter-area ratio Unity capacitors must be used
B:C1 T:C1 B:C2 T:C2=3C1
B:C3
T:C3=4C1
COMMON CENTROID ARRANGEMENT
C1 TC1
C2 TC2
C3 TC3
C4 TC4
C5 TC5
C2 = C1 C3 = 2C1 C4 = 4C1 C5 = 8C1
TC5
TC4
TC1
TC2 TC3
INTRODUCTION
The Role and Place of Modern Mixed AnalogDigital Chips Very Large Scale Integration (VLSI) Technologies Over 1 million transistors From 70s Digital Computer Era had begun Analog Signal Processing reduced but not disappeared The need to interface the computer to the analog world The need for analogenhances digital performance
Layout
THE NEED TO INTERFACE THE COMPUTER TO THE ANALOG WORLD

Computers work in the real word Automobile
Radio, computerized engine control, safety, navigation aids, etc.
Cellular telephony
Transmission and reception of both analog and digital signals
A/D and D/A converters

Layout

PrePost Conversion signal condition
Amplication, ltering for antialiasing or smoothing, sampling, holding, multiplexing etc.
Direct signal processing without A/D conversion

Medium SNR systems, high speed, low power
Interface with sensors

Receiving antennas, transmission lines,
Drive for attuators

Transmitting antennas, transmission lines
Layout

MAD circuits have been realized in metaloxide semiconductor (MOS) technology Precision ratio capacitor arrays Internally compensated MOS operational ampliers High performances A/D converters High performances SwitchedCapacitor lters Continuous time lters PCM encodersdecoders
Layout
THE NEED FOR ANALOG-ENHANCED DIGITAL PERFORMANCE

Analog circuits make possible the high performance of digital systems
Hard disk drive Digital communication links High speed digital circuits are analog in nature Clock recovery circuits PLL Charge pumps
Layout
ADVANTAGE OF MIXING ANALOG AND DIGITAL CIRCUITS ON THE SAME CHIP

The size of the system is reduced The speed of the operation can be increased The power dissipation is decreased The design exibility is increased > high # of channels The reliability is increased The system cost is reduced
Layout
APPLICATIONS OF MAD CHIPS

Telecommunications Consumer electronics Computer and related equipment Multimedia Automotive systems Biomedical instrumentation Robotics
Layout
PROBLEMS IN THE DESIGN OF MAD CIRCUITS

Analog circuits are critical to design Analog voltages are small signals (V) near digital circuits (V) On chip interferences Analog circuits are not amenable to standardization For analog circuits design automation is not possible Testing Mixed circuit designers are not easy to nd
Layout
MECHANISM AND EFFECT OF NOISE COUPLING

VLSI MAD chips consist of several subsystems which must be kept from interfering with each other Sharing of common substrate Sharing of common connections to the external word Parasitic coupling from inductance and resistance of power supply and ground wires Coupling from substrate Coupling from protection diodes Coupling from parasitic cap. of adjacent elements
Layout
MECHANISM AND EFFECT OF NOISE COUPLING

Voltages and currents switching cause noise This noise will increase as:
Magnitude of switching events increase Number of switching events increase Frequency of switching events increase
Differential ECL ECL TTL CMOS

Layout
TECHNIQUES FOR NOISE REDUCTION

Design system solution Shielding Packaging Chip oorplanning Chip wiring
Layout
SYSTEM SOLUTIONS
Even pure CMOS logic design are being limited by crosstalk and inductive switching noise problems Adding any circuitry with less noise margin than CMOS circuits is very difficult
Separate ICs mounted in hybrid packages or MultiChip Module (MCM) Correct timing of signals Comparators and sampling circuits do not compare or sample when large digital driver switch Use fully differential circuits when possible Use of special logic circuits
Layout
LAYOUT SOLUTIONS
Stop thinking of power supply lines and grounds as perfect conductors
Avoid common power supply or ground buses

Use of bypass capacitors inside and outside Pay attention to the resonant frequency Also analog circuits require different power supply VDDDR1, VDDDR2, GNDDR1, GNDDR2, (PAD RING) VDDDC1, VDDDC2, GNDDC1, GNDDC2, (CORE) VDDA1, VDDA2,.. GNDA1, GNDA2,.. VSUB1, VSUB2,..
Layout
LAYOUT SOLUTIONS
Assign bonding pads wisely
The package bonding diagram should be anticipated Use several pads in parallel for power supply and ground
Make power supply lines and ground wide

Lines as wide as 100m Use of less resistive metal layer (Metal2)
Use of star VDD
Layout
SUBSTRATE COUPLING
Consider substrate coupling carefully and guard against it
Layout
SHIELDS
Shield all sensitive circuits, devices and interconnections lines
metal-2 (digital) oxide metal-1 (shield) poly (analog) well (shield)
Use of metal-1 layer as digital inteferences shield Use of well as substrate shield
Layout
LAYOUT SOLUTIONS
Avoid proximities of circuits, devices or interconnection lines that can interfere with each other
analog digital
a)
analog
digital
b)
analog
digital
c)
Layout
LAYOUT OF SC CIRCUITS
In+ In Out In+ In Out In+ In Out
VDD
VDD VB2
Bias Cell
VB1 Op-Amp1 Op-Amp2 Comp VSS

Layout
VSS
Phases Switches Protection Protection Ring Capacitor Array
Bias cell and Op-Amps
Layout
Analog Bus
Digital Bus
Layout
FLOORPLAN SC CIRCUITS
Bus segnali analogici Bus segnali analogici Condensatori Condensatori Interruttori Bus fasi Bus fasi Bus fasi
Operazionale
Bus segnali analogici Bus fasi Bus fasi
Bus fasi
Bus segnali analogici
Bus segnali analogici
Condensatori
Condensatori
Interruttori
Bus fasi
Operazionale
Bus segnali analogici Bus fasi Comparatore Bus fasi Convertitori D/A
Bus fasi
Generatore di fasi Sezione Analogica Sezione Digitale
Interruttori
Interruttori
Layout
MICROCHIP
Layout
BONDING 1
Pin L Pad R1 Id
Digital Section
Ia
R2
Analog Section
Bad performance
dv Current in digital section i = C ----dt di
Voltage across the inductance v = L ---dt Resonance frequency LC can equal the clock frequency Transistor level simulation!!!
Layout
BONDING 2
Pad Digital R1
L1 Pin
Id
Digital Section
R2 C L2 Pad Analog
Ia
Analog Section
Improved connection Addition of bypass capacitor to avoid resonance frequency

Layout
BONDING 3
Pin Digital L1 Pad Digital R1
Id
Digital Section
C L3 L2 R2 Ia
Analog Section
Pin Analog
Pad Analog
Best solution Cost

Layout
FLOORPLAN
Layout
GUARD RINGS
VDDM
To "clean" mixed ground p+ guard ring n-well guard ring p+ guard ring Mixed Circuit being "guarded"
GNDM
VDD GND VDD DIGITAL GND GND VDD

To "clean" DC
n-well guard ring p+ guard ring
Analog Circuit being "guarded"
To "clean" analog ground
VDDA
GNDA
Layout
MAD EXAMPLE 1
Layout
MAD EXAMPLE 2
Layout

Analog Layout

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OUTLINE

IC Technology & Layout

THE CMOS TECHNOLOGY

IC Technology & Layout

TYPICAL CMOS P-WELL PROCESS

Boron 80 keV; 3 x 1012/cm2

p-well diffusion oxidation

IC Technology & Layout

TYPICAL CMOS P-WELL PROCESS

thin oxide growth active area definition

Boron 100 keV

IC Technology & Layout

TYPICAL CMOS P-WELL PROCESS

field oxide growth

Boron 30 keV; 2 x 1011/cm2

additional implant to adjust threshold voltages

definition of polysilicon gates and capacitor bottom plates

IC Technology & Layout

TYPICAL CMOS P-WELL PROCESS

n-channel source & drain implant and diffusion

boron 50 keV; 2 x 1015/cm2

p-channel source & drain implant and diffusion

definition of capacitor top plate

IC Technology & Layout

TYPICAL CMOS P-WELL PROCESS

IC Technology & Layout

DIFFERENCES LAYOUT - CIRCUIT

ETCHING UNDER PROTECTION

BOUNDARY DEPENDENT ETCHING

IC Technology & Layout

LAYOUT OF MOS TRANSISTORS

Active Area Poly

Extreme situation of a layout of a digital transistor

LAYOUT OF MOS TRANSISTORS

Active Area Poly

IC Technology & Layout

Current flow direction

Multiple contacts (reliability issue)

IC Technology & Layout

Metal Contact Poly gate Active area

n-Well n+ Diffusion Well bias p+ Diffusion Substrate bias

IC Technology & Layout

ABSOLUTE & RELATIVE ACCURACIES

L L - ----R # = 2 R cont + ---+ ----W x j W-

IC Technology & Layout

n+ diffusion p+ diffusion n-well

p+ n-well p-substrate polysilicon

IC Technology & Layout

IC Technology & Layout

LAYOUT OF ACCURATE RESISTORS

IC Technology & Layout

FACTORS AFFECTING ACCURACY

IC Technology & Layout

IC Technology & Layout

n-well p-substrate p+ diffusion

n-well n+ diffusion p-substrate

IC Technology & Layout

IC Technology & Layout

tox = 16 nm C = 2.16 fF/m2

shielding well (well biasing not visible)

IC Technology & Layout

INTEGRATED CAPACITORS ACCURACY

oxide grow rate poly grain size

IC Technology & Layout