Wireless Information Transmission System Lab.

Introduction to System IC Design Flow

Hung-Chih Chiang
Institute of Communications Engineering National Sun Yat-sen University

Outline
Wireless Communication IC Examples Fundamentals of SoC System IC Design Flow Application Specific Platform

Example1: Siemens C35i Phone

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. Infineon E-GOLD PMB2851E, GSM Baseband controller and DSP. 32.768kHz crystal NIY Bottom connector FLASH Power supply IC VCO Epcoc B4846; SAW filter, 225.0MHz PCB pads to Battery 13MHz crystal Tx VCO Hitachi PF08112B; Power amplifier External antenna connetor with switch. Diplex filter NIY Epcos B4127 SAW filter 942.5MHz NIY PCB pads to SIM card holder Synthesizer (?) Hitachi HD155124F Bright II; GSM Transceiver Circuit Infineon PMB2906: Analog interface IC (E-GAIM). Interfaces analogue signals (I/Q, voiceband, PA-control, charging control signals) to the digital domain

Example2: Philips DAB Receiver

Years 2000 2005 Communication IC Production Values in Taiwan

2000 2001 2002(e) 2003(f) 2004(f) 2005(f)

50.7 24.3% 53.7 5.9% 67.2 25.1% 101.7 51.4% 141.0 38.6% 155.6 10.4%

17.3 158.0% 32.9 90.6% 42.3 28.5% 64.3 51.9% 98.7 53.4% 118.4 20.0% ADSL/CABLE Modem 19.6 345.5% 13.4 -31.5% 19.0 41.4% 31.1 64.0% 45.1 44.9% 54.1 20.0% 5.8 728.6% 1.2 -78.8% 1.5 19.7% 4.2 184.2% 11.3 171.7% 16.9 50.0% 13.8 1871.4% 15.9 14.7% 21.9 38.1% 41.5 89.5% 67.7 63.0% 77.8 15.0% 66.8 38.9% 54.9 -17.8% 56.9 3.7% 78.9 38.5% 95.8 21.6% 108.2 12.9%

Source: ITIS(2002/09)

System Integration Trend- Cfone

Source: ITIS(2002/10) 6

Outline
Wireless Communication IC Examples Fundamentals of SoC System IC Design Flow Application Specific Platform

Moores Law and Extensions

Gordon Moore (ISSCC2003): - Moores Law will extend another 10-15 years. - But no exponential is forever, so delayed Moores Law (valid in the past 50 years) will be more realistic for the next 10-15 years. 8

Source: Intel

Histories of Key IC Components

Logic 1st Bipolar Transistor 1 Bipolar ECL 1st IC 1st TTL 1st CMOS 1st 4-bit NMOS uP 1 32-bit CMOS uP 1st 32-bit RISC uP 1st 100Mhz CMOS uP 1 64-bit CMOS uP-200Mhz 1st out-of-orde r-execution uP 1st 32-bit 1Ghz uP-0.18u Analog 1st PLL IC 1 MOS voice-encoder 1 switch-capacitor Filter 1st echo-canceller 1st 1-chip Pager 1 GSM Transceiver
st st st st st st

Belllab in 1956 IBM in 1957 Fairchild in 1960 Fairchild in 1962 Fairchild in 1963 Intel in 1974 Belllab in 1981 Standford+Berkeley in 1984 Intel in 1991 DEC in 1992 Intel in 1995 Intel in 2000 Signetics in 1969 Berkeley in 1976 Berkeley in 1977 Belllab in 1983 Philips in 1991 Belllab in 1995

Memory 1st integrated me mory-cell 1 1Kb 3T MOS DRAM 1st 2Kb EPROM 1st 1T DRAM 1st mux-addressed 16Kb DRAM 1st 4Kb pseudo-SRAM 1 16Kb EEPROM 1st 256Kb Flash 1st 256b FRAM
st st st

NEC in 1966 Intel/Honeywell in 1970 Intel in 1971 Siemens in 1972 Mostek in 1977 Intel in 1979 Intel in 1980 Toshiba in 1985 Ramtron in 1988

DSP

1 multi-level 32Mb Flash Intel in 1995 st 1 sampled-data band-pass Filter Belllab in 1960 1st analog shift-register 1st switched-capacitor Filte r 1 DSP 1 floating-point 32-bit DSP 1st Video DSP 1st CMOS read-channel 1 low-power 16-bit DSP
st st st st

Philips in 1972 Berkeley in 1978 Belllab in 1980 Bellab in 1985 NEC in 1987 Hitachi in 1993 Matsushida in 1993

1 1024-QAM cable-mode m DSP Broadcom in 1998 1st 5Ghz OFDM-BB 80Mb/s Imec in 2000

Technology Migration
TSMC Logic Technology Roadmap

Source: TSMC Technology Roadmap (Apr 2004) 10

SoC Concept
- From System on a Board to System on a Chip Analog

Memory

ASIC

CPU

Analog

IP IP

Memory

IP

IP

CPU 11

Soc Advantages
Minimize System Cost Compact System Size Reduce System Power Consumption Increase System Performance
IDM Sales Channel / Service Provider System House (OEM/ODM) Design House (fabless) Siemens IP Provider Photo Mask/Foundry Service Packaging Service Testing Service 12 Motorola Toshiba

SoC Challenges
IP Resource

IP library, IP provider Components with different manufacturer processes (logic, memory, analog, high V, ) EDA Tools that support system verification at all or mixed design phases Independently test components (logic, memory, analog, )

Chip Integration

Chip Design Verification

Chip Testing

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A Current Practical Alternative to SoC: System-in-a-Package (SiP)

SiP concept Analog

Memory

ASIC

CPU

Packaged Chip die

substrate 14

Benefits of SiP SiP benefits:

Reduced developing schedule Reduced developing cost Possible mounting of different technologies Increased yields enabled by smaller chip size

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SiP Examples
Examples of practical SiP

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Outline
Wireless Communication IC Examples Fundamentals of SoC System IC Design Flow* Application Specific Platform

*Ref:

Reuse Methodology Manual For SYSTEM-ON-A-CHIP Designs THIRD EDITION By Michael Keating & Pierre Bricaud KLUWER ACADEMIC PUBLISHERS 17

Typical System IC Architecture

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Traditional Sequential ASIC Design Flow

Specification System Models RTL Design Functional Verification Logical Synthesis Timing Verification P&R Physical Verification Prototype Build & Test 19

Architecture Design

RTL Design

Logic synthesis Physical Design Prototype

Parallel System IC Design Flow

System Design and Verification Physical Physical Specification: area, power, clock tree design Preliminary floorplan Updated floorplans Updated floorplans Trial placement Timing Timing Specification: IO timing, clock frequency Block timing specification Block synthesis & placement Top-level synthesis Hardware Hardware Specification Algorithm develop. & macro decomp. Block selection / design Block verification Top-level HDL Top-level verification Software Software Specification Application prototype development AP prototype testing Application development Application testing Application testing

Time

Placement and Route -> Tapeout 20

Specifications
Specification Requirements:

Hardware

Functionality External interfaces to other hardware Software interface (register definitions) Timing Performance Area and power constraints

Software

Functionality Timing Performance Hardware Interface Software structure, kernel

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Specification
Two Useful Specification Techniques:
Formal specifications: The desired characteristics of a design are defined independently of any implementation. Once a formal specification is generated, format methods such as property checking can be used to prove that a specific implementation meets the specification. Executable specifications: An executable specification is typically an abstract model for the hardware/software been specified written in in C, C++, SystemC, HVL, Verilog, or VHDL.

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Top-Level System Design Processes

CREATE system specification DEVELOP system model SPECIFY & DEVELOP HW architecture model DETERMINE HW/SW partition REFINE & TEST architecture model (HW/SW co-simulation) SPECIFY HW blocks Block1 spec. Block2 spec. 23 SPECIFY SW DEVELOP Prototype SW

Outline
Wireless Communication IC Examples Fundamentals of SoC System IC Design Flow Application Specific Platform

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Application Specific Platform

IP re-use is essential for all SoC designs. The specification of an ASIC (Application-Specific Integrated Circuit) chip often includes application adaptability due to the following factors:

Significant market shift, Rapid evolved standards, Product differentiation, Hardware reuse.

Its probably not a good idea to develop an all-purpose platform for IP integration, since different applications requires different CPU/DSP powers, memories, IOs, etc.

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Application Specific Platform

A generic platform contains the following components:

Bus system (AMBA, PalmBus, ) CPU/MCU, DSP SRAM, DRAM, non-volatile memory, Basic I/O functions (UART, SPI, USB, PCI, )

An application specific platform contains:

Specification of application A generic platform + pre-integrated IP for the specified application.

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Platform Design Objectives

Application Space Platform Design Objectives: Design the platform to support multiple applications

Application Space Exploration System Platform

Platform Specification

Architecture Space 27

Platform Selection
Application Space Application Specification Platform Selection: For a given application. select the best platform in terms of performance, cost, etc. System Platform Platform Space Exploration

Architecture Space 28

Platform Example1:
ARM PrimeXsys Platform

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Platform Example2:
MIPS SOC-it

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Platform Example3:
PowerPC CoreConnect Platform

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Application Specific Platform Example1:

ARM PrimeXsys Wireless Platform

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Application Specific Platform Example2:

AWM Wireless Multimedia Platform

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Application Specific Platform Example3:

Xpert-GPS 3000 Platform

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Application Specific Platform Example4:

Palm Pak SoC Platform

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System-on-a-Programmable-Chip (SoPC)
SoPC - FPGA with the following features

Embedded processor core On-chip peripherals and memory Millions of gates in FPGA logic cells System level tools provided

SoPC advantages over SoC

Reconfigurable Fast prototyping Save NRE charges

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SoPC Solution
Xilinx Virtex-II Pro

Virtex-II Pro FPGA PowerPC 405, CoreConnect bus Micro Blaze controller (32-bit RISC) Peripheral and memory blocks EDK/ISE

Altera- Excalibur

APEX 20KE FPGA ARM 922T, AMBA bus NIOS controller (16/32-bit RISC) Peripheral and memory blocks SoPC Builder/Quartus II

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Summaries
IC design trend is moving toward SoC. Parallel design flow significantly reduces system IC developing schedule wrt. Traditional design flow. Selecting a proper application-specific platform is important for current and future project development.

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