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Space Vector Pulsewidth Amplitude Modulation for a BuckBoost Voltage/Current Source Inverter
Qin Lei, Student Member, IEEE, and Fang Zheng Peng, Fellow, IEEE
AbstractThis paper proposes a space vector pulsewidth amplitude modulation (SVPWAM) method for a buckboost voltage/current source inverter. For a voltage source inverter, the switching loss is reduced by 87%, compared to a conventional sinusoidal pulsewidth modulation (SPWM) method. For a current source inverter, the switching loss is reduced by 60%. In both cases, the power density is increased by a factor of 2 to 3. In addition, it is also veried that the output harmonic distortions of SVPWAM is lower than SPWM, by only using one-third switching frequency of the latter one. A 1-kW boost-converter-inverter prototype has been built and tested using this modulation method. The maximum overall system efciency of 96.7% has been attained at full power rating. The whole system power density reaches 2.3 kW/L and 0.5 kW/lb. The numbers are remarkable at this power rating. As a result, it is feasible to use SVPWAM to make the buckboost inverter suitable for applications that require high efciency, high power density, high temperature, and low cost. Such applications include electric vehicle motor drive or engine starter/alternator. Index TermsBuck-boost, SVPWAM, switching loss reduction, THD.

Fig. 1.

Typical conguration of a series PHEV.

I. INTRODUCTION

URRENTLY, two existing inverter topologies are used for hybrid electric vehicles (HEVs) and electric vehicles (EVs): the conventional three-phase inverter with a high voltage battery and a three-phase pulsewidth modulation (PWM) inverter with a dc/dc boost front end. The conventional PWM inverter imposes high stress on switching devices and motor thus limits the motors constant power speed range (CPSR), which can be alleviated through the dcdc boosted PWM inverter. Fig. 1 shows a typical conguration of the series plug-in electric vehicle (PHEV). The inverter is required to inject low harmonic current to the motor, in order to reduce the winding loss and core loss. For this purpose, the switching frequency of the inverter is designed within a high range from 15 to 20 kHz, resulting in the switching loss increase in switching device and also the core loss increase in the motor stator. To solve this problem, various soft-switching methods have been proposed [1][3]. Active switching rectier or a diode rectier with small

Manuscript received April 18, 2012; revised June 21, 2012 and August 23, 2012; accepted October 2, 2012. Date of current version July 18, 2013. Recommended for publication by Associate Editor J.-I. Itoh. Q. Lei is with the Department of Electrical Engineering, Michigan State University, Lansing, MI 48824 USA (e-mail: leiqin@msu.edu). F. Z. Peng is with the Department of Electrical and Computer Engineering, Michigan State University, Lansing, MI 48824 USA (e-mail: fzpeng@msu.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2225847

DC link capacitor have been proposed in [4], [5], [8][12]. Varies types of modulation method have been proposed previously such as optimized pulse-width-modulation [13], improved Space-Vector-PWM control for different optimization targets and applications [14][16], and discontinuous PWM (DPWM) [17]. Different switching sequence arrangement can also affect the harmonics, power loss and voltage/current ripples [18]. DPWM has been widely used to reduce the switching frequency, by selecting only one zero vector in one sector. It results in 50% switching frequency reduction. However, if an equal output THD is required, DPWM can not reduce switching loss than SPWM. Moreover, it will worsen the device heat transfer because the temperature variation. A double 120 attop modulation method has been proposed in [6] and [7] to reduce the period of PWM switching to only 1/3 of the whole fundamental period. However, these papers didnt compare the spectrum of this method with others, which is not fair. In addition, the method is only specied to a xed topology, which can not be applied widely. This paper proposes a novel generalized space vector pulsewidth amplitude modulation (SVPWAM) method for the buck/boost voltage source inverter (VSI) and current source inverter (CSI). By eliminating the conventional zero vector in the space vector modulation, two-third and one-third switching frequency reduction can be achieved in VSI and CSI, respectively. If a unity power factor is assumed, an 87% switching loss reduction can be implemented in VSI, and a 74% reduction can be implemented in CSI. A 1-kW boost-converter inverter system has been developed and tested based on the SVPWAM method. A 90% power loss reduction compared to SPWM has been observed. The two stage efciency reaches 96.7% at the full power rating. The power volume density of the prototype is 2.3 kW/L. The total weight of the system is 1.51 lb. Therefore, a

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Fig. 4.

Vector placement in each sector for VSI.

Fig. 2.

SVPWAM for VSI.

Fig. 5. Theoretic waveforms of dc-link voltage, output line-to-line voltage and switching signals.

Fig. 3.

DC-link voltage of SVPWAM in VSI.

high-efciency, high-power density, high-temperature, and lowcost 1-kW inverter is achieved by using an SVPWAM method. II. SVPWAM FOR VSI A. Principle of SVPWAM Control in VSI The principle of an SVPWAM control is to eliminate the zero vector in each sector. The modulation principle of SVPWAM is shown in Fig. 2. In each sector, only one phase leg is doing PWM switching; thus, the switching frequency is reduced by two-third. This imposes zero switching for one phase leg in the adjacent two sectors. For example, in sector VI and I, phase leg A has no switching at all. The dc-link voltage thus is directly generated from the output line-to-line voltage. In sector I, no zero vector is selected. Therefore, S1 and S2 keep constant ON, and S3 and S6 are doing PWM switching. As a result, if the output voltage is kept at the normal three-phase sinusoidal voltage, the dc-link voltage should be equal to line-to-line voltage Vac at this time. Consequently, the dc-link voltage should present a 6 varied feature to maintain a desired output voltage. The corresponding waveform is shown in solid line in Fig. 3. A dcdc conversion is needed in the front stage to generate this 6 voltage. The topologies to implement this method will be discussed later. The original equations for time period T1 and T2 are 3 3 T1 = m sin ; T2 = m sin() (1) 2 3 2

where [0, /3] is relative angle from the output voltage vector to the rst adjacent basic voltage vector like in Fig. 2. If the time period for each vector maintains the same, the switching frequency will vary with angle, which results in a variable inductor current ripple and mutifrequency output harmonics. Therefore, in order to keep the switching period constant but still keep the same pulsewidth as the original one, the new time periods can be calculated as (2) T1 /Ts = T1 /(T1 + T2 ) The vector placement within one switching cycle in each sector is shown in Fig. 4. Fig. 5 shows the output line-to-line voltage and the switching signals of S1 . B. Inverter Switching Loss Reduction for VSI For unity power factor case, the inverter switching loss is reduced by 86% because the voltage phase for PWM switching is within [60 , 60 ], at which the current is in the zero-crossing region. In VSI, the device voltage stress is equal to dc-link voltage VDC , and the current stress is equal to output current ia . Thus the switching loss for each switch is PSW
I

1 2 +

/6 / 6 7 /6

ESR

|Im sin(t)| VDC fsw dt Vref Iref

ESR
5 /6

2 3 Im VDC = ESR fsw , Vref Iref where ESR , Vref , Iref are the references.

|Im sin(t)| VDC fsw dt Vref Iref (3)

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Fig. 6.

(SVPWAM power loss/SPWM power loss) versus power factor in VSI.

Fig. 8.

Switching voltage and current when pf = 1.

Fig. 9.

Vector placement for each sector for CSI.

Fig. 7.

Conventional CSI and its corresponding SVPWAM diagram.

Since the SVPWAM only has PWM switching in two 60 sections, the integration over 2 can be narrowed down into integration within two 60 PSW I = (2 3)/ (Im VDC /(Vref Iref )) ESR fsw . (4) The switching loss for a conventional SPWM method is PSW
I

= (2/ ) (Im VDC /(Vref Iref )) ESR fsw .

(5)

In result, the switching loss of SVPWAM over SPWM is f = 13.4%. However, when the power factor decreases, the switching loss reduction amount decreases because the switching current increases as Fig. 6 shows. As indicated, the worst case happens when power factor is equal to zero, where the switching loss reduction still reaches 50%. In conclusion, SVPWAM can bring the switching loss down by 5087%. III. SVPWAM FOR CSI A. Principle of SVPWAM in CSI The principle of SVPWAM in CSI is also to eliminate the zero vectors. As shown in Fig. 7, for each sector, only two switches are doing PWM switching, since only one switch in upper phase legs and one switch in lower phase legs are conducting together at any moment. Thus, for each switch, it only needs to do PWM

switching in two sectors, which is one-third of the switching period. Compared to SVPWM with single zero vector selected in each sector, this method brings down the switching frequency by one-third. Similarly, the dc-link current in this case is a 6 varied current. It is the maximum envelope of six output currents: Ia , Ib , Ic , Ia , Ib , Ic , as shown in Fig. 8. For example, in sector I, S1 always keeps ON, so the dc-link current is equal to Ia . The difference between dc-link current in CSI and dc-link voltage in VSI is dc-link current in CSI is overlapped with the phase current, but dc-link voltage in VSI is overlapped with the line voltage, not the phase voltage. The time intervals for two adjacent vectors can be calculated in the same way as (1) and (2). According to diagram in Fig. 7, the vector placement in each switching cycle for six switches can be plotted in Fig. 9. The SVPWAM is implemented on conventional CSI through simulation. Fig. 10 shows the ideal waveforms of the dc current Idc , the output phase ac current and the switching signals of S1 . The switching signal has two sections of PWM in positive cycle, but no PWM in negative cycle at all. B. Inverter Switching Loss Reduction for CSI In CSI, the current stress on the switch is equal to the dclink current, and the voltage stress is equal to output line-to-line voltage, as shown the shadow area in Fig. 8 Thus, the switching loss for a single switch is determined by 2 3 idc Vl lp eak ESR fsw . (6) PSW CSI = Vref Iref

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Fig. 10. Theoretic waveforms of dc-link current, output line current and switching signals.

Fig. 12.

Spectrum of SPWM at switching frequency.

Fig. 11. CSI switching loss ratio between SVPWAM and discontinuouse SVPWM versus power factor.

Fig. 13.

Spectrum of discontinuous SVPWM at switching frequency.

When compared to discontinuous SVPWM, if the half switching frequency is utilized, then the switching loss of it becomes half of the result in (6). The corresponding switching loss ratio between SVPWAM and discontinuous SVPWM is shown in Fig. 11. IV. SPECTRUM ANALYSIS OF SVPWAM A fair comparison in switching loss should be based on an equal output harmonics level. Thus, the switching loss may not be reduced if the switching frequency needs to be increased in order to compensate the harmonics. For example, discontinuous SVPWM has to have double switching frequency to achieve the same THD as continuous PWM. So the switching loss reduction is much smaller than 50%. Therefore, for the newly proposed SVPWAM, a spectrum analysis is conducted to be compared with other methods on the basis of an equal average switching frequency, which has not been considered in paper [16]. A. Spectrum Comparison Between SVPWAM, SPWM, and SVPWM The object of spectrum analysis is the output voltage or current before the lter. The reason is that certain orders of harmonics can be eliminated by sum of switching functions in VSI or subtraction of switching functions in CSI. The comparison is between SVPWAM, DPWM, and continuous SVPWM in VSI/CSI. The switching frequency selected for each method is different, because the comparison is built on an equalized

average switching frequency over a whole fundamental cycle, in order to make the harmonics comparable at both low modulation and high modulation range. Assume that the base frequency is f0 = 10.8 kHz. Thus, 3f0 should be selected for SVPWAM, and f0 should be selected for continuous SVPWM in VSI. In CSI, 3f0 , 2f0 , and f0 should be selected for SVPWAM, discontinuous SVPWM, and continuous SVPWM, respectively. The modulation index selected here is the maximum modulation index 1.15, since the SVPWAM always only has the maximum modulation index. Theoretically, the THD varies with modulation index. The dc-link voltage is designed to be a constant for SVPWM and an ideal 6 envelope of the output six line-to-line voltages for SVPWAM. Thus, the harmonic of the SVPWAM here does not contain the harmonics from the dcdc converter output. It is direct comparison between two modulation methods from mathematics point of view. Figs. 1214 show the calculated spectrum magnitude at rst side band of switching frequency range for three methods. It can be concluded that the ideal switching function of SVPWAM has less or comparable harmonics with SPWM and DPWM. B. Analytical Double Fourier Expression for SVPWAM The expression of double Fourier coefcient is Am n + jBm n = 1 2 2
6 y e (i) y s (i) x f (i) x r (i)

Idc ej ( m x + n y ) dxdy (7)

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Fig. 14.

Spectrum of SVPWAM at switching frequency. TABLE I INTEGRATION LIMIT FOR LINE-TO-LINE VOLTAGE V a b (t)

i ys(i) ye(i) xr(i) xr1 = 0; 3 sin( / 3 y ) 1 0 xr 2 =2 sin( / 3 + y ) 2 3 4

xf(i)
sin( / 3 y ) xf1 = ; sin( / 3 + y ) x f 2 =2

Idc
Fig. 15. SVPWAM-based boost-converter-inverter motor drive system.

3
2 3

2 3

xr =

sin(2 / 3 y ) sin y

xr = 2 -

sin(2 / 3 y ) sin y

-1 -1 -1

0
xf1 = x f 2 =2

2
sin(4 / 3 y ) ; sin( y -2 / 3)

x = 0; 4 r1 sin(4 / 3 y ) 3 xr 2 =2 sin( y -2 / 3)

example. Instead of controlling the dc-link current Ipn to have a constant average value, the open zero state duty cycle Dop will be regulated instantaneously to control Ipm to have a 6 uctuate average value, resulting in a pulse type 6 waveform at the real dc-link current Ipn , since I1 is related to the input dc current Iin by a transfer function I1 = 1 Dop Iin 1 2Dop (9)

4 5 3

5 3

sin(5 / 3 y ) xr1 = sin( y - )

sin(5 / 3 y ) x f 1 = 2 sin( y - )

1 1

5 3

VI. CASE STUDY: 1-KW BOOST-CONVERTER INVERTER FOR EV MOTOR DRIVE APPLICATION A. Basic Control Principle The circuit schematic and control system for a 1-kW boostconverter inverter motor drive system is shown in Fig. 15. A 6 dc-link voltage is generated from a constant dc voltage by a boost converter, using open-loop control. Inverter then could be modulated by a SVPWAM method. The specications for the system are input voltage is 100200 V; the average dc-link voltage is 300 V; output line-to-line voltage rms is 230 V; and frequency is from 60 Hz to 1 kHz. B. Voltage Constraint and Operation Region It is worth noting that the SVPWAM technique can only be applied when the batteries voltage falls into the region V Vin 3 l l due to the step-up nature of boost converter. 2 The constraint is determined by the minimum point of the 6 dc-link voltage. Beyond this region, conventional SPWM can be implemented. However, the dc-link voltage in this case still varies with 6 because of the small lm capacitor we selected. Thus, a modied SPWM with varying dc-link voltage will be adopted during the motor start up as shown in Fig. 16. Hence, the system will achieve optimum efciency when the motor is operating a little below or around nominal voltage. When the motor demands a low voltage during start up, efciency is the same as the conventional SPWM-controlled inverter.

where y [0, 2 ] represents the fundamental cycle; x [0, 2 ] represents one switching cycle. The double Fourier expression coefcients can be derived as long as the rising edge of each PWM waveform is known. The output line-to-line voltage Vab is used as an illustrative example. It is a function of switching function Vab (t) = Vdc (S1 (t) S3 (t)). (8)

So its double Fourier equation is equal to the subtraction of two double fourier equations for switching functions. The integration limits for Vab (t) is shown in Tables I. The coefcients nally could be simplied into a closed-form expression in terms of Bessel functions, which will not be discussed here. V. TOPOLOGIES FOR SVPWAM Basically, the topologies that can utilize SVPWAM have two stages: dcdc conversion which converts a dc voltage or current into a 6 varied dc-link voltage or current; VSI or CSI for which SVPWAM is applied. One typical example of this structure is the boost converter inverter discussed previously. However, the same function can also be implemented in a single stage, such as Z/quasi-Z/trans-Z source inverter [37][40]. The front stage can also be integrated with inverter to form a single stage. Take current-fed quasi-Z-source inverter as an

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Fig. 16.

Operation region of boost-converter-inverter EV traction drive.

Fig. 18.

Hardware picture of the 1-kW SVPWAM boost converter inverter.

Fig. 17.

Variable carrier SPWM control in buck mode.

In SVPWAM control of boost mode, dc-link voltage varies with the output voltage, in which the modulation index is always kept maximum. So, when dc-link voltage is above the battery voltage, dc-link voltage level varies with the output voltage. The voltage utilization increased and the total power stress on the devices has been reduced. C. Variable DC-Link SPWM Control at High Frequency When the output needs to operate at a relative high frequency, like between 120 Hz and 1 kHz, it is challenging to obtain a 6 dc-link voltage without increasing the switching frequency of a boost converter. Because the controller does not have enough bandwidth. Furthermore, increasing boost converter switching frequency would cause a substantial increase of the total switching loss, because it takes up more than 75% of the total switching loss. The reason is because it switches at a complete current region. Also a normal SPWM can not be used in this range because the capacitor is designed to be small that it can not hold a constant dc link voltage. Therefore, the optimum option is to control the dc link voltage to be 6 and do a variable dc link SPWM modulation, as explained in Fig. 17. In this variable dc-link SPWM control, in order to get better utilization of the dc-link voltage, an integer times between the dc-link fundamental frequency and output frequency is preferred. When the output frequency is in [60 Hz, 120 Hz], a 6 dc link is chosen; when the frequency is in [120 Hz, 240 Hz], a 3 dc link is chosen; when the frequency is in [240 Hz, 360 Hz], a 2 dc link is chosen. D. Experiment Results 1) Experiment Setup: A 1-kW boost-converter inverter prototype has been built in the laboratory to implement the SVPWAM control at 60 Hz and SPWM control at 1 kHz, in
Fig. 19. Output voltage and input current at V in = 20 V, V d c V lrm s = 46 V, P o = 40 W, fo = 60 Hz, fsw = 20 kHz.
av g

= 60 V,

order to demonstrate their merits in reducing power loss and reducing the size compared to traditional methods. The picture of the hardware is shown in Fig. 18. It includes a DSP board, a gate drive board, a boost converter, a three-phase inverter, heat sink, and a fan cooling system. The dimension is 11 cm 8 cm 5 cm, and the total weight is 1.5 lb. The parameters used in the test are rated power: 1 kW; battery voltage: 100200 V; rated line voltage rms: 230 V; dc-link voltage peak: 324 V; switching frequency: 20 kHz; output frequency: 60 Hz1 kHz 2) SVPWAM Control at 60 Hz: Figs. 1920 show the output and input voltage, current waveform when input voltage increases from 20 to 100 V, while keeping the boost ratio constant. In this case, the output voltage increases linearly with input voltage increase. The output power increases in proportion to square of the input voltage. Fig. 21 shows the efciency test results by YOKOGAWA WT1600 series power meter when the input voltage increases from 100 to 200 V, while keeping the output power constant at 1 kW. The output line-to-line voltage rms keeps at 230 V, and the dc-link voltage is a 6 varied waveform with 325 V peak value. In the data record on the power meter, Um n6 , Um n4 , and Um n1 represent the phase line voltages; Irm s6 , Irm s4 , and Irm s1 represent ten times of phase currents, because ten circles of wires have been wound on the current transducer core of

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Fig. 20. Output voltage and input current at V in = 100 V, V d c V lrm s = 230 V, P o = 1 kW, fo = 60 Hz, fsw = 20 kHz.

av g

= 300 V,

Fig. 22. Results of efciency test at constant torque region by YOKOGAWA WT1600 series power meter. Waveforms from the top to bottom: output lineto-line voltage before LC lter, output current. The input voltage keeps at 200 V constant; the dc-link voltage keeps at 300 V 6 voltage; the output voltage changes from 54 to 162 V, thus the power also changes from 280 to 850 W proportionally. When power is equal to 1 kW, the voltage reaches at nominal value 230 V. (a) V in = 200 V, V d c av g = 300 V, V lrm s = 162 V, P o = 850 W, fo = 60 Hz. (b) V in = 200 V, V d c av g = 300 V, V lrm s = 54 V, P o = 280 W, fo = 60 Hz.

Fig. 21. Results of efciency test at constant full power rating 1 kW but different input voltage by YOKOGAWA WT1600 series power meter. Waveforms from the top to bottom: output line-to-line voltage before LC lter, output current, input voltage, input current. The numbers displayed on the screen represent: U m n 6 , U m n 1 , U m n 4 : RMS value of output line-to-line voltage before LC lter, like the rst waveform shows; Irm s6 , Irm s1 , Irm s4 : ten times of output line current; U d c 2 : input voltage; Id c 2 : 10 times of input current; F1: output power; F2: input power; F3: efciency calculated from F1/F2; F4: total power loss: (a) V in = 150 V, V d c av g = 300 V, V lrm s = 230 V, P o = 1 kW, fo = 60 Hz, fsw = 20 kHz; (b) V in = 200 V, V d c av g = 300 V, V lrm s = 230 V, P o = 1 kW, fo = 60 Hz, fsw = 20 kHz.

the power meter. Udc2 is input dc voltage and Idc2 is ten times of average input dc current. F1 and F2 are the measured output and input power, respectively. F3 is the efciency that is calculated using F1/F2. F4 is the overall power loss. Fig. 22 shows the efciency test results when the power increases in proportional to output voltage below the maximum power while keeping the input voltage and dc-link voltage constant, which is corresponding to the constant torque region in Fig. 16. The input voltage keeps at 300 V 6 voltage; the output voltage changes from 54 to 162 V; thus, the power also changes from 280 to 850 W proportionally. When power is equal to 1 kW, the voltage reaches at nominal value 230 V; this waveform is shown in Fig. 21(b). 3) Output Three-Phase Voltage at 1 kHz: When the output frequency increases to 1 kHz, the measured voltage and current waveforms and efciency are shown in Fig. 23 at input voltage

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Fig. 25.

Efciency versus voltage gain results corresponding to Fig. 19.

Fig. 23. The efciency test at V in = 150 V at fo = 1 kHz: from top to bottom: output line voltage, output current, and input current.

Fig. 24. Measured overall efciency when input voltage changes from 100 to 200 V at 1-kW power rating corresponding to Fig. 23 (fo = 60 Hz, fsw = 20 kHz, V d c p e a k = 325 V, V ol -lrm s = 230 V).

150 V. The efciency is around 84% for both cases, lower than 60 Hz case. E. Overall Efciency and Power Loss Comparison Between SVPWAM and SPWM Fig. 24 shows the measured efciency when the input voltage increases from 100 to 200 V, all at 1-kW power rating. The overall efciency increases as the input voltage increases, because the efciency of a boost converter increases when the input voltage increases. The maximum efciency at 1 kW reaches 96.7% at input voltage 200 V. Fig. 25 shows the joined results of the constant torque region and constant power region in Fig. 16. It can be seen that the maximum efciency at constant torque region happens at its maximum output voltage where the voltage gain is equal to 1, and the maximum efciency at constant power region power happens at its minimum voltage gain point, which is also equal to 1. At constant power region, the efciency decreases as the voltage increases while keeping the power constant. Fig. 26(a) and (b) shows the power loss estimation (from the loss model mentioned before) of the inverter when the power
Fig. 26. Comparison between inverter power losses in the condition that dclink voltage changes from 0 to full rating at 300 V: (a) SVPWAM, (b) SPWM.

increases from 0 to full rating under two methods. Since the research target is only inverter, the test condition is based on varying the output power by changing output voltage from 0 to 230 V. It is observed that in the SVPWAM method, conduction loss accounts for 80% of the total power loss, but in the SPWM method, switching loss is higher than conduction loss. The switching loss is reduced from 10 to 1.4 W from SPWM to SVPWAM. An estimated 87% switching loss reduction has been achieved. VII. CONCLUSION The SVPWAM control method preserves the following advantages compared to traditional SPWM and SVPWM method. 1) The switching power loss is reduced by 90% compared with the conventional SPWM inverter system.

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2) The power density is increased by a factor of 2 because of reduced dc capacitor (from 40 to 6 F) and small heat sink is needed. 3) The cost is reduced by 30% because of reduced passives, heat sink, and semiconductor stress. A high-efciency, high-power density, high-temperature, and low-cost 1-kW inverter engine drive system has been developed and tested. The effectiveness of the proposed method in reduction of power losses has been validated by the experimental results that were obtained from the laboratory scale prototype. REFERENCES
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Qin Lei (S09) received the B. S. degree in electrical engineering from Huazhong University of Science and Technology, Wuhan, China, in 2006, and the Ph.D degree in electrical engineering from Michigan State University, Ann Arbor, MI, USA, in Sep. 2012. After graduation, she joined General Electric Global Research Center, Niskayuna, where she is an Electric Engineer now. Her research interests include high power converter control, HEV/EV motor drive, microgrid, and Z-source inverter.

Fang Zheng Peng (M92-SM96-F04) received the B.S. degree in electrical engineering from Wuhan University, China, in 1983, and the M.S. and Ph.D. degrees, both in electrical engineering, from Nagaoka University of Technology, Japan, in 1987 and 1990, respectively. From 1990 to 1992, he was a Research Scientist with Toyo Electric Manufacturing Co., Ltd., where he was engaged in research and development of active power lters, utility applications, and motor drives. From 1992 to 1994, he worked with Tokyo Institute of Technology as a Research Assistant Professor, where he initiated a multilevel inverter program and a speed-sensorless vector control project. From 1994 to 2000, he worked for Oak Ridge National Laboratory (ORNL), rst as a Research Assistant Professor at the University of Tennessee, Knoxville from 1994 to 1997 and was then a Staff Member, Lead (principal) Scientist of the Power Electronics and Electric Machinery Research Center at ORNL from 1997 to 2000. In 2000, he joined Michigan State University as an Associate Professor and he is now a Full Professor of the Department of Electrical and Computer Engineering. He holds over 10 patents and two of them have been used extensively in industry. Dr. Peng received many awards including the 1991 First Prize Paper Award in IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS and the 1990 Best Paper Award in the Transactions of the IEE of Japan, the Promotion Award of Electrical Academy. He has served the IEEE Power Electronics Society in many including as Awards Chair, Chair of Technical Committee, an Associate Editor for the Transactions, Region 1-6 Liaison and AdCom Member-at-Large. He was an IEEE/IAS Distinguished Lecturer for the 20102011 term.