IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

3, MARCH 2014

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A Z-Source Half-Bridge Converter

Guidong Zhang, Zhong Li, Bo Zhang, Member, IEEE, Dongyuan Qiu, Member, IEEE, Wenxun Xiao, and Wolfgang A. Halang

AbstractApplying an LC network into a half-bridge converter, a novel Z-source half-bridge converter is presented, in which less LC components are needed compared to the conventional one. This Z-source half-bridge converter can solve not only the problems of the shoot-through and limited voltage but also the problem of imbalance at the midpoint voltage of input capacitors. Furthermore, it can generate a broader range of output voltage values and much more kinds of waveforms, such as the varied positive or negative output voltages and the varied time ratio between positive and negative voltages, which are particularly desirable for some special power supplies, like the electrochemical power supply. Finally, the proposed converter is implemented in a prototype, and the experimental results can verify the effectiveness of the proposed converter. Index TermsHalf-bridge shoot-through, Z-source. converter, reduced number,

Fig. 1. Conventional half-bridge converter.

I. I NTRODUCTION

ONVENTIONAL half-bridge converters have their switches in series, as shown in Fig. 1, with which the shoot-through can occur [1], which means that the strong current owing through the switches makes them break down. Moreover, the ac output voltage is limited below the dc voltage, which is named the limited voltage problem, because, in practice, ac output voltage is sometimes desirable to be higher than the dc voltage. Furthermore, an unbalanced midpoint of input capacitors in conventional half-bridge converters leads to large ripples [2], [3], making the system unstable. To solve the unbalanced midpoint problem, Eloy-Garcia et al. proposed an extended direct power control algorithm to balance the midpoint voltage in multilevel neutral-pointclamped (NPC) inverters [4], [5]. Although the method is designed for three-phase inverters and multilevel NPC, it is also applicable to a single-phase half-bridge converter. Additionally,

Manuscript received August 20, 2012; revised November 21, 2012 and February 3, 2013; accepted March 20, 2013. Date of publication April 5, 2013; date of current version August 23, 2013. This work was supported in part by the Key Program of the National Natural Science Foundation of China under Grant 50937001. G. Zhang is with the School of Electric Power, South China University of Technology, Guangzhou 510640, China, and also with the Faculty of Mathematics and Computer Science, FernUniversitt in Hagen, 58084 Hagen, Germany (e-mail: zgdscut@gmail.com). Z. Li was with the Faculty of Mathematics and Computer Science, FernUniversitt in Hagen, 58084 Hagen, Germany. He is now with the Faculty of Engineering, University of DuisburgEssen, 47057 Duisburg, Germany (e-mail: zhong.li@fernuni-hagen.de). B. Zhang, D. Qiu, and W. Xiao are with the School of Electric Power, South China University of Technology, Guangzhou 510640, China (e-mail: epbzhang@scut.edu.cn; epdyqiu@scut.edu.cn; epxwx@yahoo.com.cn). W. A. Halang is with the Faculty of Mathematics and Computer Science, FernUniversitt in Hagen, 58084 Hagen, Germany (e-mail: Wolfgang.Halang@ fernuni-hagen.de). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIE.2013.2257146

Win et al. and Tanaka et al. proposed a half-bridge-converterbased active power quality compensator with a dc voltage balancer to balance voltages of two dc capacitors [6], [7]. To solve the limited voltage problem, adding a boost circuit instead of the source or adding a step-up transformer in parallel with the output part has been proposed [8], where the output voltage is xed due to the xed turn ratio of the transformer. In order to solve the shoot-through problem, a shoot-through protection scheme has been proposed [9], but it is only applicable to specially designed switches. In addition, a novel control strategy based on a digital signal processor [10] has also been proposed, which is like traditional methods focusing on control design instead of redesigning the main circuit. Redesigning the main circuit not only can reduce the complexity and cost but also can enhance the stability of the system. To solve the limited voltage problem and the shoot-through problem better, Peng has rst used an LC network, which is named a Z-network as shown in Fig. 2, to couple with the dc source in the converters and, thus, proposed a novel source, which is different from the voltage source and the current source and is named as a Z-source (see Fig. 2) [11]. Since then, the Z-source technology has greatly advanced. For example, Peng et al. have proposed some novel Z-source circuits [12], [13] and corresponding control methods [14], [15]. Following Pengs work, new Z-source circuits and control methods have also been proposed, such as the algorithms for controlling both the dc boost and ac output voltage of Z-source inverters [16] and dual-inputdual-output Z-source inverters [17]; moreover, the Z-source technology has been applied in practice, for instance, in fuel cell systems [18], motor drives [19], distributed power generations [20], photovoltaic systems [21], and battery hybrid electric vehicles [22]. The Z-source converter can work in the shoot-through mode, and its output voltage can reach a broader range than that of the conventional ones. However, the range of the output voltage is not broad enough for some special applications, like electrochemical power supply [23], which requires a much broader range of output voltage [24] and abundant waveforms in various shapes [25], [26].

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Fig. 2. Z-source half-bridge converter with two Z-networks.

Applying Pengs Z-source concept into half-bridge converters [11] results in a Z-source half-bridge converter, in which an LC Z-network should be parallelized to the power source. It is known that two input capacitors in the half-bridge converter play the role of two dc sources; therefore, two LC Z-networks are needed to couple with the capacitors, as shown in Fig. 2 [27], [28]. Although the characteristics of the Z-source may be obtained, many additional devices, such as LC elements, are used in the circuit, which increase the cost, size, and weight of the converter. Here, a novel Z-source half-bridge converter is proposed, in which, instead of putting two LC Z-networks to couple with the capacitors, only one LC Z-network is required to be placed between the input capacitors and the switches. This proposed Z-source half-bridge converter not only can solve the limited voltage and the shoot-through problems but also can solve the unbalanced midpoint voltage problem. Furthermore, it can generate a much broader range of output voltages and more abundant waveforms than the conventional Z-source converter. It is also remarked that it has higher efciency than conventional half-bridge converters, where an additional dcdc boost converter is needed to obtain such desired outputs as the proposed converter can, as it is stated in [11] that The Z-source inverter can generate boostbuck voltage, minimize component count, increase efciency, and reduce cost and For applications where over drive is desirable and the available dc voltage is limited, an additional dcdc boost converter is needed to obtain a desired ac output. The additional power converter stage increases system cost and lowers efciency. A typical application of the Z-source half-bridge converter is in the electrochemical power supply, whose output voltages are requested to be varied, including varied positive or negative output voltages and the varied time ratio between positive and negative voltages. These characteristics, desired in electrochemical power supply, are the very ones of the proposed converter. For example, in order to realize the smooth electroplating products, the current densities and directions should be varied according to the requests of electroplating technology [25], [26]. Traditionally, the engineer had to compose several cascaded subcircuits and use complex control methods to generate an overlapped waveform of multioutput voltages [23], [24]. However, the disadvantages lie in that it is hard to control and regulate the output voltages, and the use of cascaded subcircuits not only increases the cost and size but also leads to a more complex bulky structure and instability of the system.

Fig. 3.

Diagram of electroplating.

Electroplating is a kind of electrochemical process, whose fundamental operation diagram and operation principle are shown in Fig. 3 and described in the following. The electroplating process is a redox reaction, with fundamental components: two electrodes (+ and ), a dc source (Vd ), and the solution, as shown in Fig. 3. The purpose of the electroplating is to make the metal ions cover the surface of the negative electrode evenly and smoothly. However, due to the nonuniformity of the solution, the dc-voltage direction and the current density should be changed from time to time, which requires complicated designs according to different products and processes [25], [26]. With the rapid growth of the demand on electroplating products with very different voltages and duties, there are more stringent requirements on the electrochemical power supplies to provide a broad range of outputs, asymmetrical positive and negative voltages, step waves, recurrent pulses, square waves, triangular waves, and saw-tooth waves [24], which can be quite well fullled by the proposed converter. The rest of this paper is organized as follows. Section II gives the system design and analysis. Then, in Section III, the midpoint balances of input capacitors in the traditional converter and the proposed converter are compared to show that the proposed converter is more stable. The parameter design of the Z-network is discussed in Section IV. In Section V, simulations via Simulink software are conducted to verify the analysis. In Section VI, a prototype is designed to illustrate the performance of the proposed converter. Finally, a conclusion is drawn in Section VII. II. S YSTEM D ESIGN AND A NALYSIS The proposed converter is depicted in Fig. 4, in which an LC Z-network, consisting of capacitors C1 and C2 and inductors L1 and L2 , is integrated into a traditional half-bridge converter, consisting of capacitors Cd1 and Cd2 , switches S1 and S2 , and diode D, which is used to prevent the current from owing back to the source. Therein, the use of the inductors in the Z-network is to avoid strong current in the circuit when the switches are in the shoot-through state.

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Fig. 4.

Z-source half-bridge converter.

For simplicity, the following conditions are assumed: 1) All the components are ideal; 2) the dead time in the driven pulses is ignored; 3) L1 = L2 and C1 = C2 in the Z-network; 4) C1 , C2 , Cd1 , and Cd2 are large enough; and 5) the freewheeling diodes of the switches are ignored in the analysis since the load characteristic of the electrochemical solution is resistance or resistance with a small capacitance. Denote the duties of the switches S1 and S2 by D1 and D2 , respectively. The proposed converter performs differently in two cases: D1 + D2 1 and D1 + D2 > 1. A. Case 1: D1 + D2 1 In this case, S1 and S2 are not switched on at the same time; then, the circuit is in the non-shoot-through state. There are three modes corresponding to the states of the switches. In the rst mode, Fig. 5(a) shows an equivalent circuit for the mode when the S1 is on and S2 is off, in which the current ows out of the source, through the diode, the Z-network, and S1 , and then back to the source. The arrows indicate the current directions. In the second mode, Fig. 5(b) shows an equivalent circuit of that when S1 and S2 are off, in which the current also ows out of the source, through the diode and the Z-network, and back to the source; there is no output here. In the third mode, Fig. 5(c) shows an equivalent circuit of that when S2 is on and S1 is off, in which the diode suffers a negative voltage and, thus, turns off. The current ows out of the source, through the load, S2 , and the Z-network, and then back to the source. Furthermore, the current direction is also indicated. The operation process for this case is similar to the traditional one for half-bridge converters, which is not detailed here. B. Case 2: D1 + D2 > 1 In this case, the behavior of the switches in the circuit leads to three modes within a switch period T , which correspond to three linear equivalent circuits: Mode 1, when S1 and S2 are on; Mode 2, when S1 is on and S2 is off; and Mode 3, when S1 is off and S2 is on, as shown in Fig. 6(a)(c), respectively. Denote t0 as the beginning of one period, t1 as the mode transition instant from mode 1 to mode 2, i.e., t1 = t0 + (D2 + D1 1)T , t2 as the mode transition instant from mode 2 to mode 3, i.e., t2 = t1 + (1 D2 )T , and t3 = T as the end of the period.

Fig. 5. Equivalent circuits in case 1. (a) S1 on and S2 off. (b) S1 off and S2 off. (c) S1 off and S2 on.

In the steady state of the converter, its operation process in a switch period is analyzed in the following, and the output voltage vo will be deduced in each mode. 1) Mode 1: t [t0 , t1 ]: As shown in Fig. 6(a), in loops 1 and 2, capacitors C1 and C2 discharge the energy to inductors L1 and L2 ; thereafter, iL1 and iL2 increase. Thus, L1 and L2 store the energy, and one has v L1 = v C 1 (1) v L2 = v C 2 where iL1 , iL2 , vL1 , vL2 , vC1 , and vC2 are the currents of L1 and L2 and the voltages of L1 , L2 , C1 , and C2 , respectively. The voltage of diode D is (vC1 + vC2 Vd ), so D undertakes negative voltage stress and, thus, turns off. The energy of C2 is delivered to the load RL and Cd2 through the C2 RL Cd2 loop, so Cd2 charges and Cd1 discharges.

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In terms of the C2 RL Cd2 loop, the output voltage of the converter is the same as that in (2). Mode 3: t [t2 , t3 ]: In Fig. 6(c), S1 is off, and S2 is on. In loop 1, the source Vd and L1 discharge the energy to C2 ; thus, vC2 increases. Similarly, in loop 2, Vd and L2 discharge the energy to C1 ; thus, vC1 increases. The energy of L2 and Cd2 is delivered to RL through the L2 Cd2 RL loop, so Cd2 discharges and Cd1 charges. In terms of loop 1, one has the same equation as (3). In terms of the Vd DC1 RL Cd2 loop, the output voltage is vo = (vCd2 + vC1 Vd ). As a result, vo can be deduced as follows. The voltagesecond characteristic of L1 leads to
T

(4)

vL1 dt = 0.
0

(5)

Substituting (1) and (3) into (5) leads to (D2 + D1 1)T vC1 +(2 D2 D1 )T (Vd vC2 ) = 0. (6)

Assume that L1 = L2 , C1 = C2 , and C1 and C2 are large enough. Due to the structural symmetry of the Z-network, (6) can be rewritten as v C1 v C2 = 2 D1 D2 Vd . 3 (D1 + D2 ) (7)

The amperesecond property of Cd2 implies that

T

iCd2 dt = 0
0

(8)

Fig. 6. Equivalent circuits in case 2. (a) Mode 1: S1 on and S2 on. (b) Mode 2: S1 on and S2 off. (c) Mode 3: S1 off and S2 on.

where iCd2 is the current of Cd2 . Denote the voltage and current of Cd1 by vCd1 and iCd1 , respectively. It is known from Fig. 6 that vCd1+ vCd2 = Vd . Denote the errors of vCd1 and vCd2 by vCd1 and vCd2 , respectively. Due to Vd being a constant, one has vCd1 = vCd2 , and straightforwardly, iCd1 = iCd2 in terms of i = Cdu/dt. Moreover, from io = iCd1 + iCd2 , one has iCd2 = io /2, where io is the current of the load; thereafter, (8) can be rewritten as (vC2 vCd2 ) (vC2 + vCd2 Vd ) D1 T + (1 D1 )T = 0 2RL 2RL and it follows that vCd2 = (2vC2 Vd )D1 vC2 + Vd . (10) (9)

In terms of the C2 RL Cd2 loop, the output voltage of the converter reads vo = vC2 vCd2 (2)

where vCd2 is the voltage of Cd2 . 2) Mode 2: t [t1 , t2 ]: As shown in Fig. 6(b), S1 is on, and S2 is off. In loop 1, the source Vd and L1 discharge the energy to C2 , so that vC2 increases. In loop 2, the source Vd and L2 discharge the energy to C1 ; thereafter, vC1 increases. Then, the energy of C2 is delivered to the load RL and Cd2 through the C2 RL Cd2 loop, so Cd2 charges and Cd1 discharges. From loop 1, one has v L1 = V d v C 2 . (3)

When switch S1 is on, substituting (7) and (10) into (2) results in the positive output of the converter vp as vp = vo = vC2 vCd2 = (1 D1 ) Vd . 3 2(D1 + D2 ) (11)

When the switch S2 is on and S1 is off, substituting (7) and (10) into (4) leads to the negative output of the converter vn as vn = vo = vd vC2 vCd2 = D1 Vd . (12) 3 2(D1 + D2 )

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Fig. 7.

Relationship gure of D1 , D2 , and vo /Vd .

Fig. 9. Key waveforms of the Z-source half-bridge converter in case 2 when D1 = 0.5 and D2 = 0.7.

Fig. 8.

Zooming in of Fig. 7.

According to (11) and (12), the relationships of D1 , D2 , and vo /Vd are drawn in Fig. 7. Therein, vo /Vd increases dramatically as D1 + D2 is about 1.5, which is zoomed in in Fig. 8. It is remarked from Figs. 7 and 8 that the novel converter can generate abundant output voltages by adjusting D1 and D2 . When vo /Vd < 1, the converter functions as a buck converter; otherwise, the converter acts as a boost converter. Therefore, it is a buckboost converter. By controlling the duty of the switches, special output voltages can be obtained, including the buckboost voltages, asymmetric and symmetric voltages, positive and negative peak output voltages, and the time ratio between positive and negative voltages. Additionally, according to (11) and (12), the values of vp and vn are not equal when D1 = 0.5, but they are equal when D1 = 0.5, which will be explained hereinafter. First, when D1 = 0.5, the key waveforms of the Z-source half-bridge converter in case 2 are drawn in Fig. 9 according to the analysis for three modes, where QS1 and QS2 stand for the driving voltages of switches S1 and S2 , respectively; id is the current of diode D; iL1 and iL2 are the currents of inductances L1 and L2 , respectively; vC1 , vC2 , vCd1 , and vCd2 are the voltages of the capacitances C1 , C2 , Cd1 , and Cd2 , respectively; and vo is the output voltage. Additionally, modes 1, 2, and 3 are distinguished in red, blue, and green colors, respectively. The limited output voltages of the traditional half-bridge converter

Vd /2 and Vd /2 are marked at the output voltage waveform vo , and it is shown that the output voltages of the proposed converter can exceed the limited one. Second, the corresponding waveforms for D1 = 0.5 are shown in Fig. 10. It is remarked that the output voltage vo in Fig. 10 is quite different from that in Fig. 9; the positive and negative values of vo in Fig. 9 are symmetrical, but they are asymmetrical in Fig. 10. This means that the proposed converter generates many kinds of output voltages, fullling the requirements of the electrochemical power supply, such as various positive or negative output voltages, and the regulated duration at negative or positive output voltage, which has prominent advantages over traditional methods by using complicated control methods and multiple cascaded subcircuits. Moreover, the efciency of the converter is given by = Pout Pin 2 2 vp n D1 R + (1 D1 ) v R = Vd Iav 2 2 D1 v p + (1 D1 )vn = RVd Iav D1 (1 D1 )Vd = (3 2(D1 + D2 ))2 RIav

(13)

2 2 where Pout = D1 vp + (1 D1 )vn /R, Pin = Vd Iav , and Iav are the output power, the input power, and the average input current, respectively. Here, the conduction and switching loss is taken into account, which is indicated in Pin Pout .

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Fig. 11. Equivalent circuits of the conventional half-bridge converter. (a) Mode 1: S1 on and S2 off. (b) Mode 2: S1 off and S2 on.

tion of vCd2 by V . Following (15), one has V = vCd2 max vCd2 min = (Vd VCd2 0 ) 1 e
Fig. 10. Waveforms of the Z-source half-bridge converter in case 2 when D1 = 0.7 and D2 = 0.5.
C
D1 T d2 R

(16)

III. M IDPOINT BALANCE OF I NPUT C APACITORS The stability of the midpoint voltage in the converter plays a key role for the systems stability. The midpoint voltages of the input capacitors in the conventional converter and the proposed converter will be analyzed and compared in this section. A. Midpoint Voltage in Conventional Half-Bridge Converters In conventional half-bridge converters, there are always some problems caused by the midpoint imbalance of the input capacitor voltage. In this section, the midpoint voltage in conventional half-bridge converters will be analyzed, and the uctuation equation of the midpoint voltage will be deduced. Fig. 11 shows the equivalent circuits of that in Fig. 1. In a switching period, S1 is on and S2 is off as t [0, D1 T ], while S1 is off and S2 is on as t [D1 T, T ]. Denote the initial voltage of Cd2 by VCd2 0 . In terms of the Kirchhoffs voltage law (KVL), vCd2 can be derived in frequency domain as vCd2 (s) = Vd VCd2 0 Vd . s s + Cd1 2R (14)

In the high-frequency power supply, T is always very small, the input capacitance Cd2 is always quite large, particularly in electrochemical application, and its load is very large. Thus, D1 T is much smaller than Cd2 R, and (16) can be approximated by V D1 t (Vd VCd2 0 ). Cd2 R (17)

B. Midpoint Voltage in Z-Source Half-Bridge Converters It is described in [29] that the input part can be regarded as a dc voltage source or a dc current source due to the Z-network. Similarly, the output part of the Z-network can be treated as a dc current source. Hence, the equivalent circuits are derived as follows. The differential equation of the circuit shown in Fig. 12(a) can be described as Cd 2 dvCd2 = Ip dt (18)

where Ip is the current of the constant current source. Integrating both sides of (18) leads to vCd2 (t) = VCd2 0 + Ip dt. Cd2 (19)

Employing Laplace inverse transformation to (14) results in vCd2 (t) = Vd (Vd VCd2 0 )e
C
t d2 R

Denote the maximal uctuation of vCd2 as shown in Fig. 12 by VZ . Then, from (19), one has VZ = vCd2 max vCd2 min D1 T Ip Ip = dt = D1 T . C C d 2 d2 0

(15)

Denote the maximal and the minimal voltages of vCd2 by vCd2 max and vCd2 min , respectively, and the maximal uctua-

(20)

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IV. PARAMETER D ESIGN The parameters of the Z-network are designed in this section, including capacitor and inductance parameter design. A. Parameter Design of the Capacitor in the Z-Network Normally, the design of the capacitor is to determine the rated voltage and capacitance with a permitted uctuation range xC % (xC is preassigned), a given output voltage Vo , a given output current Io , and a given switching period T . From (7), (11), and (12), one has v C2 = v C2 = 2 D1 D2 Vo , D1 2 D1 D2 Vo , 1 D1 when (S1 ) = (on) (24)

when (S1 , S2 ) = (off, on). (25)

In terms of KCL, the equations of the connected nodes of L2 C1 S2 in Fig. 6(a), L1 C2 S1 in Fig. 6(b), and L2 C1 S2 in Fig. 6(c) can be derived as iL2 = iC1 + io , when (S1 , S2 ) = (on, on) iL = iC2 + io , when (S1 , S2 ) = (on, off) (26) 1 iL2 = io iC1 , when (S1 , S2 ) = (off, on). Denote the rms currents of L2 and C2 by IL2 and IC2 , respectively. Then, from (26), one has I C 2 I L2 =
Fig. 12. Equivalent circuits of the Z-source half-bridge converter. (a) Mode 1: S1 on and S2 off. (b) Mode 2: S1 off and S2 on.

Io . 2

(27)

Ip can be derived by Kirchhoffs current law (KCL) as Ip = Vd VCd2 0 VIp R (21)

where VIp is the voltage of the constant current source. Substituting (21) into (20) leads to VZ = D1 T Vd VCd2 0 VIp . Cd2 R (22)

1) Determination of the Rated Voltage: The range of vC2 is determined by (24) and (25). Thereby, the rated voltage of C2 can be determined by the maximal VC2 M . Considering the safety margin, the rated voltage of C2 is normally set between 1.5VC2 M and 2VC2 M . 2) Determination of the Rated Capacitance: The ripples of the capacitors have great inuence on the stability of the converter, whose permitted uctuation range can be used to design the capacitance. Then, the capacitors in the Z-network can be designed according to the differential equation of capacitors C2 = iC2 dt . dvC2 (28)

Therein, the ratio of VZ to V can be derived from (17) and (22) as Vd VCd2 0 VIp VZ = 100%. V Vd VCd2 0 (23)

The high harmonic frequency of the capacitance is nearly equal to the switching frequency of the converter, as shown in Fig. 9, namely, dt (D1 + D2 1)T. (29)

It is obvious that VZ < V , if VIp is positive; the smaller the VZ /V is, the smaller the ripple in the proposed converter is and, consequently, the more stable the proposed converter is. VZ /V will become very small, or even zero, if VIp is very close to the value of Vd VCd2 0 , and VIp can be designed by the parameters of the Z-network. It is remarked that the proposed converter is more stable than the traditional one with regard to the problem of the input capacitor stability.

Denote the permitted error of VC2 M by dvC2 , according to the permitted uctuation range xC %; dvC2 is expressed as dvC2 = xC %VC2 M . Substituting (27), (29), and (30) into (28) leads to C2 = Io (D1 + D2 1)T . 2xC %VC2 M (31) (30)

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Therein, the range of the capacitance can be calculated, and the maximum is taken as the rated capacitance. B. Parameter Design of the Inductor in the Z-Network Similar to the parameter design of the capacitor, the parameter design of the inductor is to determine the rated current and capacitance with a permitted uctuation range xL % (xL is preassigned), a given output voltage Vo , a given output current Io , and a given switching period T . 1) Determination of the Rated Current: IL2 can be determined by (27). Considering the safety margin, the rated current of L2 is normally taken as 2IL2 . 2) Determination of the Rated Inductance: The ripples of the inductors also have great inuence on the stability of the converter; therefore, the inductance can be designed in terms of the permitted ripples. The inductances in the Z-network can be designed according to the differential equation of inductances L2 = vL2 dtL . diL2 (32)
Fig. 13. Simulation waveforms when D1 = 0.5 and D2 = 0.7.

In the L1 C2 L2 C1 loop, the KVL equation can be expressed as vL2 + vC1 = vL1 + vC2 . In the Z-network, the rms voltages of C1 , C2 , L1 , and L2 are denoted by VC1 , VC2 , VL1 , and VL2 , respectively, and one has vC1 VC2 and VL2 VL1 . Thereby, the maximum of vL2 is derived as V L2 M V C 2 M . (33)

The high harmonic frequency of the inductance is nearly equal to the switching frequency of the converter, as shown in Fig. 9, so the time interval dtL in (32) can be obtained as dtL (D1 + D2 1)T. (34)

Denote the permitted error of IL2 by diL2 . According to the permitted uctuation range xL %, diL2 is expressed as diL2 = xL %IL2 . (35)

Substituting (24), (25), (27), and (33)(35) into (32) leads to the inductance of L2 2VC2 M (D1 + D2 1)T L2 = . xL %Io V. S IMULATION R ESULTS To verify the feasibility and validity of the proposed converter, Simulink software is applied for the simulation of the converter. The preassigned parameters are as follows: xC % = 1%, xL % = 10%, Vd = 48 V, Vo = 100 V, Io = 10 A, and T = 20 s. According to the design, the parameters of the converter can be calculated: C1 = C2 = 482.5 F and L1 = L2 = 105.5 H. However, in practice, the parameters can be chosen as follows: C1 = C2 = 470 F and L1 = L2 = 100 H.
Fig. 14. Simulation waveforms when D1 = 0.7 and D2 = 0.5.

(36) The simulation results are shown in Figs. 13 and 14, which are consistent to the theoretical analyses shown in Figs. 9 and 10. VI. E XPERIMENT R ESULTS A prototype of the Z-network converter is built as shown in Fig. 15, and the parameters are chosen as follows: Cd1 = Cd2 = 470 F, C1 = C2 = 470 F, L1 = L2 = 100 H, R = 100 , and T = 20 s. The main circuit is in the left side in Fig. 15, composed of L1 , L2 , C1 , C2 , switches (type: IRFP450), and the resistive load R, while the driving circuit is in the right side, composed of

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Fig. 17. Experimental waveforms in shoot-through case (D1 = 0.7 and D2 = 0.5).

Fig. 15. Prototype of the proposed converter.

Fig. 18. Ripple experiment waveform of vCd2 in the proposed converter.

Fig. 16. Experimental waveforms in shoot-through case (D1 = 0.5 and D2 = 0.7).

two SG3525 ICs being applied to generated two synchronous overlapped driving signals and TLP250 ICs being used to drive the switches, whose working frequency and duties can be adapted by the adjustable resistors. The waveforms of the converter at D1 = 0.5 and D2 = 0.7 with an input voltage of 40 V are shown in Fig. 16. Therein, the upper waveform refers to VGS (gatedrain voltage) of the switch S1 , the middle one is VSD (sourcedrain voltage) of the switch S2 , which is not but can be synchronized to the driving waveform of S2 , and the lower one is the output voltage of the load R, whose negative and positive output voltages are symmetric, and they are all about 50 V. This veries the analytical and simulation results. Fig. 17 shows the experimental waveforms of the converter when D1 = 0.7 and D2 = 0.5. Therein, the negative and positive output voltages are asymmetric; the positive one is about 20 V, which is nearly equal to Vd /2 and has a width of D1 T , while the negative one is 40 V, which is much larger than Vd /2. The experimental results are also consistent with the simulation results. In order to verify that the proposed converter has a balanced midpoint voltage, the experimental result is shown in Fig. 18. Therein, the ripples of vCd2 in the proposed converter have maximal peak-to-peak values just about 98.4 mV. The start-up waveforms with the start-up time of about 80 ms are shown in Fig. 19. The efciency is obtained through an experiment and the calculation according to (13), with regard to the resistance

Fig. 19. Start-up output waveforms.

Fig. 20. Comparison between the experimental and estimation efciencies.

increasing from 1 to 10 at a step length of 1 , as shown in Fig. 20. It is remarked that, as the resistance increases, the power reduces and the efciency decreases; moreover, the output voltages can be regulated.

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VII. C ONCLUSION Inspired by the Z-source converter, this paper has proposed a novel Z-source half-bridge converter that can output buck boost voltages. Different from the Z-source converter, it needs only one LC Z-network between the input capacitors and the switches. Additionally, the novel converter is more stable than the conventional one according to the analysis of the midpoint balance of input capacitors. Moreover, the converter has been analyzed in two different states, including the shoot-through and non-shoot-through states. Furthermore, the feature of the proposed converter owning abundant outputs under an appropriate control is very desirable for requirements of the electrochemical power supply. Finally, simulations and experiments have been carried out to verify the effectiveness of the proposed converter. ACKNOWLEDGMENT The rst author would like to thank F. Xie for his help in conducting a part of the experiments. R EFERENCES
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Guidong Zhang was born in Guangdong, China, in 1986. He received the B.Sc. degree in electrical engineering and automation from the School of Automation and Information Engineering, Xian University of Technology, Xian, China, in 2008. He has been working toward the Ph.D. degree in power electronics and electric transmission, by taking successive postgraduate and doctoral programs, in the School of Electric Power, South China University of Technology, Guangzhou, China, since September 2010. He has also been working toward the Ph.D. degree at the Faculty of Mathematics and Computer Science, FernUniversitt in Hagen, Hagen, Germany, since 2011. His research interests include power electronics topology and applications.

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Zhong Li received the B.Sc. degree from Sichuan University, Chengdu, China, in 1989, the M.Sc. degree from Jinan University, Guangzhou, China, in 1996, the Ph.D. degree from the South China University of Technology, Guangzhou, in 2000, and the D.Sc. (Habilitation) degree from the FernUniversitt in Hagen, Hagen, Germany, in 2007. He was an Adjunct Professor with the FernUniversitt in Hagen. He is currently with the Faculty of Engineering, University of DuisburgEssen, Duisburg, Germany. His research interests include fuzzy logic and fuzzy control, chaos theory and chaos control, intelligent computation and control, complex networks, and swarm intelligence. He serves as Associate Editor for six international journals and has published three books with Springer-Verlag, 18 book chapters, 53 journal papers, and 38 conference papers.

Wenxun Xiao was born in Hainan, China, in 1979. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the South China University of Technology, Guangzhou, China, in 2002, 2005, and 2008, respectively. Since 2008, he has been with the School of Electrical Power, South China University of Technology, where he is currently an Associate Professor. His research interests include topology and control methods of switching power supplies, and multiphysics coupling of power electronics equipment.

Bo Zhang (M03) was born in Shanghai, China, in 1962. He received the B.Sc. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 1982, the M.Sc. degree in power electronics from Southwest Jiaotong University, Chengdu, China, in 1988, and the Ph.D. degree in power electronics from the Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 1994. He is currently the Vice Dean of the School of Electric Power, South China University of Technology, Guangzhou, China, where he is also a Professor. He has authored or coauthored more than 330 papers and is the holder of 30 patents. His current research interests include nonlinear analysis and control of power supplies and ac drives.

Dongyuan Qiu (M03) was born in China in 1972. She received the B.Sc. and M.Sc. degrees from the South China University of Technology, Guangzhou, China, in 1994 and 1997, respectively, and the Ph.D. degree from the City University of Hong Kong, Kowloon, Hong Kong, in 2002. She is currently a Professor with the School of Electric Power, South China University of Technology, Guangzhou. Her main research interests include design and control of power converters, fault diagnosis, and sneak circuit analysis of power electronic systems.

Wolfgang A. Halang received the Ph.D. degree in mathematics from Ruhr-Universitt Bochum, Bochum, Germany, in 1976, and the Ph.D. degree in computer science from the Universitt Dortmund, Dortmund, Germany, in 1980. He worked both in industry (Coca-Cola GmbH and Bayer AG) and in academia (King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia, and the University of Illinois at Urbana Champaign, Urbana, IL, USA), before he was appointed as the Chair of Applications-Oriented Computing Science and the Head of the Department of Computing Science, University of Groningen, Groningen, The Netherlands. Since 1992, he has been the Chair of Computer Engineering with the Faculty of Electrical and Computer Engineering, FernUniversitt in Hagen, Hagen, Germany, where he was the Dean from 2002 to 2006. He was a Visiting Professor with the University of Maribor, Maribor, Slovenia, in 1997, and the University of Rome II, Rome, Italy, in 1999. His research interests comprise all major areas of hard real-time computing with special emphasis on safety-related systems. He is the Founder and was the European Editor-in-Chief of the journal Real-Time Systems, is a Member of the Editorial Boards of four other journals, was a Codirector of the 1992 North Atlantic Treaty Organization Advanced Study Institute on RealTime Computing, has authored 12 books and some 350 refereed book chapters, journal publications, and conference contributions, has edited 20 books, is the holder of 12 patents, and has given some 80 guest lectures in more than 20 countries. Dr. Halang is active in various professional organizations and technical committees as well as being involved in the program committees of some 180 conferences. In the International Federation of Automatic Control, he chaired the Technical Committee on Real-Time Software Engineering before he became a Member of the Technical Board from 2002 to 2008 chairing the Coordinating Committee on Computers, Cognition, and Communication for Control.