Static & Dynamic Logic

VLSI Design VLSI Design

Static & Dynamic Logic
By Dr. Yaseer A. Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila
Outline
Introduction to Combinational & Sequential
Circuits
De Morgans Law & Boolean Algebra Rules
Static & Dynamic Logic Circuits
Memory Logic Circuits
2
Combinational Vs. Sequential Logic
Logic
Logic
Combinational logic circuits
Output depends only on present input
Sequential logic circuits
Output depends on present input and present state of circuit
3
Logic
Circuit
Logic
Circuit
Combinational Circuit Combinational Circuit
Sequential Circuits
State
Output=f(input)
Output=f(Input, Previous Input)
Design Procedure
Combinational logic design procedure
Start with the problem statement
Determine the number of inputs variables & required number of output variables
Derive a truth table that defines the required relationship between I/O
Simplify each output function (Karnaugh maps)
Draw the logic diagram
Sequential logic design procedure
Derive a state/output table from problem specification
Minimize number of states in state/output table by eliminating equivalent states
Choose a set of state variables. Assign to each state a unique combination from set
4
Choose a set of state variables. Assign to each state a unique combination from set
derived above
Create a transition/output table
Choose a flip-flop type & construct its excitation table
Using excitation table fill the values for input excitation function columns on
transition/output table
Derive the excitation & output equations
Draw logic diagram
De Mogans Law
Commutative law of addition for two variables is written as: A+B = B+A
Commutative law of multiplication for two variables is written as: AB = BA
Associative law of addition for 3 variables is written as: A+(B+C) = (A+B)+C
A
B
A+B
B
A
B+A
A
B
AB
B
A
B+A
A
A+(B+C)
A

A+B
5
Associative law of multiplication for 3 variables is written as: A(BC) = (AB)C
Distributive law is written for 3 variables as follows: A(B+C) = AB + AC
B
A+(B+C)
C
B
(A+B)+C
C

B+C
A
B
A(BC)
C
A
B
(AB)C
C

BC
AB
B
C
A
B+C

A
B
C
A
X
X
AB
AC
X=A(B+C) X=AB+AC
Rules of Boolean Algebra
DeMorgans theorems provide mathematical verification of:
1 . 6
. 5
1 . 4
0 0 . 3
1 1 . 2
0 . 1
= +
= +
=
=
= +
= +
A A
A A A
A A
A
A
A A
BC A C A B A
B A B A A
A AB A
A A
A A
A A A
+ = + +
+ = +
= +
=
=
=
) )( .( 12
. 11
. 10
. 9
0 . 8
. 7
A, B, and C can represent a single variable or a combination of variables
6
DeMorgans theorems provide mathematical verification of:
Equivalency of NAND & negative-OR gates
Equivalency of NOR & negative-AND gates
Z Y X W
Z Y X
Z Y X
Z Y X

+ +
+ +

Complement of two or more ANDed variables is equivalent to OR of
complements of individual variables
Complement of two or more ORed variables is equivalent to AND of
complements of individual variables
Y X Y X + =
Y X Y X = +
NAND
Negative-OR
Negative-AND
NOR
Exercise
) (
) (
F E D C B A
EF D C B A
DEF ABC
D C B A
+ + +
+ +
+
+ +
Boolean function is a expression formed with binary variables, OR, AND, NOT
operators
F=xyz
Boolean function can be algebraically expressed from truth table by taking OR all
minterms that produce 1 as output in function
Boolean function can be algebraically expressed from truth table by taking AND
all maxterms that produce 0 as output in function
Boolean Function
7
Digital Design
Digital design engineers always tries to build circuit using universal gates
(NAND or NOR) as they are easy to fabricate
Rules of obtaining NAND gate implementation of Boolean function
Convert all AND gates into NAND gates by using AND-NOT symbol
Convert all OR gates into NAND gates by using NOT-OR symbol
For every bubble that is not counteracted by another bubble along same line,
insert a NOT gate or complement the literal from its original appearance
Rules of obtaining NOR gate implementation of Boolean function
Convert all OR gates into NOR gates by using OR-NOT symbol
8
Convert all OR gates into NOR gates by using OR-NOT symbol
Convert all AND gates into NOR gates by using NOT-AND symbol
For every bubble that is not counteracted by another bubble along same line,
insert a NOT gate or complement the literal from its original appearance
Examples
A
B=1
C=A
A
B=1
C=A
A
B=0
C=A
A
B=0
C=A
A
B=0
C=0
A
B=0
C=1
A
B=1
C=1
A
B=1
C=0
A
B
A
B
C C
A
B
C
A A
A A
9
B=0
B=1
A
B
C
C
A
B
C
A
B
C
A
B
C
A
B
C
Simplification of Boolean Algebra
F
A
A
B
F
10
F
B
C
C
F
Random Logic
Random Logic: Circuit design using NAND, NOR & NOT gates (often
called AOI Logic gate represents = AND-OR-Inverter Logic)
11
Random logic: Adder
Logic Families
Logic families are classified as:
Static Logic
Do not use clock signal
Slower
Easy to design
Dynamic Logic
Use clock signal
More faster
Difficult to design
12
Static CMOS Circuit
At every point in time (except during switching transients) each gate output is
connected to either VDD or VSS via low-resistive path
Outputs of gates assume at all times the value of Boolean function,
implemented by circuit (ignoring, once again, transient effects during switching
periods)
PUN consists PMOS transistors & PDN consists NMOS transistors
PUN & PDN implementations are complimentary to each other
PMOS NMOS
Series topology Parallel topology
V
DD Make a connection from VDD to
F when F(In1, In2,Inn)=1
13
V
SS
PUN
PDN
In1
In2
In3
F = G
In
1
In
2
In
3
PUN and PDN are Dual Networks PUN and PDN are Dual Networks
PMOS Only
NMOS Only
Make a connection from VDD to
VSS when F(In1, In2,Inn)=0
No steady state path b/w VDD & VSS (no static
power consumption)
Delay a function of load capacitance &
transistor resistance
Comparable rise & fall times (under
appropriate transistor sizing conditions)
High noise margins
Full rail to rail swing
VOH & VOL are at VDD & VSS
Low output impedance, high input impedance
Design Method
NMOS devices pull the output to 0 when the gate inputs are 1
PMOS devices pull the output to 1 when the gate inputs are 0
Consider a function to be realized: F(A,B,C, . . .)
NMOS pull-down network must realize the pull-down function
FPD = F(A,B,C,)
PMOS pull-up network must realize the pull-up function
FPU = F(A,B,C)
The literals in FPU have to be inverted, because the p-channel transistors
conduct, if their gate input is 0 (low)
14
Rules for Logic Formation
Rule 1: NMOS transistors in series implement the AND operation
Rule 2: NMOS transistors in parallel implement the OR operation
Rule 3: Logic functions in series are ANDed together
Rule 4: Parallel nMOS branches OR the individual branch functions
Rule 5: Parallel connections of NMOS transistors have to be transformed to
serial connections of PMOS transistors. The input literals applied to the PMOS
transistors are identical with the gate inputs of the NMOS transistors (no
inversion needed)
Rule 6: Serial connections of NMOS transistors have to be transformed to
parallel connections of PMOS transistors. Input literals remain unchanged parallel connections of PMOS transistors. Input literals remain unchanged
Rule 7: Parallel connected logic blocks of the NMOS network
Serial connection in the PMOS network
Rule 8: Serial connected logic blocks of the NMOS network
Parallel connection in the PMOS network
15
PUN/PDN Rules
NMOS is ON when Vg=1, OFF when Vg=0. For PMOS vice versa
NMOS produces strong Zeros while PMOS produces strong Ones
NMOS connected in Series corresponds to AND function while in Parallel OR
function. PMOS connected in Series corresponds to NOR function & Parallel to
NAND function
Using De Morgans Theorem using
PUN/PDN of complementary CMOS structure are dual network. This means
Parallel connection in PUN corresponds to Series connection in PDN & vice
versa
( ) B A B A = +
) ( B A B A + =
16
versa
Complementary gates is naturally inverting, implementing only functions such as
NAND, NOR and XNOR. Noninverting Boolean function such as AND, OR, XOR
in a single stage is not possible & requires addition of an extra inverter stage
Number of transistors required to implement an N-input logic gate is 2N
NMOS/PMOS Serial/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
PMOS switch closes when switch control input is low
NMOS: 1 = ON, PMOS: 0 = ON
Series: both must be ON, Parallel: either can be ON
X Y
A B
X
Y
A
B
A C A C
17
Y = X if A and B
NMOS Serial Connection
X
Y
A
B
Y = X if A OR B
NMOS Transistors pass a
strong 0 but a weak 1
NMOS Parallel Connection
Y = X if A AND
B = A + B
PMOS Serial Connection
X Y
B
Y = X if A OR B = AB
PMOS Transistors pass a
strong 1 but a weak 0
PMOS Parallel Connection
B D
A
B
C
D
A B C D
A B
C D
B
D
Y
A
C
A
C
B D
B
D
Y
Construction of PDN
NMOS devices in series implements NAND function
NMOS devices in parallel implements NOR function
A
B
A B
A B
A + B
18
CMOS Inverter
A Y
0
1 0
V
DD
A= 1 Y= 0
GND
ON
OFF
A Y
A Y
0 1
1 0
V
DD
A= 0 Y= 1
OFF
ON
19
GND
CMOS NAND Gate
A B F
0 0 1
0 1 1
1 0 1
vdd
A
B
A
B
C
A
B
C
B A C =
20
1 1 0
A
B
Y
C
3 input NAND gate 3 input NAND gate 4 input NAND gate
In
3
In1
In2
In4
In
1
In
2
In
3
In
4
V
DD
Out
CMOS NOR Gate
B A C + =
A B C
0 0 1
0 1 0
A
B
C
D
Y
A
C
B
A
B
vdd
21
0 1 0
1 0 0
1 1 0
Y
4 input NOR gate
A
B
2 input NOR gate
AND/OR Gate
vdd
A
B
A
vdd
Gnd
C
NAND
!nverter
B
C = A B
A
B
C
22
NAND
A
B
A B
vdd
vdd
Gnd
C
!nverter
NOR
A
B C
B A C + =
XOR Gate
A B C
0 0 0
0 1 1
1 0 1
A
B
Y
vdd
A
B
A
A
B
B
Y
vdd
A
B
A
A
A
B
Y
B A B A Y + =
B A AB Y + =
23
1 1 0
A B
A
B
A
B
A B

A B
A
B B

XNOR Gate
A B C
0 0 1
0 1 0
A
B
Y
vdd
A
B
A
B
A B
Y
vdd
A
B
A
A
A
B
B
B
Y
vdd
!nverter
B A B A Y + =
B A AB Y + =
24
A B
A
B
A
B
A B
1 0 0
1 1 1
A
B

B
XOR

Complex NMOS Logic
25
2-input NMOS NOR gate
N-input NMOS NOR gate
2-input NMOS NAND gate
Complex NMOS Logic
26
XOR gate
XNOR gate
Relatively it is easy to obtain PDN, simply because we already had Y in terms of
uncomplemeted inputs
To obtain PUN, we had to manipulate the given Boolean expression to express
Y as a function of complemented variables
) ( CD B A Y + =
) ( CD B A Y + =
Complex Gate
) (
CD B A
CD B A
CD B A Y
+ =
+ + =
+ =
) ( D C B A
CD B A
+ + =
+ =
27
Systematic Function Construction
F= A ( B C + D)
28
F=AB+(A+B)C
Examples
B C A F + =
!n series
!n parallel
B C A F + =
B C A F
B C A F
=
+ =
A
B D
A C
vdd
) C (A B D A F + + =
Start from innermost term
29
B C) A ( F + =
vdd
A
C
B
A C
B
F
B D
A D
A
C
B
F
Examples
)) C (A B D A ( ) D (E F + + + =
Start from the innermost term
A
A
C
vdd
E D
V
DD
A
B
C
D
F = D + A
(B+C)
30
B D
A D
A
C
B
F
E
D
D
A
B C
Examples
( ) Y A B C D = + +
Y
D C
B
A
V
DD
C
( ) ( )
( ) ( )
( ) ( )
( ) ( ) D C B A Y
D C B A Y
D C B A Y
D C B A Y
+ =
+ + =
+ =
+ + =
( ) ( ) D C B A Y + + =
F = (D + A (B + C))
D
A
B
C
31
A B
Y
C
D
Y
A
A
B
B
C
C
D
D
D
A
B C
Full Adder
32
AOI (AND-OR-INVERT) CMOS Gate
AOI complex CMOS gate can be used to directly implement a sum-of-products
Boolean function
Pull-down N-tree can be implemented as follows:
Product terms yield series-connected NMOS transistors
Sums are denoted by parallel-connected legs
Complete function must be an inverted representation
Pull-up P-tree is derived as the dual of the N-tree
33
OAI (OR-AND-INVERT) CMOS Gate
An Or-And-Invert (OAI) CMOS gate is similar to the AOI gate except that it is an
implementation of product-of-sums realization of a function
N-tree is implemented as follows:
Each product term is a set of parallel transistors for each input in the term
All product terms (parallel groups) are put in series
The complete function is again assumed to be an inverted representation
P-tree can be implemented as the dual of N-tree
Note: AO & OA gates (non-inverted function representation) can be
implemented directly on the P-tree if inverted inputs are available
34
Full Adder
V
V
DD
DD
V
DD
V
DD
A B
C
i
S
X
B
A
C
i A
B B A
C
i
A B C
i
C
i
A
C
i
A
B
B A
28 transistors 28 transistors
35
C
o B
C
o
= AB + C
i (A+B)
V
DD
C
i
A
B B A
B
A
A B
Kill
Generate
"1"-Propagate
"0"-Propagate
V
DD
C
i
A B C
i
C
i
B
A
C
i
A
B
B
A
V
DD
S
C
o
24 transistors
Transistor Sizing
Transistor sizing is the ratios of the Width/Length (W/L) of the transistor
These ratios provide the gate with current-driving capability in both directions
equal to that of the basic inverter
(W/L)=n and (W/L)
p
=P, n is usually 1.5 to 2 & for matched design p=(
n
/
p
)n
We should find the input combinations that result in lowest output current & then
choose sizes that will make this current equal to that of the basic inverter
We consider the parallel/series connections & find equivalent W/L ratios
Transistors connected in series:
1
Transistors connected in series:
Transistors connected in parallel:
...
) / (
1
) / (
1
1
) / (
2 1
+ +
=
L W L W
L W
eq
... ) / ( ) / ( ) / (
2 1
+ + = L W L W L W
eq
V
DD
GND
NMOS (2/.24 = 8/1)
PMOS (4/.24 = 16/1)
metal2
metal1
polysilicon
In Out
metal1-poly via
metal2-metal1 via
metal1-diff via
pdiff
ndiff
36
Example
Two identical MOS transistors with individual W/L ratios of 4 result in an
equivalent W/L of 2 when connected in series & of 8 when connected in parallel
Worst case (lowest current) for PDN is obtained when only one of NMOS
transistors is conducting
We therefore select W/L of each NMOS transistor to be equal to that of NMOS
transistor of basic inverter, namely, n
For PUN, worst-case situation is when all inputs are low & four series PMOS
transistors are conducting
Since equivalent W/K will be one-quarter of that of each PMOS device, we
should select W/L ratio of each PMOS transistor to be four times that of Q of should select W/L ratio of each PMOS transistor to be four times that of Q
P
of
basic inverter, that is ,4p
37 n & p denote the (W/L) ratios of Q
N
& Q
P
, of the basic inverter
Example
Provide transistor W/L ratios for the logic circuit . Assume that for the basic
inverter n = 1.5 and p =5 and that the channel length is 0.25m?
Solution:
Consider PDN: In worst case, when Q
NB
is ONB & either Q
NC
or Q
ND
is ON
Worst case, we have two transistors in series
Therefore, we select each of Q
NB
, Q
NC
, and Q
ND
to have twice the width of the n-
channel device in the basic inverter, thus
Q
NB
: W/L = 2n = 3 =0.75/0.25
Q
NC
: W/L = 2n = 3 =0.75/0.25
Q : W/L = 2n = 3 =0.75/0.25 Q
ND
: W/L = 2n = 3 =0.75/0.25
38
Example
For transistor Q
NA
, select W/L to be equal to that of the n-channel device in the
basic inverter:
Q
NA
: W/L = n = 1.5 = 0.375/0.25
Next, consider the PUN
Here, we see that in the worst case, we have three transistors in series: Q
PA
,
Q
PC
, and Q
PD
.
Therefore, we select the W/L ratios of each of these to be three times that of
Q
P
in the basic inverter, that is, 3p, thus
Q
PA
: W/L = 3p = 15 =3.75/0.25
Q : W/L = 3p = 15 =3.75/0.25 Q
PC
: W/L = 3p = 15 =3.75/0.25
Q
PD
: W/L = 3p = 15 =3.75/0.25
39
CMOS Transmission Gates (TG)
CMOS TG can be constructed by parallel combination of NMOS & PMOS
transistors, with complementary gate signals
TG input signal transmitted to output without threshold voltage attenuation
C
A
B
C
B A
CB
C=0, CB=1
A B
C=1, CB=0
A
B
0 Strong 0
Input
Output
1 Strong 1
C=1, CB=0
C=1, CB=0
40
C
B A
C
C
A
B 1 Strong 1
0V Vdd 0V
0V
|VTP|
Vdd
Vdd 0V Vdd
Vdd-VTN
Vdd
Vdd
A
B
F
B
A
B
B
M1
M2
M3/M4
XOR
CMOS Transmission Gate
B
B
41
A
F
B
A
B
B
M1
M2
M3/M4
A
A
B
B
B A B A +
XOR
Half Adder
TG based Full Adder
42
Full Adder
A
B
P
C
i
V
DD
A
A A
V
DD
C
i
A
P
A
B
V
DD
V
DD
C
i
C
i
C
o
S
C
i
P
P
P
P
P
Sum Generation
Carry Generation
Setup
S
S
D0
D1
Y
S
2x1 MUX
Only 4 transistors
Multiplexers (MUX)
2x1 MUX
S
S
A
B
S B AS +
S0
A
B
C
S0 S1 S1
OUT
43
A
M
2
M
1
B
S
S
S
F
V
DD
Pass Transistor based MUX
4x1 Multiplexor
D
Two Level MUX
TG Tristates
Tristate buffer produces Z when not enabled
Non-restoring Tristate
TG acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN
A Y
EN
EN
Tristate inverter produces restored output
Violates conduction complement rule
Because we want Z output
44
Because we want Z output
A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN
Multiplexers (MUX)
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1
Y
Gate level MUX Design
45
0 1
D S SD Y + =
4
4
D1
D0
S
Y
4
2
2
2
Y
2
D1
D0
S
20 transistors
Gate level MUX Design
MUX chooses one of 4 inputs using two selects
Inverting MUX
Use compound AOI
Or pair of tristate inverters
Essentially the same thing
Noninverting MUX adds an inverter
S
D0
D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S
Inverting
MUX
Multiplexers (MUX)
46
MUX chooses one of 4 inputs using two selects
Two levels of 2:1 MUXes
Or four tristates
S0
D0
D1
0
1
0
1
0
1
Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
4x1 MUX
Fast Complex Gate - Design Techniques
Design techniques to reduce delay of large fan-in circuits
Transistor Sizing
Increase transistor size, while larger parasitic capacitances & propagation delay
Progressive Transistor Sizing
Uniform sizing, reduces the dominant resistance
Input Reordering
Some signals might critical than others. Not all inputs of a gate arrive at
same time
Logic Restructuring
Manipulating logic equations can reduce fan-in & reduce gate delay
47
C
L
In
1
In
N
In
3
In
2
Out
C
1
C
2
C
3
M1 > M2 > M3 > MN
M1
M2
M3
MN
Distributed RC-line
Can Reduce Delay with more than 30%!
In
1
In
3
In
2
C
1
C
2
C
L
M1
M2
M3
In
3
In
1
In
2
C
3
C
2
C
L
M3
M2
M1
critical path critical path
critical path critical path
Manipulating logic equations can reduce fan-in & reduce gate delay
Buffering: Isolate Fan-in from Fan-out
C
L
C
L
Improved Logic Design Improved Logic Design
Input reording
Fan-In & Fan-Out
Fan-In = Number of inputs to a logic gate
4 input NAND has a FI = 4
2 input NOR has a FI = 2, etc.
Fan-Out = Number of gate inputs which are driven by a particular gate output
FO = 4 in Fig. b below shows an output wire feeding an input on four
different logic gates
Circuit delay of a gate is a function of both Fan-In & Fan-Out
Ex. m-input NAND: t
dr
= (R
p
/n)(m.n.C
d
+ C
r
+ k.C
g
) = t
internal-r
+ k.t
output-r
where n=width multiplier, m=fan-in, k=fan-out, Rp=resistance of min inverter P
Tx, Cg=gate capacitance, Cd=source/drain capacitance, Cr=routing (wiring) Tx, Cg=gate capacitance, Cd=source/drain capacitance, Cr=routing (wiring)
capacitance
48
Fan-In & Fan-Out
Circuit fall delay can be written in a similar manner
Ex. m-input NAND: t
df
= m(R
n
/n)(m.n.C
d
+ C
r
+ k.C
g
) = t
internal-f
+ k.t
output-f
where n=width multiplier, m=fan-in, k=fan-out, Rn=resistance of min inverter
NMOS Tx, Cg=gate capacitance, Cd = source/drain capac, Cr = routing (wiring)
capacitance
If we set t
dr
=t
df
for the case of symmetrical rise & fall delay, we get Rp = m Rn

p
W
p
= (
n
W
n
)/m
49
CMOS Logic Families
Complementary Logic
Standard CMOS
Clocked CMOS (C
2
MOS)
BICMOS (CMOS logic with Bipolar driver)
Ratio Circuit Logic
Pseudo-NMOS
Saturated NMOS Load
Saturated PMOS Load
Depletion NMOS Load (E/D)
Source Follower Pull-up Logic (SFPL) Source Follower Pull-up Logic (SFPL)
Dynamic Logic:
CMOS Domino Logic
NP Domino Logic (also called Zipper CMOS)
NORA Logic
Cascade voltage Switch Logic (CVSL)
Sample-Set Differential Logic (SSDL)
Pass-Transistor Logic
50
Clock Signal
Used to synchronize data flow through a digital network
Clocked static or dynamic circuits
Problems: clock skew (delay caused by clock distribution wires)
51
Ideal nonoverlapping 2-phase clocks 2-phase clocking
Single & Multiple Clock Signals
For nonoverlapping clock phases and fine tuned and well designed delay
lines (realized as Transmission gates) have to be inserted in order to avoid
overlapping of and
Generation of
inverted clock phase
TG delay circuit
52
Psuedo 2- clocking
Clocked shift register circuit
Shift register
Clocked Static Logic
Dynamic CMOS Circuits
Dynamic logic is temporary (transient) in that output levels will remain valid
only for a certain period of time
Static logic retains its output level as long as power is applied
Dynamic logic is due to charging & discharging capacitance
Precharge clock to charge the capacitance
Evaluate clock to discharge the capacitance depending on condition of
logic inputs
Precharge Evaluate Precharge
1
2
A
Y
1
1
A
Y

4/3
2/3
A
Y
53
Y
Dynamic NMOS Inverter
Dynamic PMOS Inverter
M
p
M
e
V
DD
PDN
f
In
1
In
2
In
3
Out
M
e
M
p
V
DD
PUN
f
In
1
In
2
In
3
f
f
Out
C
L
C
L
f p network
f nnetwork
1
Static Static
Dynamic Dynamic
Pseudo-NMOS
Dynamic CMOS Circuits
Advantages over static logic:
Use of low leakage of FETs to store charge instead of moving current.
Provides higher density, faster operation at cost of reduced noise immunity
Avoids duplicating logic twice as both N-tree & P-tree
Faster gates & used in very high performance applications
Best for wide OR/NOR gates (e.g. bit-lines), providing 50% delay
improvement over static CMOS
Simple sequential memory circuits; amenable to synchronous logic
Transistor count is reduced from 2n (static CMOS) to n+2 for dynamic
precharged CMOS (but now: 2 phases of operation)
54
precharged CMOS (but now: 2 phases of operation)
High density achievable
Consumes less power (in some cases)
Consumes 2xpower due to its phase activity (unconditional pre-
charging), not counting clock power
Disadvantages compared to static logic:
Problems with clock synchronization & timing
Design is more difficult
Increased sensitivity to noise
Capacitive crosstalk, Charge sharing, Power supply, Feed through noise
Single clock is to accomplish both pre-charge & evaluation operations
When is low: PMOS pre-charge transistor Mp charges Vout to Vdd, since it
remains in its linear region during final pre-charge
During this time, logic inputs A1 B2 are active & Me is OFF, no charge
will be lost from Vout
When is high: Mp is turned OFF & NMOS evaluate transistor Me is turned ON,
allowing for Vout to be selectively discharged to GND depending on logic inputs
If A1 B2 inputs are such that a conducting path exists b/w Vout & Me,
then Vout will discharge to 0, Otherwise, Vout remains at Vdd
No DC current flows during precharge or evaluate phase
Dynamic CMOS Circuits
No DC current flows during precharge or evaluate phase
Power is dynamic P = C
N
V
dd
2
f where C
N
represents an equivalent total
capacitance on the output, f=clock frequency, =logic repetition rate
55
Dynamic Logic
56
Dynamic NMOS inverter
Precharge & Evaluate
Precharge n/w for worse case
Evaluation discharge n/w
Complex Dynamic Logic
Cascading Problem in Dynamic CMOS Logic
If several stages of dynamic circuit are cascaded together using same clock , a
problem in evaluation involving a built-in race condition will exist
During pre-charge, both Vout1 & Vout2 are pre-charged to Vdd
When goes high to begin evaluate, all inputs at stage-1 require some time to
resolve, but during this time charge may erroneously be discharged from Vout2
Assume 1
st
-stage NMOS logic conducts & fully discharges Vout1, but all
inputs are not resolved, it takes some time to discharge Vout1 to GND
If, during this time delay, 2
nd
-stage has input condition shown with bottom
NMOS transistor gate at logic 1, then Vout2 will start to fall & discharge its
CL until Vout1 finally evaluates & turns OFF the top series NMOS transistor CL until Vout1 finally evaluates & turns OFF the top series NMOS transistor
in stage-2
Result is an error in output of 2
nd
-stage Vout2
57
Possible Solutions:
Two phase clocks
Use of inverters to create
Domino Logic
NP Domino Logic
Zipper/NORA logic
Dynamic Cascades
PMOS & NMOS blocks have to be installed alternated in order to avoid glitches
58
Cascaded NMOS-NMOS glitch problem
Dynamic cascades
Pass Transistor Logic
Transistor are used as switches which are controlled by input literals do logic
Inputs drive diffusion terminals as well as gates
Limited fan-in & excessive fan-out
Noise vulnerability (not restoring)
Supply voltage offset/bias vulnerability
Decode exclusivity (else short-circuit!)
Poor high voltage levels if NMOS-only
Pass-logic may consume half the power of static logic. But be careful of Vt drop
resulting in static leakage
Pass-gate logic is not appropriate when long interconnects separate logic stages
Pass Transistor Model
Pass-gate logic is not appropriate when long interconnects separate logic stages
or when circuits have high fan-out load (use buffering)
59
Complementary switch Pass Transistor NXOR
A = 5 V
B
C = 5V
C
L
A = 5 V
C = 5 V
B
M
2
M
1
M
n
V
B
NMOS only switch
Does not pull up to 5V, but 5V
Vth loss causes static power consumption
V
TN
Pass Transistor Logic
Criteria for Clocked CMOS & Pass-Gate Logic
Clocked CMOS logic
Mitigates hot electron effects
Pass-gate logic
Fast, if few pass gates in series
Good for complex functions
Small area, low power
60
Clocked CMOS logic
Mitigates hot electron effects
Pass-gate logic
Fast, if few pass gates in series
Good for complex functions
Small area, low power Small area, low power
Pass Transistor Circuits
Pass transistor (MP) is NMOS device, but could also be implemented with TG
C
x
is equivalent capacitance of input gate of second NMOS (part of inverter
or logic gate) & PN junction capacitance of MPs drain (source)
When clock (CK ) goes high, MP is turned ON & allows Vin to be placed on
capacitor Cx
When CK goes low, MP is turned OFF, trapping charge on Cx
Operation for 1 or 0:
If Vin is high (say V
OH
), then MP will allow current to flow into Cx, charging it
up to Vdd Vtn (assume CK up level Vdd)
If Vin is low (say GND), then MP will allow current to flow out of Cx, If Vin is low (say GND), then MP will allow current to flow out of Cx,
discharging it to GND
Due to leakage from drain (source) of MP, Cx can only retain charge Q for a
given period of time (called soft node)
If MP is NMOS, Cx will discharge to GND
If MP is PMOS, Cx will discharge to VDD
If MP is a TG, Cx could discharge in either direction
62
Pass Transistor Logic with PMOS Pull-Up
For reduction of device count and area an NMOS version with PMOS pull-up
can also be useful (kind of pseudo NMOS)
63
Pass Transistors
Vdd-VTN Vdd-VTN
Vdd-VTN
Vdd-2VTN
Vdd-3VTN
NMOS Pass Gate
Configuration
64
|VTP| |VTP|
|VTP|
2|VTP|
3|VTP|
PMOS Pass Gate
Configuration
Complexity of CMOS pass-gate logic can be reduced by dropping PMOS
transistors & using only NMOS pass transistors called CPL
CMOS inverters must be used periodically to recover the full V
DD
level since NMOS
pass transistors will provide V
OH
of VDD V
Tn
in some cases
CPL circuit requires complementary inputs & generates complementary outputs
to pass on to next CPL stage
Complimentary Pass Transistor Logic (CPL)
F
Pass-Transistor
Network
A
A
B
B
B B
A
A F=A
F Pass-Transistor
Network
A
A
B
B
Inverse
B
S
S
S
S
A
B
A
Y
Y L
L
A
A
A
F=A
F=A
65
Boolean Function CPL
Pass-transistor logic used to design NOR, XOR, NAND, AND & OR gates
depending upon P1-P4 inputs:
P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR
P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR
P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND
P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND
P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR
Circuit can be operated with clocked P pull-up device or inverter-based latch
Output inverter provides F(A,B) and can be used to latch node F high (-F low)
66
Utilizes CMOS transmission gate to perform logic
Logical inputs may be applied to both device gates & source/drain regions
Limited number of Pass Gates may be ganged in series before clocked Pull-
up (or pull-down) stage is required
(a) and (b) show simple XNOR implementation:
If A is high, B is passed through the gate to the output
If A is low, -B is passed through the gate to the output
(c) shows XNOR circuit including a cross-coupled input with P pull-up devices
which does not require inverted inputs
CPL Using TG Logic
67
Domino Logic
Dynamic stage with inverting static gate called domino gate
Design method for glitch-free cascading of NMOS logic
Only one clock signal required
Attractive for high-speed circuits (1.52x faster than static CMOS)
Adding levels restorer reduces leakage & charge redistribution problems
Small load capacity to be driven by logic
Widely used in high-performance microprocessors
But many challenges: Noise, Leakage Charge Sharing, Monotonicity
68
M
p
M
e
V
DD
PDN

In
1
In
2
In
3
Out1

M
p
M
e
V
DD
PDN

In
4

Out2
M
r
V
DD
Static Inverter
A
W

B C
X Y Z
domino AND
dynamic
NAND
static
inverter
Domino CMOS Logic
Domino logic consist of precharge/evaluation block & output inverter
Each stage is driven by (Precharge =0 & Evaluation = 1)
Precharge Phase: Gate output is precharged to logic 1 & inverter output is going
to logic 0. Logic transmission errors are avoided by providing logic 0 at inverter
output (avoiding discharge of next logic stage)
Evaluation Phase: Inverter output stays according to actual input values at logic
0 or is set to logic 1. The correct result signal is provided at end of domino
cascade after stabilization of all stages
69
AND gate
Cascaded domino logic
Domino Logic
Problem with faulty discharge of pre-charged nodes in dynamic logic circuits can
be solved by placing an inverter in series with output of each gate
All inputs to N logic blocks will be at zero volts during pre-charge & will
remain at zero until evaluation stage has logic inputs to discharge pre-
charged node PZ
In (b) a weak P device compensates for charge loss due to charge sharing &
leakage at low frequency clock operation
In (c ) weak P device can be used to latch output high
70
Mixing Domino Logic with Static Logic
We can add even number of static inverting logic gates after Domino logic stage
prior to next Domino logic stage
Even number of inverting stages guarantees that inputs to second Domino
logic stage experience only 0-to-1 transitions
In cascaded Domino logic structure, evaluation of each stage ripples through
cascaded stages similar to a chain of Dominos
Evaluate cycle must be sufficient duration to allow all cascaded logic stages
(between latches) to complete their evaluation process within clock
evaluation interval
71
NP Domino/NORA Logic
In dynamic logic erroneous evaluation problem is to use NP Domino
Logic/NORA logic
Alternate stages of N logic with stages of P logic:
N logic stages use true clock, normal pre-charge & evaluation phases, with
N logic tree in the pull down leg
P logic stages use a complement clock, with P logic stage tied above the
output node
During pre-charge clk is low (-clk is high) & P-logic output pre-charges to
ground while N-logic outputs pre-charge to Vdd
During evaluate clk is high (-clk is low) and both type stages go through During evaluate clk is high (-clk is low) and both type stages go through
evaluation; N-logic tree logically evaluates to ground while P-logic tree
logically evaluates to Vdd
Inverter outputs can be used to feed other N-blocks from N-blocks, or to feed
other P-blocks from P-blocks
72
M
p
M
e
V
DD
PDN

In
1
In
2
In
3

M
e
M
p
V
DD
PUN

In
4

Out1
Out2
Only 10 transitions allowed at inputs of PUN
NP-CMOS Logic
V
DD

B
1

A
1
V
DD

A
1
B
1
C
i2
V
DD

B
1
C
i1
B
1

A
1
A
1
V
DD

S
1
C
i1
73
V
DD

C
i0
A
0
B
0
B
0

A
0
C
i1
C
i0
C
i0
B
0
A
0
B
0
S
0
A
0
V
DD

V
DD

Carry Path
NP CMOS Adder NP CMOS Adder
NORA Logic
NO Raace:
Signal race can arise, when both TG conduct at same time. If new input
from TG1 reaches the input of TG2 while TG2 is still transmitting the
output, output information will be lost. Imperfect TG synchronization occurs
because of normal transition intervals or clock skew
NORA is very insensitive to clock delay
One clock signal & inverted clock signal with short slopes rise times are
sufficient
No inverter is needed b/w logic stages due to use of n-& p-type blocks
Last stage is a clocked inverter, a C2MOS latch
74
Race Problem
Pipelined NORA Logic
With pipelined NORA CMOS logic design
One can alternate N and P stages between
C
2
MOS latches where high is used for
evaluation as shown in (a)
Or, one can alternate N and P stages similarly
between C
2
MOS latches with high used for
evaluation as in (b)
sections may be alternately cascaded with
sections as shown in (c)
During the evaluation phase, logic ripples through During the evaluation phase, logic ripples through
each stage in succession up to next C
2
MOS latch
75
NORA Logic
During low ( high), each stage pre-charges
N logic stages pre-charge to Vdd; P logic stages pre-charge to GND
When goes high ( low), each stage enters the evaluation phase
N logic evaluates to GND; P logic stages evaluate to Vdd
All NMOS & PMOS stages evaluate one after another in succession, as in
Domino logic
Logic below:
Stage 1 is X = (A B)
Stage 2 is G = X + Y
Stage 3 is Z = (F G + H) Stage 3 is Z = (F G + H)
76
Single-Phase NP Dynamic Logic Structures
Combines NP Domino logic sections with C
2
MOS latch
n-logic block can drive p-logic block or another n-logic block with a static inverter
Similarly for a p-logic block
Must end in a C
2
MOS latch
Clk logic: (a) prechrg on clk=0, eval clk=1
-Clk logic: (b) pre on clk=1, eval on clk=0
Clk logic can feed clk logic & vice-versa
Can mix static logic with NP domino logic
Rules to avoid race conditions:
During precharge, logic blocks are OFF During precharge, logic blocks are OFF
During eval, internal inputs make only one transition
Pipeline design:
Even # of inversions between C
2
MOS, or
at least 1 dynamic stage and even # inversions prior to it
77
f
input s
Y
2/3
Y
2/3
Pseudo-NMOS Logic
Consists of a single PMOS load per gate & NMOS PDN
It is a ratio circuit where DC current flows when N PDN is conducting
Must design the ratio of N devices W/L to P load device W/L so that when N pull
down leg with max resistance is conducting, output is at a sufficiently low V
OL
Needs ratioed devices
Dissipates static power, when PDN is ON
Provides a method of emulating NMOS circuits in CMOS
Reduced noise margin
Criteria for Psuedo NMOS Logic
V
DD
A B C D
F
C
L
Inverter NAND2
NOR2
4/3
2/3
A
Y
8/3
8/3
B
A
Y
A B
4/3 4/3
Y
78
Criteria for Psuedo NMOS Logic
Fully-complementary CMOS logic
Immune to noise
Virtually zero static power
Many stages required for high fan-in functions
Pseudo nMOS logic
Good for high fan-in Nor function
ROM
PLA
Adder carry look-ahead
Zipper Dynamic Logic
Zipper CMOS logic is for improving charge leakage & charge sharing problems
Pre-charge transistors receive a slightly modified clock where clock pulse
(during pre-charge off time) holds the pre-charge transistor at weak conduction
in order to provide a trickle pre-charge current during the evaluation phase
PMOS pre-charge transistor gates are held at Vdd - |Vtp|
NMOS pre-charge transistor gates are held at Vtn above GND
79
Source-Follower Pull-up Logic (SFPL)
SFPL is a variation on pseudo-NMOS whereby load device is an N pull-down
transistor & N source-follower pull-ups are used on inputs
N pull-up transistors can be small limiting input capacitance
N transistors are also duplicated as pull-down devices in order to improve
fall time
Rise time is determined by P1 inverter pull-up transistor when all low inputs
SFPL is useful for high fan-in NOR logic gates
80
Ratioed Logic
V
DD
V
DD
V
DD
Ratioed logic is an attempt to reduce number of transistors required to
implement a given function, often at cost reduced robustness & extra power
dissipation
Purpose of PUN is to provide conditional path b/w Vdd & output when PDN is
OFF. In ratioed logic, entire PUN is replaced with load device that pulls up the
output for high output
Psuedo NMOS gate reduced number of transistors (N+1) Vs. N
81
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
V
SS
In
1
In
2
In
3
F
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Resistive
Depletion
Load
PMOS
Load
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
V
T
< 0
Goal: to reduce the number of devices over complementary CMOS
Differential Cascode Voltage Switch Logic
(DCVSL)
V
DD
Out
V
DD
Out
M1 M2
B B
B B
Out
Out
82
V
SS
PDN1
V
SS
PDN2
A
A
B
B
Even Better Noise Immunity/Density
B
A A
B
B B
XOR-NXOR gate
CMOS Circuit Styles - Summary
83
On-Chip Internal V
DD
Generator
CMOS and Pseudo-NMOS circuitry often require an internally-generated Vdd
supply voltage or a bias voltage (above Vss) for on-chip use
Requirements:
track supply voltages Vdd and Vss
temperature compensation
highly regulated
de-coupled from power supply noise with use of on-chip capacitance
Circuit below utilizes a reference voltage generator comprised of series-
connected saturated P devices feeding a current mirror to obtain Internal V
DD
<
External V External V
DD
Clocked device P1 can be used to provide low power (sleep) mode with
reduced Internal V
DD
84
The Foot
What if Pull-Down network is ON during precharge?
Use series evaluation transistor to prevent fight
A
Y

foot
precharge
transistor
1
1
A
Y
2
2
1
B
A
Y
A B
1 1
1
g
d
= 1/3
p
d
= 2/3
g
d
= 2/3
g
d
= 1/3
p = 3/3
Y

Unfooted
85

Y
inputs

Y
inputs
Footed
Unfooted
f
f
d
Inverter
NAND2
NOR2
p
d
= 2/3
d
p
d
= 3/3
d
p
d
= 3/3
2
1
A
Y
3
3
1
B
A
Y
A B
2 2
1
g
d
= 2/3
p
d
= 3/3
g
d
= 3/3
p = 4/3
g
d
= 2/3
p
d
= 5/3
Y

Footed
3
2
2
Monotonicity
Dynamic gates require monotonically rising inputs during evaluation
0 -> 0
0 -> 1
1 -> 1
But not 1 -> 0
A
X

Y
Precharge Evaluate
X
Precharge
A=1
Y
A

Monotonicity Woes
86
Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicity
during evaluation
But dynamic gates produce monotonically falling outputs during evaluation
Illegal for one dynamic gate to drive another!
A
X

Y
PrechargeEvaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
Leakage & Charge Sharing
Dynamic node floats high during evaluation
Transistors are leaky (I
OFF
0)
Dynamic value will leak away over time
Formerly miliseconds, now nanoseconds!
Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
A

H
2
2
1 k
X
Y
weak keeper
Charge sharing
87
Charge sharing
Dynamic gates suffer from charge sharing
B = 0
A
Y

x
C
x
C
Y
A

x
Y
Charge sharing noise
Y
x Y DD
x Y
C
V V V
C C
= =
+
Secondary Precharge
Solution: add secondary precharge transistors
Typically need to precharge every other node
Big load capacitance C
Y
helps as well
A
Y

secondary
precharge
transistor
88
B
A
x
Principle of CMOS Memory
LD=1 QD Q D
LD=0 store current state
89
Dynamic Flip0Flops:Pseudo 2-Phase Clocking
90
Clock skew
Slow Clock Edges
Pseudo 2-Phase Latch
Charge distribution problem in (b)
Reduced Transistor Count Latch
With high impedance sustainer transistors
91
Dynamic D-Latches
Dynamic D-Latches
92
Pseudo 2-Phase dynamic logic
Pseudo 2-Phase domino logic
2-Phase Memory
93
2-Phase Static D flip-flops
2-Phase Static D flip-flops
Static Memory
Static D flip-flop with set and reset
94
Latch
These sequential devices differ in way their outputs are changed:
Output of a latch changes independent of a clocking signal
Output of flipflop changes at specific times determined by clocking signal
SR Latch based on NOR gate
S input sets Q output to 1 while R reset it to 0
When R=S=0 then output keeps previous value
When R=S=1 then Q=Q=0, and the latch may
go to an unpredictable next state
SR latch based on NAND gates
95
SR latch based on NAND gates
S input sets Q output to 1 while R reset it to 0
When R=S=1 then output keeps previous
value
When R=S=1 then Q=Q=1, & latch may go to
an unpredictable next state
D latch
This latch eliminates the problem that occurs in SR
latch when R=S=0
C is an enable input:
When C=1 then output follows the input D &
latch is said to be open
When C=0 then output retains its last value &
latch is said to be closed
Flip Flop
D flip-flop is made out of two D latches. First latch is master, & second slave
When C
k
= 0, master is open & slave is closed. Q
m
& D
s
follow D
m
When C
k
= 1 master is closed, slave is open & Q
m
is transferred to Q
s
Note: Q
s
does not change because master latch is closed leaving Q
m
fixed
96
J-K flip-flop is similar to S-R flip-flop. Difference arises when J & K are asserted
simultaneously. In this situation output of J-K flip-flop inverts its current state
Flip-Flop
T flip-flop
When input T = 0, output Q retain its previous value
When input T = 1, output Q inverts on every tick of clock
When inputs J & K of a J-K flip-flop are connected together, J-K flip-flop will
behave like a T flip-flop
97
Flip-flops/Latches
Flip-flops occupy a special place in conventional digital design
Always Dynamic Behavior
Allow time coherence across large parts of the circuit
Preserve data across synchronization boundaries
Inherently asynchronous design
98
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
Transparent latch or level-sensitive latch
CLK
D Q
L
a
t
c
hD
CLK
CLK = 1
D Q
Q
CLK = 0
D
Q
Q
99
L
a
t
c
h
Q
Multiplexer chooses D or old Q
1
0
D
CLK
Q
CLK
CLK
CLK
CLK
D Q Q
Q
CLK = 0
D Latch Operation
Advanced Latches
100
Tri-state based static Latch
Modified Svensson Latch 21064
D Flip-flop Design
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop,
master-slave flip-flop
F
l
o
p
CLK
D Q
D
CLK
Q
CLK = 1
D
CLK = 0
Q
D
QM
QM
Q
101
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
L
a
t
c
h
L
a
t
c
h
D Q
QM
CLK
CLK
Built from master and slave D latches
D
CLK
Q
D-F/F Operation
Sense Amplifier-Based Flip-Flop
First stage is unchanged sense amplifier
Second stage is sized to provide
maximum switching speed
102
Driver transistors are large
Keeper transistors are small
& disengaged during transitions
Asymmetric Read/Write Ports
103
Multi porting
Dynamic Latches with a Single Clock
Dynamic latches eliminate dc feedback leg by storing data on gate capacitance
of inverter (or logic gate) and switching charge in or out with a transmission
gate
Minimum frequency operation is 50-100 KHz, not to lose data due to junction or gate
leakage from the node
Can be clocked at high frequency since very little delay in latch elements
Examples:
(a) or (b) show simple transmission gate latch concept
(c ) tri-state inverter dynamic latch holds data on gate when clk is high
(d) and (e) dynamic D register
104
Dynamic Registers with two Phase Clocks
Dynamic register with pass gates & two phase
clocking is shown
Clocks phi1 and phi2 are non-overlapping
When phi1 is high & phi2 is zero,
1
st
pass gate closed & D data charges
gate capacitance C1 of 1
st
inverter
2
nd
pass gate is open trapping prior
charge on C2
When phi1 is low and phi2 is high, When phi1 is low and phi2 is high,
1
st
pass gate opens trapping D data on
C1
2
nd
pass gate closes allowing C2 to
charge with inverted D data
If clock skew or sloppy rise/fall time clock
buffers cause overlap of phi1 and phi2 clocks,
Both pass gates can be closed at the same
time causing mixing of old and new data
and therefore loss of data integrity!
105
Two Phase Dynamic Registers (Compact Form)
Compact implementation of of two phase
dynamic registers using a tri-state buffer form
Transmission gate & inverter integrated
into one circuit
Two versions:
Pass devices closest to output
Inverter devices closest to output
Two phase dynamic registers & logic is often Two phase dynamic registers & logic is often
preferred over single phase because:
Due to finite rise/fall times, CLK & CLK are
not truly non-overlapping
Clock skew often is a problem due to CLK
is usually generated from CLK using an
inverter circuit & also due to practical
problem of distributing clock lines without
any skew
106
Dynamic Shift Registers with Enhancement Load
Dynamic shift register implemented with a
technique named ratioed dynamic logic.
1 and 2 are non-overlapping clocks
When 1 is high, Cin1 charges to Vdd Vt if Vin
is high or to GND if Vin is low
When 1 drops and 2 comes up, the input data
is trapped on Cin1 and yields a logic output on
Cout1 which is transferred to Cin2
When 2 drops and 1 comes up again, the logic
output on Cout1 is trapped on Cin2, which yields
a logic output on Cout2, which is transferred to a logic output on Cout2, which is transferred to
Cin3, etc.
To avoid losing too much voltage on the logic high
level, Cout
n
>> Cin
n+1
is desired
Each inverter must be ratioed to achieve a
desired V
OL
(e.g. when 2 is high on 1
st
inv)
Dynamic shift register is a ratioless dynamic
logic circuit
When 2 is high transferring data to stage 2, 1
has already turned off the stage 1 load transistor,
allowing a V
OL
= 0 to be obtained without a ratio
condition between load and driver transistors.
107