EE 200 Project Designing a simple coffee vending machine

Louis van der Elst, April 7, 2013

Designing and Implementing a Coffee Vending Machine Finite State Machine

Part 1: Design and Simulation

Block Diagram 1. State Table:

Moore Finite State Machine

Present State Input Next State Output QA QB N D DA DB C 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 1 X X 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 1 X X 0 1 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 X X 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 X X 1 2. Karnaugh Maps, flip-flop Inputs Equations and System Output Equation: QAQB 00 01 11 10 00 1 1 01 1 1 1 1 ND 11 X X X X 10 1 1 1 DA QAQB 00 01 11 10 00 1 1 01 1 1 1 ND 11 X X X X 10 1 1 1 DB QAQB 00 01 11 10 00 1 01 1 ND 11 1 10 1 C

3. Flip-flop Inputs Equations and System Output Equation and its conversion to NAND Gates: DA = QA + D + NQB = (QA + D + NQB) = (QAD(NQB)) DB = NQB + NQA + DQA + NQB = (NQB + NQA + DQA + NQB) = ((NQB)(NQA)(DQA)(NQB))
1

C = (QAQB) = ((QAQB)) = (QAQB)

EE 200 Project Designing a simple coffee vending machine

Louis van der Elst, April 7, 2013

4. Major components to be used: Eight 2-bit NAND Gates: NQB, NQB, NQA, DQA, NQB, N, D, and QAQB Two 4-bit NAND Gates: QAD(NQB) and (NQB)(NQA)(DQA)(NQB) Two D-Type Flip Flop: DA and DB 5. Realizing Logic Equations:

Logic Circuit Diagram using NAND Gates and two Flip Flops

EE 200 Project Designing a simple coffee vending machine

Louis van der Elst, April 7, 2013

Part 2: Testing and Implementing

FSM Components to be used 1. Verifying Circuit Design with Multisim:

Design Simulation Running Successfully

EE 200 Project Designing a simple coffee vending machine

Louis van der Elst, April 7, 2013

Multisim Convergence Assistant Summary Report Convergence Assistant Summary Report Outcome: The simulation error was corrected successfully. Changes Made: -Shunt resistance from analog nodes to ground (RSHUNT) was changed to 100000000 Multisim Convergence Assistant Log Step 1: Verifying Error Scenario ...completed. Step 2: Setting parameter Integration Method (METHOD) to Gear Simulating... ...completed. Simulation error still occurs. Step 3: Setting parameter Initial Conditions to Set To Zero Simulating... ...completed. Simulation error still occurs. Step 4: Setting parameter Maximum Timestep (TMAX) to 1.0000e-004 Simulating... ...completed. Simulation error still occurs. Step 5: Setting parameter Maximum Timestep (TMAX) to 1.0000e-003 Simulating... ...completed. Simulation error still occurs. Step 6: Setting parameter Relative error tolerance (RELTOL) to 1.0000e-002 Simulating... ...completed. Simulation error still occurs. Step 7: Setting parameter Shunt resistance from analog nodes to ground (RSHUNT) to 1000000000 Simulating... ...completed. Simulation error still occurs. Step 8: Setting parameter Shunt resistance from analog nodes to ground (RSHUNT) to 100000000 Simulating... ...completed. Simulation error fixed. Step 9: Attempting rollback of Initial Conditions to Automatically Determine Simulating... ...Rollback successful. Step 10: Attempting rollback of Maximum Timestep (TMAX) to 1.0000e-005 Simulating... ...Rollback successful. Step 11: Attempting rollback of Relative error tolerance (RELTOL) to 1.0000e-003 Simulating... ...Rollback successful. Step 12: Attempting rollback of Shunt resistance from analog nodes to ground (RSHUNT) to 1.0000e+012 Simulating... ...Error recurred - rollback unsuccessful. Step 13: Restoring value of Shunt resistance from analog nodes to ground (RSHUNT) to 100000000 Step 14: Attempting rollback of Integration Method (METHOD) to Trapezoidal Simulating... ...Rollback successful. Convergence Assistant completed successfully.

Errors Encountered and solved during experimentation and verification of the simulated design

EE 200 Project Designing a simple coffee vending machine

Louis van der Elst, April 7, 2013

2. Implementing Circuit on Breadboard:

Dual 4-input NAND

Quad 2-input NAND

Dual D-Type Flip Flop

Programmable Timer [] Breadboard implementation successfully working From left to right: SPST tactile switch of inputs nickels (N), dimes (D), and reset (R). Column 1, from top to bottom: Quad 2-input NAND Gate 1, Quad 2-input NAND Gate 2, and Programmable Timer of input clock (CLK, with RS = 56K, RTC = 27K, and CTC = 0.01F) Column 2: Dual 4-input NAND Gate, and red LED of output coffee (C) Column 3: Dual D-Type Flip Flop [] Output C = 0 [] Output C = 1