IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO.
5, JUNE 1997
The MainStreetXpress Core Services
Node—A Versatile ATM Switch
Architecture for the Full Service Network
Erwin P. Rathgeb, Wolfgang Fischer, Member, IEEE,
Christian Hinterberger, Eugen Wallmeier, and Regina Wille-Fier
Abstract— Switching systems based on the ATM principle
have outgrown the experimental stage, and are already used
today in private and corporate networks, as well as in public
wide area networks to provide regular service. ATM has the
inherent ability to provide a common basis for transmission and
switching functionality in both local and wide area networks.
With the potential to support all services available today as
well as those envisaged for the future, ATM holds a strong
promise for network operators and end customers. To fully
exploit this potential, ATM switch architectures are required
which provide versatility and modularity in supporting services
and protocols, independent scalability of data throughput and
control performance over a wide range, and also reliability
features adaptable to the respective application scenario. This
paper describes in some detail how the MainStreetXpress core
services node, which has evolved from the prototype described
earlier [5] to a mature central office ATM switch, addresses these
issues and provides a future-proof architecture incorporating all
of the features required in the B-ISDN era.
Index Terms—Asynchronous transfer mode, broad-band com-
munication, redundancy, switching systems.
I. INTRODUCTION: NETWORK CONCEPTS
T HE introduction of ATM in wide area networks is cur-
rently driven by four main application areas.
1) High-Speed Interconnection of Local Area Networks
(LAN): For this application area, features for interwork-
ing with existing data networks and services, as well as
mechanisms for efficient multiplexing of bursty traffic
streams have to be provided by the ATM multiservice
network. To enhance the support of the ATM transport
network for this application, a variety of mechanisms
are currently being discussed and specified. Examples
are LAN emulation (LANE [1]) and “multiprotocol over
ATM” (MPOA [2]), as well as the “classical IP over
ATM” approach [9].
2) Integrated Voice and Data Transport for New Alternative
Service Providers: Since the transmission links con-
necting local networks of these providers will often
have to be leased from established network providers,
an integrated transport technology is required which
allows us to optimally utilize these resources. With
Manuscript received May 1, 1996; revised December 1, 1996.
The authors are with the Public Communication Networks Group, Broad-
band Networks, Siemens AG, D-81359 München, Germany.
Publisher Item Identifier S 0733-8716(97)03378-7.
0733–8716/97$10.00  1997 IEEE
795
respect to ATM-based solutions, statistical multiplexing
of packetized voice and data in combination with voice
compression and intelligent call-routing features will be
required.
3) Network Consolidation: Providers of existing wide-area
networks introduce ATM as the basis for a future broad-
band ISDN, which allows the consolidation of the ex-
isting networks in the long term. Such an application
scenario requires intensive interworking with the exist-
ing narrow-band networks with adaptation functions for
the user channels and feature transparent interworking
between the signaling systems used.
4) Entertainment-Oriented Interactive Video and Multime-
dia Services for Residential Customers: In the medium
term, this application area is expected to grow sig-
nificantly. In this area, cost-effective solutions for the
customer access are the key issue. In the core net-
work, high-throughput ATM switches able to support
the highly asymmetrical traffic streams in an efficient
way are required to accommodate an adequate number
of subscribers per switch.
If an ATM-based multiservice platform is targeted, the ATM
systems used in wide area networks have to meet the full
spectrum of requirements for the application areas mentioned
above. In many cases, these requirements differ substantially
from those defined for local area networks.
• Reliability and availability of broad-band wide area net-
works—which are public networks in many cases—are
oriented towards the established values defined for the
public telephone and leased line networks. These re-
quirements imply that for the architecture of the systems
which are used in these networks, redundancy of central
subsystems and of interfaces is absolutely mandatory.
• The wide spectrum of applications of these sys-
tems—from small access nodes with a few interfaces and
a throughput of less than 10 Gbit/s up to large central
office switches with several thousands of interfaces and
a throughput of much more than 100 Gbit/s—require
architectures which allow a high level of scalability.
This scalability, however, relates not only to the data
throughput of the ATM switching network, but also to
the processing power of the switching processors used.
• Data and packetized voice with silence suppression would
cause a huge waste of resources if they were trans-
796 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO. 5, JUNE 1997

ported through wide area networks employing peak bit-

rate allocation. Statistical multiplexing of these traffic
types—which is state of the art in all existing data
networks—is a prerequisite for economic use of trans-
mission capacity also in ATM networks. When pro-
viding statistical multiplexing capabilities for real-time
services coded with variable bit rates (voice, video), no
large multiplexing buffers can be used in order not to
violate the stringent delay objectives. Therefore, only
connection admission procedures taking into account the
bursty nature of these traffic types can be applied to
achieve statistical gain without excessive delays. For less
delay sensitive (data) services, large buffers have to be
provided in the switching nodes, along with appropriate
non-FIFO scheduling strategies working at very high
speeds. These scheduling mechanisms have to ensure
fairness and isolation between traffic streams originating
from individual users, who—in contrast to the users
in local area networks—cannot be assumed to behave
cooperatively. In addition, delay priority has to be given
to the real-time services within these mechanisms. In
particular, the support of the new “available bit rate”
(ABR) service category—or “ATM transfer capability”
in ITU-T terms—and the “unspecified bit rate” (UBR)
service category defined by the ATM Forum requires
these large buffers and the corresponding scheduling and
priority mechanisms.
• In the foreseeable future, only a fairly small percentage
of end systems is expected to provide ATM interfaces.
Most terminals instead will be equipped with the interface
types already in use today, e.g., PDH leased lines, Frame Fig. 1. MainStreetXpress core services node architecture.
Relay, SMDS/CBDS, and X.25. In order to connect these
systems with their service-specific interfaces to ATM • the fully redundant ATM switching network (ASN) con-
networks, interface adaptation has to be performed by sisting of ATM multiplexers (AMX) and the ASN core to
the ATM nodes. Beyond the pure interface adaptation, perform cell multiplexing, concentration, and cell switch-
processing of the higher layer service-specific functions ing functions;
and protocols also has to be provided. In this context, • the scalable, fully redundant control cluster for central
the handling of Internet-specific functions (e.g., routing,
control and termination of signaling protocols;
address conversion, protocol handling, etc.) [6] is of
• echo cancellation circuits (ECC) for 64 kbit/s voice
primary importance because the efficient support of the
connections;
IP-based Internet applications will be a prerequisite for
• statistical multiplexing units (SMU) providing large cell
the successful introduction and acceptance of ATM-based
buffers, non-FIFO cell scheduling, delay priority mecha-
multiservice network infrastructures.
nisms, and support of ABR and UBR protocols to support
The following sections will provide insight into the archi- statistical multiplexing for nonreal time variable bit-rate
tecture of the Siemens MainStreetXpress core services node connections.
which has been designed with all of the requirements men-
tioned above in mind. The LIC’s connected to one AMX are physically combined
with this AMX in a so-called access unit (AU) shelf. The
AU’s as well as the LIC’s are designed such that, in addition
II. THE SYSTEM ARCHITECTURE to a normal simplex configuration, line and board redundancy
schemes also can be supported if required by the application
scenario.
A. System Overview In between the functional blocks shown in Fig. 1, a common
The main components of the system shown in Fig. 1 are cell-based interface is used, allowing for a flexible configura-
as follows: tion of the system, e.g.,
• line interface circuits (LIC) of various types to connect • all LIC types can be mixed freely within one AU shelf to
external interfaces (subscriber lines, trunks) and to per- provide optimum utilization of the bandwidth available
form ATM layer and service-specific functions; at one AMX;
RATHGEB et al.: MAINSTREETXPRESS 797

• ECC’s can be pooled together in separate shelves (ECC

cluster) or can be plugged into regular AU’s according to
the requirements of a specific configuration;
• the AMX can be omitted for high-rate interfaces (2.4
Gbit/s) not requiring multiplexing toward the ASN;
• the SMU can be omitted if it is not required for certain
interfaces only carrying real-time critical traffic.

B. ATM Switching Network (ASN)

The ASN consists of AMX’s physically located in the AU
shelves and of the central ASN core. The AMX’s provide a
multiplexing and concentration stage to allow for efficient use
of the ASN core. The function of the ASN is to switch cells
received from the ingress side LIC’s to the appropriate egress
side LIC’s, to specific server-type boards, e.g., ECC’s, or to
the control cluster by using the routing information contained
in the internal cell header.
The AMX is connected to the ASN core via unidirec-
tional cables with a granularity of four STM-1 equivalents.
Therefore, the AMX can be connected to the ASN core with
a variable number of STM-1 equivalent links to provide a
flexible concentration ratio. Due to the fact that the cabling
is unidirectional, the interconnection between the AMX and
ASN core can also be asymmetrical to support applications
with highly asymmetrical bit-rate characteristics, e.g., for
interactive video services.
The AMX includes a peripheral control platform (PCP) to
control and supervise the switching functions, as well as a
clock generation platform and power supply units. It should
be noted here that the PCP is a universal processing platform
consisting of a processor with all required processor periphery.
All PCP software is stored in Flash-PROM memories to make
the PCP fully software loadable, and thus to eliminate the need
for physical access to the PCP for upgrades. Also, part of the
PCP is an ASIC processing the lower levels of the internal
control communication protocols to offload this dynamic load
from the peripheral processor. The PCP with a common basic
software is used on all LIC’s, ECC’s, SMU’s, and in the AMX
and ASN core, together with some specific software extensions
for the different applications.
The ASN core is strictly nonblocking in the sense that—if
a properly working connection acceptance control (CAC)
function ensures that the destination output link is not over-
loaded—any cell stream arriving at an arbitrary ASN core
input port can be routed to any arbitrary ASN core output
port irrespective of the traffic at the other ports without cell
losses exceeding the specified limits. This means that there
are no additional restrictions nor is any additional bandwidth
management necessary within the ASN core. The ASN core
can be scaled from a minimum configuration with a total
throughput of 5 Gbit/s up to configurations with more than
1 Tbit/s with the same switching network structure.
The ASN core as well as the AMX’s are constructed by
using switching elements (SE) which provide inputs and
outputs (SE 2 ). The ASN core has a “funnel” structure
with stages such that a single funnel represents a strictly
nonblocking switch fabric module with 2 2 inputs and
Fig. 2. 20 Gbit/s ASN core.
outputs. By connecting funnels in parallel to all the inputs,
a quadratic switch fabric can be constructed. Fig. 2 shows as
an example the structure of a 20 Gbit/s ASN core built up of
switching elements (SE 32/16) with 32 inputs and 16 outputs,
each running at 207 Mbit/s, and thus able to transport the
traffic load of one external STM-1 interface per port.
The main properties of the funnel switch fabric are the
following.
• It is strictly nonblocking, i.e., connections can be ac-
cepted, and the bit rate of any existing connection can
be modified (increased) without any restriction as long as
sufficient bandwidth is available at the respective input
and output ports.
• It has only a single path between any input/output pair
(single path network), i.e., no path hunting is necessary,
and the cell sequence integrity is preserved.
• The performance is practically equivalent to the per-
formance of a single-stage output-buffered switch (ideal
switch) irrespective of the number of funnel stages.
The input/output ports of the ASN core can be grouped
together and operated as bundles with a capacity of 2, 4, 8, or
16 STM-1 equivalents which are cyclically fed by a common
queue. As the cells on the links of a bundle are transmitted
staggered against each other, it can be guaranteed that the
cell sequence within the bundle is preserved. By operating all
groups of internal links connected to the same receiving device
(switching element, LIC) as a single higher bit rate ATM pipe,
any bandwidth loss due to fragmentation is avoided. Due to
the fact that within the ASN core only bundles of 16 links are
used (STM-16 equivalent capacity), interfaces and connections
with bit rates up to 2.4 Gbit/s can be supported without any
restrictions and without the need for resequencing. The SE’s
are based on an extension of the “Sigma” concept described in
798 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO. 5, JUNE 1997
Fig. 3. Switching element with Sigma architecture.
[5] featuring a central buffer architecture with logical output
queues for optimum performance. A block diagram of the
Sigma SE is shown in Fig. 3. Cells received on any of the
input links are converted to a parallel format after phase
alignment. They are then stored in an empty location of the
shared cell memory which is organized as random access
memory (RAM). The internal routing tags are forwarded to
a control block. For point-to-point connections, the complete
routing information for the ASN is added to the cell at the
ingress LIC, and the control block makes the routing decision
based on the analysis of the relevant parts of the routing tag
(self-routing principle).
The SE’s are also able to support ATM layer multicast
connections by copying arriving cells and reemitting the
copies on an arbitrary subset of their outputs. For multicast
connections, a multicast routing address (MCRA) is added
to the cell at the ingress LIC instead of the normal routing
information. This identifier is used by the SE’s to address
an SE-specific multicast lookup table containing a bit map
identifying the outputs to which copies of a specific cell have
to be transmitted. With this multicast mechanism, there is no
restriction to the fan-out of any multicast connection within
the ASN.
Depending on the result of the evaluation of the routing tags,
a pointer to the location of the cell in the central cell memory is
queued in one or several logical output queues, which control
the reemission order of the cells on the outputs. It should be
mentioned that the cell itself is stored physically only once in
the central cell buffer; only the relevant information is stored in
several logical output queues for multicast connections. Once
a cell copy has been transmitted on each destination output, the
cell is physically removed from the buffer. If the SE outputs
are operated in bundle mode, only one logical output queue
per bundle is maintained.
With respect to the cell-routing function, the SE’s operate in
different modes depending on their location within the ASN.
The SE’s in the first stage of a funnel filter out the cells
destined for the outputs connected to the respective funnel and
multiplex them onto their outputs. The SE’s in the intermediate
funnel stages—as well as the SE’s in the AMX’s on the ingress
side—only perform multiplexing, whereas the SE’s in the last
funnel stage and in the egress side AMX’s perform the actual
routing functions.
The SE’s also support the CLP mechanism of the ATM
cell header. The cell loss priorities are implemented by a
partial buffer-sharing mechanism. With this mechanism, only
high priority cells are admitted to the cell
buffer once the fill level exceeds a configurable threshold. In
addition, a fairness management mechanism is implemented.
This mechanism allows to specify and control a limit for the
number of buffer spaces in the central cell memory which
can be occupied by a single logical output queue. With this
fairness mechanism, a single, highly loaded output queue can
be prevented from occupying the complete shared buffer space.
Larger switch fabrics have the same basic funnel structure
and are provided by using the next generation of switching
elements (SE G16/8) with eight times higher throughput (16
inputs/8 outputs at 3.3 Gbit/s port data rate). These SE’s
are designed by using 0.5 m technology and are already
available. They provide a functionality equivalent to that of
the SE 32/16, and allow us to realize, e.g., a 40 Gbit/s switch
fabric on a single board. A 160 Gbit/s switching network can
be built with a three-stage funnel equivalent to the structure
shown in Fig. 2, whereby a fully redundant configuration fits
into one standard rack. To avoid the limitations of the electrical
cabling, optical links are used to interconnect the various ASN
boards. By extending the structure to more than three stages
with each additional stage doubling the switching network
throughput, funnel structures with a throughput of more than 1
Tbit/s can be constructed with the SE G16/8 without reaching
technological limits. The routing field of the internal cell
format is already dimensioned to cope with the large-capacity
switching networks. Therefore, in order to allow an upgrade
of smaller systems, only specific multiplexing stages within
the ASN core have to be provided to convert from the
207 Mbit/s internal interface format used in the periphery to
the 3.3 Gbit/s format used in the large ASN core. For such an
upgrade, only the ASN core has to be replaced; all peripheral
components including AMX’s and SMU’s can be retained.
C. Line Interface Circuits (LIC’s)
The LIC’s provide connectivity of various external line
interfaces to the system. The LIC types can vary in the
interface bit rate (1.5 Mbit/s up to 2.4 Gbit/s) as well as in
the services provided (ATM cell relay, 64 kbit/s, 1.5/2
Mbit/s circuit emulation service, Frame Relay, SMDS/CBDS).
Depending on these characteristics, one or several external
RATHGEB et al.: MAINSTREETXPRESS
Fig. 4. LIC providing ATM cell relay, CES, and n 2 64 kbit/s service.
interfaces are provided on one LIC board. For each interface
type, the same hardware is used for UNI, VB5 interface, or
NNI applications.
The external interfaces may support ATM traffic and also
non-ATM traffic depending on the LIC type, whereas the
internal interface toward the ASN is purely cell based. If
the external line interface carries, e.g., CBR or Frame Relay
traffic, the respective LIC provides interworking and the ATM
adaptation layer (AAL) functionality for the corresponding
service.
All LIC types have the common overall structure shown in
Fig. 4 using an LIC providing both ATM cell relay and CBR
circuit emulation, as an example. For other services, basically
the service-dependent interworking and AAL functions are
adapted, whereas for pure cell relay interfaces, these parts are
omitted.
The LIC’s are equipped with a PCP, an on-board power
supply, and units to derive the required clocks from a centrally
distributed system clock. They also provide the possibility to
recover the transmission clock and feed it to the central system
clock generator to synchronize the ATM node to the network
clock if no separate clock signal is provided by the network.
All LIC’s can be operated in a nonredundant configuration,
but if required, the same boards and shelves can be used
to provide line/board redundancy as described in more detail
in Section III. Common to all LIC types is also the ATM
layer processing and the interface to the AMX and ASN. The
physical layer (PHY) processing is adapted to the different
transmission systems for the various interface types.
The PHY part provides both the PMD and the TC sublayer
functions, which include handling of the physical character-
istics of the external lines, framing of the transport signal,
the PHY–OAM functions and mapping of ATM cells to the
transmission frame structure. The HEC mechanism, with on-
the-fly HEC processing, is implemented for cell delineation
and header verification as specified in the relevant ITU-T
recommendation.
The ATM layer part provides the standardized functions like
VPI/VCI translation, UPC/NPC, and ATM–OAM processing
in full compliance with the relevant ITU-T and ATM Forum
specifications. In addition, it provides the system-specific
functions required for the internal operation of the switch by
799
using an extended internal cell format between the ingress
and the egress side.
In order to provide access to the full VPI/VCI range—while
keeping the RAM for connection-specific parameters to a
minimum size—a content-addressable memory (CAM) is used.
This device is a full custom design ASIC integrating an
address reduction function from a 32-bit input address (12-
bit VPI, 16-bit VCI, 4-bit port number) to a 13-bit internal
connection identifier. The address reduction is performed
prior to the access to the connection specific memory where,
e.g., UPC/NPC parameters, new VPI/VCI values, ATM traffic
measurement data, etc., are stored. The address reduction
allows direct addressing of the connection RAM with 8096
entries, which is implemented by using fast SRAM or DRAM
technology.
Full ATM layer multicast is also supported providing both
spatial and logical multicast as shown in Fig. 5. Spatial
multicast refers to copying cells within the ATM switch, and
reemitting the cell copies with individual VPI/VCI values
onto different physical egress interfaces. When using logical
multicast, the cell copies are reemitted onto the same phys-
ical interface but still carry individual VPI/VCI values. The
latter function is required if network elements not supporting
multicast are located in downstream direction.
The copy function for spatial multicast in the ASN is
performed by the switching elements as described in Section
II-B. A similar spatial multicast operation is also performed on
multiport egress LIC’s. The individual header translation for
the cell copies is performed on the egress LIC’s. The header
translation mechanism also allows us to copy cells several
times and to attach individual headers to the copies to perform
logical multicast.
All ATM layer operations on a cell are performed “on the
fly,” i.e., they are completed in less than one cell duration
on the external link. The clock frequency of the ATM layer
ASIC’s is chosen such that sufficient free clock cycles are
generated to be able to update the connection-specific table
entries in case of connection setup or release without affecting
the user data flow.
The ATM layer part is implemented by using a common
set of semicustom ASIC’s for all types of LIC’s up to STM-1
interface bit rates. This chip set can support 8192 connections
simultaneously. For the higher rate interfaces, specific ATM
layer chip sets with higher data throughput and a higher
number of simultaneous connections are provided. As the
interface between the PHY and ATM layer as well as between
the AAL and the ATM layer devices, the UTOPIA interface
as specified by the ATM Forum is used.
D. Statistical Multiplexing Unit
The FIFO cell buffers integrated in the switching fabric
and the LIC’s are dimensioned to support real-time services
which are either using constant bit rate (CBR) or real-time
variable bit-rate (VBR-rt) connections. Significantly larger
buffers do not provide additional benefit for CBR and VBR-rt
connections since quality of service requirements concerning
cell delay and cell delay variation do not allow for long
800 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO. 5, JUNE 1997
Fig. 5. Multicast connections.
queueing delays. For nonreal-time services with variable bit
rate, however, larger buffers can improve the achievable
network utilization significantly. It is a well-known fact (see
[10], [13], and [18]) that high link loads for bursty connections
with high peak cell rates (larger than a few percent of the link
rate) can only be achieved in wide area broad-band networks
if a network node is able to buffer multiple bursts for a link.
For the support of these services, the switch incorporates
large cell buffers located in the so-called statistical multi-
plexing units (SMU). For these large buffers, pure FIFO
queueing is not adequate [13]. Therefore, the SMU provides
appropriate, non-FIFO cell-scheduling mechanisms and the
additional traffic control functions necessary to operate a
network including ATM switches with large cell buffers. Delay
priority is given to the real-time connections passing through
an SMU so that the large buffers are transparent for them.
Due to the localization of all functions related to statistical
multiplexing for nonreal-time services in the SMU’s, the
architecture is modular and flexible. For switches carrying only
real-time traffic, the SMU’s can be omitted.
With the SMU’s, the following features can be provided.
• ABR, nonreal-time VBR and UBR connections take ad-
vantage of the large cell buffers. CBR- and real-time VBR
traffic is routed through the SMU via a bypass.
• Peak cell rates of real-time or nonreal-time connections
can be shaped at the ingress of the switch.
• The peak cell rate of a VP connection originated in the
node can be shaped at the egress of the switch.
• Peak cell rates of nonreal-time connections can be re-
shaped at the egress of the switch.
Buffer Management: Fig. 6 gives an overview of the
buffering architecture of the switch equipped with SMU’s.
Large cell buffers are provided in the ingress SMU and in the
egress SMU. The buffers in the ingress SMU are required to
protect the ASN core with its small buffers against temporary
overload. A switch internal flow control called the “dynamic
bandwidth allocation” (DBA) protocol [18] is used between
the SMU’s at the ingress and the egress sides. It ensures that
the aggregate cell rate of the cell streams destined for the
same egress port of the ASN core (point in Fig. 6) never
exceeds the capacity of the port.
While the cells of CBR and VBR-rt connections use a
special bypass around the large buffers, the cells of all other
Fig. 6. Buffering architecture of the switch with SMU’s.
connections can make use of them. The queueing is such
that for each ABR, UBR, and nonreal-time VBR connection,
an individual (logical) FIFO queue is reserved (“per-VC
queueing”). Eight thousand queues are available per SMU. The
use of per-VC queuing provides connection isolation, allows
for simple congestion control, and significantly simplifies the
implementation of early packet discard or partial packet dis-
card (see [3] and [15]) schemes for ABR or UBR connections.
Furthermore, it is a prerequisite for cell-scheduling strategies
controlling service rates of individual connections.
The cell scheduling mechanisms of the SMU use a two-
stage approach. Scheduler blocks, which are shown as a
set of queues feeding one pipe in Fig. 6, are used to form
groups of per-VC queues. Each scheduler block (containing an
arbitrary number of connections) is served at a deterministic,
configurable rate . The cell streams emitted by the different
scheduler blocks are multiplexed together with the traffic
coming from the real-time bypass on the egress link of the
SMU. The FIFO queue at this multiplexing point (point
or point , respectively) can be kept small by ensuring that
the sum of the rates plus the bandwidth required for the
real-time bypass is below the capacity of the egress link of
the SMU. (In Fig. 6, the queue feeding the egress link of an
SMU is not explicitly shown.)
A scheduler block can be operated in one of two modes.
In the “WFQ” mode, the queues within a scheduler block
share its deterministic service rate according to a “weighted
fair queueing” (WFQ) strategy. WFQ provides fairness and
RATHGEB et al.: MAINSTREETXPRESS
throughput guarantees for individual queues as required, e.g.,
for ABR traffic. WFQ was first proposed in [4], and has
been further analyzed in [11] and [12]. The algorithms studied
in these references have been designed for nodes handling
variable-length packets and are difficult to implement. The
SMU uses a simplified algorithm which is easier to implement
and more suitable for ATM systems switching fixed size
cells. For a discussion of further WFQ algorithms and the
role of WFQ for ATM traffic management, the reader is
referred to [14]. In order to shape the peak cell rates of
individual connections, a scheduler block can be operated in
the “rate-shaping” mode. In this mode, the service rate of each
individual queue of the scheduler block is always kept below
a queue-specific maximum value.
The scheduler blocks of the SMU’s are used for different
purposes at the ingress and egress side, respectively. In the
egress SMU, a scheduler block is associated with a physical
interface of the switch or with a virtual path originating in the
node. In the simplest case, the rate of the scheduler block
is defined as the rate of the associated interface, e.g., 45
Mbit/s for a scheduler block feeding a DS3 interface.
In the ingress SMU, one scheduler block is provided per
egress SMU in the system which contains the FIFO queues
for all nonreal-time connections routed via this specific egress
SMU. The service rate of the scheduler block defines the
capacity of an ATM pipe interconnecting the ingress SMU
with the corresponding egress SMU.
The Dynamic Bandwidth Allocation Protocol: As shown in
Fig. 6, the DBA protocol controls the capacity (cell rate)
of the pipes which interconnect each ingress/egress SMU
pair. The DBA protocol is a distributed resource management
mechanism whereby each SMU is responsible for its own local
resources, i.e., DBA does not involve any central functions
in the switch. The DBA procedures use a cell-based mes-
saging protocol to exchange bandwidth allocation information
between ingress and egress SMU’s.
Each ingress SMU has to detect a backlog of cells for
any pipe to an egress SMU, and interprets the backlog as an
indication that the currently allocated rate for the specific
pipe should be increased. This causes a DBA control cell to
be sent to the appropriate egress SMU requesting an increase
in the path’s allocated bandwidth. However, the ingress SMU
only requests additional bandwidth from an egress SMU if it
has bandwidth available at its own output (bottleneck at point
) to send data into the ASN core.
Upon receiving a request cell, the egress SMU will grant
the request only if the port bandwidth at point in Fig. 6
is not already fully allocated. If an egress SMU has allocated
all its inlet bandwidth, any further requests for bandwidth are
queued until an ingress SMU has emptied its logical buffer
assigned to this egress SMU, and sends a clear down message
to release bandwidth no longer required. It is the purpose of
the large input buffers to avoid cell loss in this situation.
This method ensures that only those cells are admitted to the
ASN core that have a prebooked exit from it in order to avoid
excessive cell losses in the buffers of the switching elements.
On the other hand, the latency of the control is low enough to
guarantee a full utilization of the switch fabric.
801
One of the advantages of a cell-based flow control protocol
like DBA is its independence from the ASN core realization.
DBA can be used with any nonblocking self-routing switching
fabric. There are three basic types of messages passed across
the core fabric between ingress and egress SMU’s.
• Request and Cleardown messages are generated by the
ingress SMU’s in response to changes in the fill state of
their scheduler blocks.
• The Offer message is generated by egress SMU’s when
bandwidth cleared down by one SMU can be offered to
another one.
In [17], the performance of the DBA protocol has been
studied. For high loads, the cell delays in a switch using input
and output buffering together with the DBA protocol approach
those experienced in an ideal output buffered switch. For very
low loads, the delays are slightly higher than for the ideal
switch due to the fact that it takes some time before a backlog
of cells at the ingress is detected and the bandwidth of a pipe
is increased.
E. Control Concept
The main challenge for the control concept of broad-band
systems is to meet the requirements of future applications and
traffic mixes, where little relevant experience exists today.
Other than in narrow-band switches, the applications are very
heterogeneous and have significantly different traffic profiles.
For example, for video on demand, the bandwidth required per
connection is relatively high (1.5–6 Mbit/s), and long holding
times (60 min and more) occur quite often. Narrow-band
backbone trunking with switching of individual connections,
on the other hand, requires low connection bandwidth (64
kbit/s or less), but due to the—on average—shorter holding
times and the large number of individual connections, the
required call-processing power is dramatically higher than in
the first case, while the required switch fabric throughput is
significantly lower. As a consequence, ATM switches need a
scalable processing platform with flexible task assignment and
distributed application software to be future-proof. Moreover,
the processing power has to be scalable independently of the
size of the switch fabric and the number of external interfaces.
For MainStreetXpress core node, a distributed control plat-
form concept has been developed [8]. The main functions
for call processing and operation/maintenance are performed
by a cluster of central control processors, the MP’s (main
processors). Starting with one processor, the processing power
of the cluster can be easily extended by adding additional MP’s
according to the requirements.
The peripheral control platforms (PCP’s) located on the
various modules (LIC’s, ECC’s, AMX’s, SMU’s, ASN core)
support the central processors by performing local, mainly
hardware-related tasks like maintaining the connection-specific
tables on the LIC’s as well as local maintenance and fault de-
tection tasks. The communication among the central processors
and between the central and the peripheral processors is ATM
based, and uses the ASN communication infrastructure already
available. The internal control communication protocol uses a
standard AAL. The AAL functions as well as real-time critical
802 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO. 5, JUNE 1997
Fig. 7. Control cluster.
operations of the higher protocol layers are supported by
specific communication ASIC’s to offload these tasks from the
actual controllers. The internal control communication services
on the main processor (MP) and the peripheral controllers
support location transparency, i.e., applications which want to
use a certain software service (e.g., digit analysis) do not need
to know on which MP the service is offered; they just ask
for the service type, and the control communication system
directs the request to the right MP. The support of location
transparency allows us to move software services from one
MP to the other without any impact on the software structure.
For the flexible assignment of tasks to MP’s, four basic load
types have been defined (see Fig. 7).
• Stand Alone (SA): The Stand Alone MP (MP–SA) pro-
vides the Q3 interface toward the management system
and interfaces for external data storage devices. All
administered data and code are stored on disk for security.
The MP–SA is also the “maintenance parent,” i.e., it
controls start-up of the system and the recovery escalation
in case of errors and failures. Usually, there is one
MP–SA per node; for very large switches, it may be
necessary to provide more than one MP with SA load
type. The major performance requirement for the MP–SA,
apart from start-up and recovery, is the processing of all
measurement and billing data collected in the system and
its periodic delivery to an operation center.
• Signaling Link Termination (SLT): The MP–SLT termi-
nates all external signaling links, and provides the low-
level protocol handling, e.g., the signaling adaptation
layer (SAAL) for broad-band UNI and NNI and the
message transfer part (MTP) for narrow-band CCS7 links.
UNI and NNI signaling links are assigned by admin-
istration to an MP–SLT. If performance measurements
indicate that an MP–SLT is permanently overloaded,
signaling links may be rearranged to another MP–SLT.
Depending on the configuration, there can be multiple
MP–SLT’s for a node.
• Signaling Manager (SM): The MP–SM performs the
network management tasks for the CCS7 network, e.g.,
handling of CCS7 link states. Usually, there is only one
MP–SM per node.
Fig. 8. Software architecture of MainStreetXpress core services node.
• Call Processing (CALLP): The Call Processing MP
(CallP–MP) handles the higher layers of the signaling
protocols (e.g., DSS2 Q.2931, B-ISUP, N-ISUP),
performs connection admission control (CAC), and
provides digit analysis and translation. User and access
resources are assigned to a CallP–MP by means of
administration, allowing again for rearrangements due to
performance requirements. The number of CallP–MP’s
grows with the overall connection-handling capacity
requirements.
The load types allow us to configure a switch exactly for the
processing capacity required. Moreover, the processing of a
call is usually distributed over several MP’s: the MP–SLT’s
terminate the incoming/outgoing signaling link and the
CallP–MP’s perform the connection admission control for the
A-side and B-side resources (e.g., bandwidth, VPI/VCI). Digit
translation and routing are performed on all CallP–MP’s for
a specific call, usually by the A-side CallP–MP. As the ASN
core itself is nonblocking and has the single-path property,
there is no need for a central path search. Therefore, there is
no MP which has to be addressed for every connection and
which could create a bottleneck in the system.
For an efficient software implementation, it is important to
identify generic functions which may be used by all appli-
cations. For the MainStreetXpress core node, three software
layers have been defined as shown in Fig. 8. These layers are
described below in more detail.
Software Platform: The software platform comprises the
microcore software, the operating system (OS), and the inter-
nal communication services. The OS provides basic services
like scheduling, memory management, and internal processor
communication. For interprocessor communication, a specific
internal transport protocol (ITP) is used. OS and ITP provide
the basic support for location transparency by service address-
ing. For ITP and external protocols (e.g., SAAL), time-critical
functions, e.g., the keep-alive functions for the SAAL and
a confirmed delivery for ITP, are supported by a dedicated
ASIC on the MP.
RATHGEB et al.: MAINSTREETXPRESS
Application Software Platform: The application software
platform comprises the following generic services which are
used by the various applications of a broad-band switch.
• Operation Administration and Maintenance (OAM) Ser-
vices: These comprise the Q3 communication services
and the file system. Applications use the Q3 communi-
cation services for the processing of Q3 commands and
for the output of statistics/billing data to the operation
center. Generic Q3 support functions are event forward-
ing, notification logging, security functions, and alarming.
The Q3 protocol stack comprises CMIP/CMISE, FTP,
and TCP/IP. The file system is used for the storage of
administered data or log files for billing/statistics data
on disk. Access to the file system and Q3 communication
services is performed through a common API (application
programming interface).
• Physical Switching Server: The physical switching server
is responsible to actually set up the paths through the
ASN. For each connection setup request, the application
specifies the endpoints of a path. The physical switching
server determines the modules involved and formulates
the switching commands required to load the connection-
specific tables in the LIC’s and, for multicast connections
only, in the switching elements. Thus, the physical switch-
ing server hides the details of the switching fabric from
the applications.
• Database Management System (DBMS): Applications use
DBMS to store and access semipermanent and transient
data. DBMS is a distributed database system, i.e., data
may be located on any MP in the system. To provide
efficient access and storage, data may be partitioned or
replicated. For example, subscriber data are partitioned
among the CallP–MP’s, i.e., a specific CallP–MP keeps
the data of a particular subscriber. Routing data for
digit translation are replicated, i.e., the same data are
kept on each MP. The location of the data on a certain
MP is completely hidden from the application. DBMS
offers generic access routines (e.g., GET, CREATE, SET,
DELETE) and Q3 operations (e.g., scoping, filtering), and
provides concurrency and transaction control to guarantee
consistent data access. The implementation approach for
DBMS is data driven, which means that all information
on data is kept in a data dictionary (DDI).
• Upgrade: The MainStreetXpress core node allows for the
online upgrade of the system software without loss of
service. During upgrade, the redundant central control
hardware is used to switch all system functions from the
old to the new software version. The upgrade procedure
is controlled by generic platform software.
• Load Control: The load state of the MP’s is constantly
monitored. In case of overload, appropriate measures are
taken by the load control, for example, new call requests
are rejected. If an MP gets into overload states frequently,
a reassignment of a service may be initiated. For example,
CCS7 links could be assigned to another or new MP–SLT.
• Maintenance: Performs all hardware-related maintenance
activities such as fault processing, diagnostics, reconfig-
uration, and routine testing of an MP. To allow for a
803
fault-tolerant software implementation, special software
error treatment and a recovery strategy with several
escalation steps are supported.
• System Utilities: Online debug utilities are provided for
testing and fault evaluation purposes. The main online
utilities are patch, trace, and dump.
Applications: The applications implement the specific ser-
vices of the broad-band switch visible to the user. Call-
processing software controls the setup and release of calls
and connections. Signaling interfaces for the NNI (e.g., CCS7)
and the UNI (e.g., DSS2) are supported. With respect to the
implementation, supplementary features are separated from
the basic call handling. Hence, the realization of new call-
processing features has a minimal impact on the existing
software. For billing, the relevant information including, e.g.,
the cell counts is provided in a format suitable for pro-
cessing at an external billing center. Statistics are collected
for performance management (e.g., quality of connections),
traffic measurements, and load measurements for the MP.
Administration is provided for a number of applications, e.g.,
call processing, CCS7 network, system configuration, and
ATM layer OAM functions (loop back, continuity check, etc.).
Both the narrow-band CCS7 (MTP, ISUP) and the B-ISDN
(SAAL, MTP level 3, B-ISUP) signaling protocols and the
required interworking functions are implemented. Together
with the packetization/depacketization for the user traffic on
the LIC’s and the additional echo cancelation circuits, this
allows for interworking with the narrow-band ISDN.
III. REDUNDANCY PRINCIPLES
To be able to meet the availability and reliability require-
ments for a central office switch, various redundancy concepts
are implemented in the MainStreetXpress core node, including:
• full redundancy for all central components, i.e., for the
ASN, the SMU’s, and the central control;
• optional redundancy for external lines and LIC boards;
• pool redundancy for ECC’s.
In general, the application classes for redundancy are de-
fined as follows.
“ ”: The traffic protected by the redundancy is car-
ried via one working and one protection entity
simultaneously. The receiver terminating the
redundancy has to select cells from one or the
other entity to be able to forward one consistent
traffic stream.
“ ”: The traffic protected by the redundancy is only
carried by the protection entity if a failure oc-
curs on the working entity. One protection entity
protects one working entity. During normal con-
ditions, the protection entity can be used for other
applications, e.g., to transport extra traffic, which
is dropped if a failure on the working line occurs.
“ ”: The traffic protected by the redundancy is only
carried by the protection entity if a failure occurs
on one of the working entities. One protection
entity protects working entities.
804 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO. 5, JUNE 1997
A. The ASN Redundancy Principle
The ASN is fully duplicated in two redundant planes op-
erating according to a redundancy scheme. To support
this scheme, a connection-specific sequence number as well
as a frame check sequence (FCS) are added to every cell at
the ingress side LIC. Then each cell is being duplicated, and
one copy is transmitted through each plane. Due to the fact
that the planes are not synchronized, the two copies of a cell
will, in general, experience slightly different queueing delays
within the ASN. On the egress side LIC which receives the
cell streams from both ASN planes, a “redundant path com-
bination” (RPC) mechanism decides, based on the sequence
number and the result of the FCS mechanism, which one of the
copies will be forwarded. If the first cell copy arriving carries
a valid FCS, it is forwarded to the outgoing link. The other
cell copy will be recognized based on the sequence number
and will be discarded. In case the FCS mechanism detects bit
errors in the faster cell copy, this one is discarded, and the one
arriving later is forwarded if at least the cell header is free of
bit errors. The main advantages of this redundancy scheme
are as follows.
• A redundancy on connection (VPC, VCC) level is pro-
vided where single failures in the ASN will not disturb
existing connections at all. Multiple failures will have no
impact on a particular connection if at least one path in
either plane is still available.
• No complex switchover mechanisms are necessary in case
of failures.
• No cross channels for synchronization of the two ASN
planes are required.
• A complete plane can be taken out of service for main-
tenance or upgrade without any impact on existing con-
nections, i.e., the upgrade of the ASN can be performed
without service interruption.
• The combination of the internal FCS mechanisms and the
RPC mechanism makes the MainStreetXpress core node
virtually error-free with respect to sporadic bit errors since
the probability that both copies of one cell are corrupted
is extremely small.
B. Line and Board (LIC) Redundancy
Network reliability can be improved significantly by provid-
ing redundant external lines between two network elements.
The LIC’s support “ ” line protection switching for high
bit-rate SDH/SONET interfaces. With the same hardware,
“ ” line protection switching also can be offered with the
option to carry low-priority traffic (which is dropped in case
of a failure) on the protection line.
The line protection switching is implemented according to
ITU-T G.841 (SDH) and according to Bellcore TR-NWT-
000253 (SONET), allowing the nodes to terminate redundant
lines coming from standard transmission equipment. To con-
trol the switchover, the multiplex section/line overhead bytes
are used to perform the “multiplex section protection”
(MSP, G.783) protocol for SDH interfaces and the similar
“automatic protection switching” (APS) protocol according to
Bellcore TR-NWT-000253 for SONET interfaces.
Fig. 9. LIC protection switch (LPS) in SE.
To meet the port down-time requirements, board redundancy
is offered for the LIC’s in a “ ” configuration for high-rate
PDH interfaces and SDH/SONET interfaces. In this “ ”
application class, one LIC board is active and another board is
in standby mode. For E1/DS1 interfaces, a “ ” redundancy
configuration is supported, i.e., active LIC’s are protected
by one standby LIC. In the case of external line redundancy,
the redundant lines are connected to different LIC’s. If one of
these LIC’s fails, the same protection switching mechanism is
used as in the case of a line failure.
For the support of line and board redundancy, the means
are provided to direct the cell streams to the currently active
units. In the direction from the ASN toward the LIC, an
LIC protection switch (LPS) is implemented in the switching
elements (SE’s) of the egress AMX (see Fig. 9).
The LPS can redirect the traffic from the logical output
buffers of the SE to any physical output of the SE without
changing the routing information contained in the extended
cell header. The LPS can be set individually for each output
of the SE by the AMX control as:
• point-to-point (e.g., applied for “ ” line protection);
• point-to-2 point (e.g., applied for “ ” line protection);
• no connection, which leads to cell discard, e.g., applied
for the low-priority traffic of a “ ” line protection if a
failure on working line/LIC occurs.
In the direction from the external interface toward the ASN,
a line selection function connects the external interface to the
currently active LIC in case of board redundancy; for external
line redundancy, this selection is not necessary. Depending
on the interface type (electrical, optical), fiber splitters, p-i-n
diode switches, relays, or a spare bus are used to provide the
line selection.
In all “1 : 1” and “1 1” redundancy cases, the connection-
specific tables on the spare LIC are already preloaded with
the same information as those in the active LIC. Thus, a short
switchover time 50 ms can be achieved. In a “1 : 1” line
redundancy application with low-priority traffic, both routing
data sets (of working and protection line) are preloaded in the
tables of the protection LIC.
C. Pool Redundancy for Echo Cancelation Circuits (ECC’s)
All ECC’s are managed as a common pool irrespective
of the location of the various ECC boards within the node,
i.e., if a new connection requires echo cancellation, any
RATHGEB et al.: MAINSTREETXPRESS
free channel out of this pool can be freely selected by the
application software. If, e.g., due to hardware failures, single
echo cancellation channels or complete ECC’s have to be taken
out of service, sufficient spare capability is provided, which
can then be allocated to new connections.
D. Redundancy of Central Control
An MP consists of two physical processors with microsyn-
chronous operation. Due to this kind of operation, both sides
always have the same information about transient states, and
the redundancy is completely transparent to the applications
software. If one side fails, the other side takes over immedi-
ately. The identification of the faulty unit is done by means of
the built-in self-test capabilities of the processors. Besides this
hardware redundancy, there is a logical redundancy on the
service level for the central control platform. For replicated
services, any MP offering the service can replace a faulty MP
without impact on the applications. For partitioned services,
the service may be reassigned to another MP.
IV. CONCLUSION
This paper has provided an insight into the architecture of
the MainStreetXpress core node which has been designed for
central office applications in the core of an ATM network. The
highlights of this architecture are the following:
• the scalability, both in terms of throughput and processing
power, allowing to build configurations ranging from
small single-shelf solutions up to very large central office
switches;
• the high availability and reliability which are achieved by
using redundancy mechanisms in all central components
of the system core as well as in the interface units;
• effective support of traffic management mechanisms
which lead to high link utilization for bursty data traffic,
and which are confined within specific SMU modules
avoiding that these complex mechanisms have to be
treated in every part of the system;
• a software architecture which allows us to introduce
feature upgrades without a major impact on existing
software, and to upgrade the system without service
interruption.
Finally, the use of a number of system-specific ASIC’s pro-
vides, at the same time, optimum performance, high reliability,
and all the features required, without compromises with respect
to the architecture.
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ISS’95, 1995.
Erwin P. Rathgeb was born in Ulm, Germany,
in 1958. He received the Dipl.-Ing. and Dr.-Ing.
(Ph.D.) degrees in electrical engineering from the
University of Stuttgart, Germany, in 1985 and 1991,
respectively.
From 1985 to 1990, he was a member of the
Scientific Staff at the Institute of Communications
Switching and Data Techniques, University of
Stuttgart, where he was head of a research group
on the design and analysis of distributed systems.
From 1990 to 1991, he was a Member of the
Technical Staff within Applied Research at Bellcore, Morristown, NJ, before
joining Bosch Telecom, Backnang, Germany. In 1993, he joined the Public
Communication Networks Group of Siemens AG, Munich, Germany. There,
he contributed to the definition of the overall system architecture of the
MainStreetXpress core node. Currently he is involved in product planning for
broad-band communication systems.
Wolfgang Fischer (S’87–M’89) received the Dipl.-
Ing. degree in electrical engineering 1983 and the
Dr.-Ing. (Ph.D.) degree in 1989, both from the
University of Stuttgart, Germany.
From 1983 to 1988, he was a member of the
Scientific Staff at the Institute of Communications
Switching and Data Techniques, University of
Stuttgart. During that period, he was responsible
for the analysis of ISDN protocols both in terms
of performance and formal correctness. In 1989,
he held the position of Research Associate at
INRS Telecommunications, Montreal, Canada, where he was involved in
the performance analysis of ATM systems. Since 1990, he has been with the
Public Communication Networks Group of Siemens AG, Munich, Germany,
where he has held various positions dealing with systems engineering of
ATM communications systems. Currently, he is responsible for the product
line management of broad-band communications systems.
806 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 15, NO. 5, JUNE 1997

Christian Hinterberger was born in Burgkirchen,
Germany, in 1961. He studied electrical engineering
at the Technical University of Munich, where he
received the Dipl.-Ing. degree in 1986.
In 1987, he joined the Siemens Research and
Development Department, where he was involved
in studies on ATM switching architectures. In 1989,
he joined the Siemens ATM System Development
Group. There, he was engaged in the development
of ATM switching systems and ATM ASIC’s. From
1994 to 1996, he was with the ATM System Engi-
neering Group. Since 1997, he has been with the Siemens Semiconductor
Department, responsible for product definition of ATM layer and ATM
adaptation layer ASIC’s.
Regina Wille-Fier was born in Darmstadt, Ger-
many, on April 25, 1956. She studied mathematics
at the Universities of Tübingen and Münster and
received the Dr. rer. nat. (Ph.D.) degree for her work
in the area of functional analysis.
In 1985, she joined the Research Laboratories
of the Public Communications Networks Group of
Siemens AG, Munich, Germany, where she was
working on software architectures for ATM switches
with decentralized control. She participated in the
development of the concepts for switching network
control, call processing, and internal communication for the MainStreetXpress
core node. Currently, she is Director of Systems Engineering for broad-band
communications systems.

Eugen Wallmeier received the diploma degree and

the Dr. rer. nat. (Ph.D.) degree in mathematics in
1980 and 1983, respectively, from the University of
Muenster, Germany.
In 1980, he became a member of the Scientific
Staff at the Institute for Mathematical Statistics,
University of Muenster. In 1985, he joined the Pub-
lic Communications Networks Group of Siemens
AG, Munich, Germany, where he has been engaged
in software development for an X.25 data processor
and performance analysis of telecommunication sys-
tems. Since 1992, he has been supervising a group working on ATM traffic
and performance issues, and on the design of traffic control functions for
ATM switches.
Dr. Wallmeier is a member of VDE.