Documente Academic
Documente Profesional
Documente Cultură
Evangelos Moustakas
A Thesis Submitted in Partial Fullfilment of the Requirements for the Degree of Master of Science in Computer Enginneering
Approved by
Professor
Professor
Professor
Department of Computer Engineering College of Engineering Rochester Institute of Technology Rochester, New York September 1991
September 6, 1991 I, Evangelos Moustakas, hereby deny permission to the Wallace Memorial Library of RIT to reproduce my thesis in whole or in part. The Author
Abstract
Hardware Description Languages are used as the connecting links between the design of a digital system and the way this design is being represented in computers, with the ultimate
goal
being
the
In
the
simulation
of
and
verification
of
that
design
RISC to
before
construction
any
this
thesis,
design
VHDL
we
follow
the
VHDL
steps
of
architecture
and and
finally
as
the
the
a
tool
describe,
abilities
simulate
of we
unique
behavioral description
.
description
where
the
latter
to
contains
multiple
levels,
step
design
(PMS)
The
final
is the
to
assist
correction
Table
of
Contents
Table
of of of of
contents
List
List List
figures
tables
abbreviations
i iii iv iv
v
Preface
The RISC Concept 1.1 How the RISC architecture 1.2 Definition of the RISC 1.3
Advantages
and
evolved
1 1 RISC
Disadvantages
of
the
5
7 12
and
System Description
Bus
2.3
2.4
Timing
Organization
the Stack
Memory
14
2.5
Exception
Handling
Set
and
15
The
3.1 3.2
instructions
instruction
the
fetch
cycle
18
formats
modes
18 22
3.3
3.4
addressing
Processor
syntax
Status
and
Word
3.5
4
The
Assembly
Central The The
instruction
encoding
25 26
Processing
structure
Unit
4.1 4.2
CPU
28 30 31 32
registers
Control
Unit Unit
4.3 4 4
.
The The
Interrupt
control
points
The The
The The
immediate
register
35
file
Logic Unit
35 36 36
37
Arithmetic
Power
Shifter
4.5
Instruction
Decomposition
VHDL
Description Hardware
of
the Architecture
Languages
~ ~
Description
43 43
5.1.1
VHDL Started
Packages
Description
Getting
5.2.1
45 45
46
data
bus
units
48
secondary
50
52
memory
CPU
The The
registers control
53 53
54
clock unit
5.7.1
5.7.2
5.7.2.1
The
internal
54
-l-
fetch PROCESS
execute state
55
55 56
57 PROCESS
BLOCK
coordination
interrupts
access
The for
of
58
59
59
Simulation
6.1 6.2
The
program
63
system
6.3 6.4
the
65 66
external
RESET
interrupt
and
execution
interrupt
68
70
Conclusion
Recommendations
References
Appendix A
-
71
Package VHDL
Listing
Listing
Program
Al
Appendix
Program
Bl
Appendix
C
D
Simnlatioi* Simulation
;._
Execution
(1)
CI
Dl
Appendix
of
Program Execution
(2)
-n-
List
of
Figures
Figure
System Under
Simulation
Figure Figure
Figure Figure Figure Figure Figure Figure
Figure
2.2
Memory Memory
Word Word
Bank
Select
and
Logic
9 9
10 10
11 12
Banks
Byte
Signals
2.4a 2 4b
.
and
and
Organization
Byte
of
Organization Protocol
2.5 2 6
.
Memory
Read/Write
Bus
Sequence
Cycles
2.7
2.8 2
.
13 13 14
2.10 3 1 3.2
.
15
instruction instruction
instruction
Word
format
format
20
20
21
long-immediate
& Processor
format
3 4 3.5
.
Instructions
Flags Status
24
4 4
CPU
structure
25 29
30
decoder
control
4.2
.
State
Sequence
of
an
3
1
Example Control
instruction
fox
and of
32
signal
Figure Figure
Figure Figure Figure Figure Figure
Figure Figure
4.4
node
5 5 5 5 5
Description
c7 Levels
c8
33
44 46 47
47 47
Digital
Systems
5.2
.
Directory
BLOCKS
Control
and
Organization
3
4
PROCESSes BLOCK
Block
Unit
5.5
.
Interrupt
Unit
6
8
Wired
OR
logic
Function
48
49 49
5.7
.
Resolution
Data
bus bus
decomposition PROCESS
of
Figure
Figure Figure Figure
5 9 5.10
.
Data
50
formation 50
Example
the
data bus
Unit
5.11
System
Clock Bank
Generator
51 51
unit
Figure
Figure Figure Figure Figure
5 12 5.13
.
5.14
Select
51
52
54
5.15
for
MAR
16
Internal
Clock
PROCESS
55 55
5.17
The The
The
fetch
Figure
Figure Figure
5.18
execute
BLOCK
56
PROCESS
5.19
5.20 5.21
5.22
state
coordination
56 interrupt
57 interrupts 8
Micro-operations
for
external
Figure
Figure Figure
VHDL The
implementation
for
the
external
memory
access
PROCESS
59
IU
5.23
5.24 5.25 5.2 6
recognition
by
59
error
Figure Figure
Figure Figure Figure
Figure
PROCESS PROCESS
will
issue
pass
an
60
will
serious
error
6 6 6
6.2
.
simulation recognition
3
4
interrupt
read
Figure
Memory
cycle
60 62 63 65 66 66
-in-
Figure Figure
6.5 6.6
Operation
External
of
the
buses
assertion
67
interrupt
68
List
of
Tables
Table
2.1
2.2 3.1 3.2
Table
Table Table Table Table
Table
Memory Timing
The Opcode
write
instructions
and
11 their
Characteristics
Set
&
Meaning
13 19 22
Instruction
Assignment
syntax
3.3
4
.
Instruction
encoding
the
26 33
of
Transfers
Resolution
and
Operations
5.1
Table
for
input
G3
48
List
of
Abbreviations
ADL ALU
Architecture Arithmetic
Description
Language Computer
Logic
Unit
CISC
Complex
Instruction
Set
CMHU CPU
CU
HDL
Unit
Unit
Description
Language
HLL INTA
Level
Language
Interrupt Interrupt
Acknowledge
Unit Register
IU
MAR
MBSU
MDR
Address
Bank Data
Select
Unit
Register
PC
PIA
Program
Peripheral
PMS
Processor
Memory
Status
Switch Word
PS
PSW
Power
Shifter
Processor
RISC SP
UART
Reduced Stack
Instruction
Set
Computer
Receiver
Pointer
Universal
Asynchronous
Transmitter
VHDL
VHSIC
VHSIC
Hardware
High
Description
Language Circuit
Very
Speed
Integrated
VMA
Valid
Memory
Address
-iv-
Preface
As the
one
can
understand
from the
:
title
of
this
thesis,
are
it
and
is focused
quite
on
The RISC
architecture
.
(VHDL)
They
in
both
related
issues products is
year s.
although
the
word
"recent"
computer
usually
since
used
to
date began
something
to
evolve
of
no
more
than
one
old
early in the
future
1980'
They
are,
they however,
and
both the
in
the
main
points
attraction
computer
architecture
and
hardware to
description
a
and
simulation
.
fields
two
a
today
they
seem
promise
lot
for the
are
connected
in
used
to describe
simulate
representative
design
theory.
simpler
The
than
RISC the
VHDL
which will be a primitive but according to the definition of the RISC chosen because architecture was it is much
CISC
ones
and and
be
spent
to
design, develop
can
short
system
time
with
could
words
and
with
figures.
then
replace
the
as
words
and
the to
figures
The
universally
of
recognized
code
capabilities
a
VHDL
are
exhibited,
and an not
attempt a
describe
piece
of
complete
architecture
just
The
set,
single
hardware
so
like
gate
or
ALU.
system's
their
many
other
issues
and
of
an
architecture
become
pages
well
organized
self-explained
code
when
described
In
in
the
VHDL. The
present
thesis
report
contains
two
of
parts.
first
will
one
(chapters
1-4),
of
the
architecture
the
and
system
that
a
be
used
for the
simulation
is presented,
architecture
starting
the
with
general with
description details
the
RISC
continuing
machine and we
the
organization
and
the the
architecture
of
built. Enough
parts
for the
behavior level
part
of
the the
system
its
are
given
from
In
we
the
chip
down
of
to
the
register
transfer
level.
second
thesis
VHSIC
report
(chapters
Description
simulate
5-6)
the
first
introduce
and
the
use we
Hardware
and
Language
(VHDL)
then
we
it to describe
built
of
architecture
of
the
system
in the
the
first
explaining simultaneously the part, complete and the way we use them to
features
the
language
project.
Finally,
would
at
the
completion
of
this
thesis
project,
of
RIT'
I
s
like
to
of
thank
the
following
faculty
members
Department
Computer
Engineering,
and
professors
George
A.
Brown,
but
Tony
H.
Chang
the
Roy
S.
Czernikowski,
for
the
their
observations,
suggestions
and
corrections
during
the project,
mainly
for
valuable
time
they dedicated in
many
thesis
meetings.
v-
The
There
RISC
are
Concept
controversial
comments
many
today
the
about
the
numerous
and powerful
RISC
architectures
microprocessor
performance.
of
strong
these
new
CPUs,
the
reason
they
the
became
so
popular,
their
weaknesses,
.
compared
to
more
conventional
micro
processors
How
the RISC
architecture
evolved
With the
of
progress
of
computer
technology
use
and
the
ability
microprocessor
manufacturers
to
many
more
transistors
in
single and
chip,
complex came
robust
to
a
have
instruction sets grew, including more instructions. A typical instruction set almost two hundred (200) instructions and in
the the
various
combination
with
and
often
numerous
addressing
where the control unit of modes, confusing the microprocessor took up almost 60% of the available space. The programmers and the compilers had a hard time determining
situation
emerged
which
instruction
a
was
the
best
for
particular
situation.
of
Also,
single
increase
could
consist address
of
several
bytes
or
they
could
use
the
data
and
the
buses
several
times
in
order
to
access
their operands,
mainly
that
due
to
the
complicated
addressing
and computer
modes.
Some
computer
engineers
scientists
thought
and
it
would
be
better
if
microprocessor
had
simple
small
instruction
modes
set
or
with
uniform
instruction
which
.
addressing
a
single
instruction
for
all
formats,
be
use
only
fetch the
cycle
the
instructions
used
Also,
that
if
the
possible, throughput
years of
single
of
execution system
cycle
would
so
could
be
maximum. within
After
of
research
that
started and
a
the
laboratories
number
of
in the in companies
IBM
emerged
late
the that
seventies
continued
new
in
a
of
eighties,
type
microprocessor
had
RISC
all
the
required
characteristics.
It
of
was
called
(Reduced
Instruction
Set
also
Computer)
had
some
because
new
its
.
limited instruction
set,
but
it
features
1.2
Definition
of
the RISC
era
In
machine
the
and
early RISC
it
was
quite
say exactly
years
what
distinguished
Today,
after
of
development,
Experts
now
the
new
RISCs are
almost
as
complicated
as
CISCs.
have
started
arguing
not
.
about
we
precisely what
will
constitutes
a RISC and
what
does
on
Below,
.
try
to define
RISC
machine
depending
are
the
most
common
of
their
characteristics
as
they
described
today
-1-
Small
Instruction
Set
It
was
observed most
during
of
the
years
of
research
the
compilers
used
only
CPUs
30%
a
the
attempt
instruction sets of some robust CISCs. RISC to implement only that 30%, giving the ability to
faster
:
have
Fewer the
size
will
chip.
The
and
instruction
contain
formats
matches
are
of
usually
of
than four
(4)
they
so
instructions
same
length. be
It
is
length
the this
the
data bus
one
an
instruction
with
fetch
always
The
of
restriction
is
that
require
overall
more
than one
size.
only an immediate
problem
operand
program
Many
with
On-Chip
about
Registers
Most
RISCs
include
file
or
one
hundred
(100)
registers. with
There
course
some
variations
only 32
RISCs
zero
registers
the
GMU
MIRIS
with :
2048.
Almost that
written
Dummy
Registers
all
of
the (i.e.
of
have
when
dummy
and
register
(usually R0)
any
value
yields
the
value
read
discards
to
it
it
the
for
is
always
tied
to
GROUND)
Limited
registers
into the registers and every ALU is applied to the contents of the registers or a immediate data. The addressing modes, thus, have been partial limited and only two are usually met : the register indirect and the immediate. implement a All the RISC CPUs : Calls Jumps and Deferred
are
operation
pipelined
Because
existence each
the
operands
of many instruction
execution
system.
In the
case
of
branch
or
call, (see
the
system
cannot or
immediately
the
one
execute
the
instruction before
prefetched
it
flushes
.
executes
that
had been
of
2.1)
Single-Cycle
simple and
execution
Because
most
the
operations
execution
are
occur
between
registers,
of
single
cycle
has
been
obtained require
for
most
the
instructions.
cycles
Some
others,
however,
multiply,
multiple
execution
(load,
store,
divide,
etc)
Load/Store Architecture
external
instructions.
complicated
memory Some
is
by
available of
way to
Load
manipulate and
the
Store
also
modern
architectures
have
include
test-and-
set
or
swap
Advantages
and
Disadvantages
of
the RISC
In
the
years
of
research
that
brought
up
the four
:
RISC
architecture,
the
computer
experts new
were
demanding
and
(4)
of
basic
features
for
Their
their
microprocessors
speed,
cost a
simplicity,
High Level
Language
(HLL)
were
support
low
manufacturing.
demands
are
accomplished
in
high
as
degree,
the
size
even of
though
there
always
example.
some
trade-offs
such
the
programs
for
-2-
The
main
idea
in RISCs
of
is to
use
big
register
file
in
the
set
the CPU to
save
most
the operands
in
a
order
to
eliminate
frequent
with
memory
standard
simple
instruction
system'
data word,
and
.
to
reduce
the
of
instruction
formats
and
the
number
the
The
the reducing the size of the instruction formats and addressing modes, we reduce instruction huge and complicated Decoding System. The
By
decoding
chip
means
can
now
be
done
of
with
simpler
circuits most
with
in
of
less
the
CISCs.
time.
total The
Control
area
Unit
(CU)
now
occupies
at as
10%
the
instead
of
around
60%
simplicity
fewer
the CU in turn
and
means
greater
speed.
smaller
CU
of
gates
shorter
propagation saved
paths
with
fast VLSI
(more
than to
realization. smaller
The
was
.
space
that
was
by
the implementation
CUs
dedicated to
The
speed
of
large
the
register
files
RISC
CPUs
is
also
due way
to
handle
interrupts
and
context
switching
-
internally,
The
CPU-memory
the RISCs
traffic
was
in this
created
after
an
examination
behave.
spends
The
their compilers and the way that many HLLs a CPU designer tries to reduce the time that
and
subroutine of calls.
in
loops
on
All
the
operations
are
performed
the
contents
the
registers
in
the
register
file
where
.
are
the memory
accesses
The
will
size
of
the
register
split
the
a
computer
designers
who
support
big
register
file
is always a subject that into two categories : those insist that a and those who
enough.
relatively
and
small
register
file
of
of
is
They
its
are
both
wrong
because
each
.
structure
has
RISC
advantages
disadvantages
[TAB90]
of
Some
the
disadvantages
happen
to
be
general
disadvantages
a small
the
architecture.
In
results
the
case
register
file,
many
will
have
to
of
.
be
stored
in
not
memory,
intermediate in resulting
the
opposite
increasing
of what
the
number
memory
There
accesses
(exactly
an
RISC promises)
calls
will
be
adequate
support
of a
for
subroutine will
and
interrupt
the
get
handling
to
(the
use
stack
be
needed)
and
ability
use
the
need
CPU
in
will
minimized.
large
and,
register
file
will
longer
used,
on a
time,
more
space
if
window
policies
are
complicated
CPU
logic
a
to
address
the
of
window
pointers
context
switch
or
subroutine
call
state.
An
inseparable
set.
disadvantage
the
of
RISC
is
a
the
instruction
of
With the
instructions,
or more
the
programmers
only
small
compilers procedure
have to
which
two
instructions
with
to
could
be
described
single
instruction
using
the
instruction
than
set,
the
one
written
thus making the average code size in CISC. The larger the code
need.
50%
CISCs larger
more
the
space
it
wiil
the
memory
of
The
subject
size
and
even
also
be
the
instruction
a a
rather
subtle
lot
of
research
-3-
in this
rather
area.
Some
companies
that
sets
manufacture with
RISCs,
provide
complex
instruction
150-200
instructions,
reaching the state to be considered CISCs rather than RISCs. It is true that both CISCs and RISCs have crossed the limits of their area and they have borrowed some features from
each
other.
will
Maybe
in
all
the the
future
we
will
see
microprocessors
that
combine and
positive
characteristics
from both
they
will
associated
with
each
them.
-4-
Architecture
The
architecture
with
and
that
Organization
we
developed
of
for
this
thesis
complies
most
of
the
aspects
RISC
they
were :
mentioned
in the
of
previous
aspects
the
number
instructions,
formats,
the addressing modes, the load/store architecture, the uniform fetch cycle, and the standard length of all instructions which
is
equal
to
the
basic
system
word
length
and
the
data
bus
width.
In
this
of
reasons
that
after explanation of the a short chapter, led us to name our RISC "primitive", an extended
description
examples refer
the
written
Because
reader
there
are also
should
to
the
more
third
the
instructions
are
explained
thoroughly.
Why
"primitive"
According to
must exhibit
the
previous
some
characteristics
the
CISC
ones.
Even
if
our
architecture
implements important
most
of
these
every
some
ones
that
Our
of
Pipelining is
system
one
of
them
and
the
most
important
for
of
one. sake
doesn't
One
support
of
any
great
pipelining
advantages
the
simplicity.
the
the
pipelined
systems
execute
is
the
high (of
speed
due
to
the
simultaneous
.
fetch
and
cycles
some
consecutive which
instructions)
our
It
incorporates,
supposed
however,
take These
and
drawbacks the
case
architecture
was
to
care
in
that
the
drawbacks
are
shown :
in
explained
later
A,B
a)
SBB JC
MOV
; ;
;
CF
address
Jump
Move
to
X
address
if
Carry
Set
X,Y
to
b)
CLCF LDX
Clear
Carry Flag
with
(address)
X,Y
; ;
Load X X
=
the
address
contents
of
ADC
CF
In
while
the
first
example,
the
last
instruction
executed.
is
fetched
the
the
one a
before
it,
it
is
to
being
the
execute and
Because
program
latter
is
branch instruction
need
and
flow the
of
the
may
be
the
an
last
instruction,
it
must of
fetched
consequently
the branch
Some
assemblers
change
sequence
instructions instruction
and
place
after
the
instruction
that
was
before
it,
without
affecting though,
the
-5-
intended
even
program
operation.
of a
This
instruction
will
be
executed
in
the
case
successful
branch,
since
it
will
have
the
mechanism will
have to
delay
first.
and
This
motive
along with the reason that follows, became the any pipelining in our system. The second case is more obvious than the first one since the LDX instruction takes two (2) execution cycles to load the
not
complicated
to
use
register
while
new
the
next
of
one
(ADC)
the
takes the
of
only
right
one
and
.
it
To
of
needs
the
contents
to
are
produce
result
visualize each
the problem,
here
steps
the execution
instruction:
LDX
FEE
F E
E
ADC
where
F means
Fetch cycle
and
means
Execution
above
cycle.
Most
with
of a
the
on
RISC
machines
today
is
overcome
the
problem
method
called
scoreboarding.
result shown
Without
any
further
as
explanation
can
that,
the
the
below,
where
we
clearly
the
see
execution
of
the
ADC
instruction
execution
:
is
held
until
load
instruction
completes
its
LDX
FEE
F
ADC Besides
pipeline
which
can
be
used
is
must
also
not
another
powerful
case
is
register
With
of
microprocessor windows
number
(blocks)
The
as well
dedicates
window
each
the
windows
to two
procedure.
variables
register
has the
which
space
to
keep
the
local
as
some
space and
is
the the
accessible variables
by
consecutive common
register
windows
keeps to
that
are
to two
procedures
(one
nested
or global variables. In this parameters passed other), way, the only thing that has to be done by the microprocessor is called, is to advance the subroutine new a every time
pointer
that
points
to
the
base
of
new
register
window.
Our
machine
cannot
support
this
it has only
since each all
eight
(8)
registers
-this
is
another
the RISC
that
want a
systems
have
at
least
32
(MIPS
and
time
we
subroutine
is
called
stack.
we
have to
to
push
the that
can
registers
to
save
into the
Finally,
instructions
working
permit
we or
have
mention
our
CPU
lacks
capable
any
of a
external
pins
that
make
or
it
even
in
multiprocessing
such
environment an
to
host
supervising
program,
as
operating
system,
that
can
multitasking.
-6-
General
The
System Description
and
microprocessor
the
an
main
under
simulation.
A data
with
and
address
memory bus
other
compose
run
the
system
both
16-bit
long,
used
some
additional
lines
control
signals.
There are
also
four
lines
with
(RESET,
each
/INT,
in
the
INTA,
CLOCK)
The
for interrupt
handling
The CPU's
and processor
timing. byte
are
whole
system
is
16-bit
machine
addressed.
external
pins
bus
16-bit, tri-state,
the data transfer to/from the memory other I/O devices. (I/O)
b)
c)
Address
WORD
bus
16-bit,
used
tri-state,
carry
a
unidirectional
bus,
a
to
If
HIGH,
(16
word
bits)
a
take
place.
If
LOW
or
then
VMA
only
single
byte
will
be
read
written
from/to
the
the
memory.
(0)
.
d)
Memory
Address
Becomes
a
address
bus
contains
memory
pulse
clock
address. on
(0)
line
will
e)
RESET
HIGH
this
for
at
least
the the
three
cycles
reset
CPU. (I)
f)
/INT
A LOW
end
will
pulse an
on
this
pin
detected
execution
at
of
instruction
the CPU's the
cycle
grab
attention
for
an
ongoing
g)
INTA
interrupt
signal
request.
(I)
acknowledges
With
this
CPU
to
the
I/O
device
that
its
and
interrupt it
will
request
has been
accepted
be
processed.
(0)
active read pulse
h)
/RD1
LOW level
for reading
data
from the
to
memory.
(O)
i)
/WR
CLOCK
data
the
memory.
(0)
permit us period
j)
Input
signal
that
will
the
desired
clock
for
LOW
the
to map CPU
operation.
(I)
that
or
h)
MEMRDY
Input
signal read
becomes
during
memory
write
cycle
until
the
data memory gets ready to accept the or put the data on the from the bus
bus. (I)
where
(I)
means
Input
and
(0)
means
Output
line.
aIn the
will
remainder
of
this
document
and
the
/RD
and
/WR
signals
be
mentioned
as
RD_bar
WR_bar
respectively.
-7-
>
IN
Cd o
p
13
2:
LU
IS
/\
/
0
LO V
to
\ /
A
_t
\
in
-4
>-
t,_
V cn
t^ut: O Z
LU LU cn
~
=3 CD CX
=> CD
A
LU z
CD
-3
N
\/
CO cn LU az 0 a CX
O ec
0 cc
k
=3
D CE O
>
3C
Ice |3E
1" lK
iC (_J O
z Z3 CC
c
UJ z
1
LU cn LU cr
cr
1
r2
z
t-^
-S
Uj CC
?=
cr cd
t-
er.
-i
3E
0
r
Figure
System Under
Simulation
-8-
The
control
signals
are
that
are
used
for
the to
proper
CPU-
Memory
modules
connection
not
routed
directly
some
the
memory
(see
to
but
a
they first
pass
through
additional
logic
Fig.
2.1)
This
which
access
single
signals
additional
unit
and
the two
exact
logic is called the memory bank select level design of this module is given
different
for
and
-
in
for
figure
the
2.2.
It
generates
write
control
signals
-
represented
memory bank
VMPO
RDO-
the
one
even
for
the
1>
OVMR
-ORD
R0DR<0>O-
>r^H
=L>
>>
-OWRl
-OWR2
HRO WORDO
O
.
Figure There
Memory
circuit
Bank
Select
Logic
and
is
another
the memory,
the
and
namely
MEMRDY
the
Handshaking
the
Unit,
access
of
that
generates
memory
cycles
it
of
is
responsible
proper
timing
.
the
buses
on
during
type
the
reads
or
This
system
circuit
depends
order
-
the
memory the
right
-
memory
that the
has
In
to
provide
timing,
specify
it has
some
other
inputs
usually
some
jumpers
that
number
of
wait
cycles.
DfiTR BUS
<15i0>
.11!
IEM0RY
-r
MEMORY
BANK
*2
BANK
.X
1>
"X
> "7
CPU
\.BDDB1>
HEMORT
TT wm
BANK
IB
SELECT UNIT
Figure
Memory
-9-
Banks
and
Signals
If
are
during
the
the
end
memory
of
access
the
clock
MEMRDY
signal
remains
LOW
after
the
inserted
paragraph
until
cycle, then T wait states it becomes HIGH. For more information refer
second
all
to
2.3.
can
The
memory
items
are
aligned
where
the
data
word
do
not
cross
boundaries. In the case that a word is into two consecutive bytes and it is banks
with
stored,
shared
it
is
divided memory
stored
by
both
stored
.
in bank #1
above
and
the LSByte
in
bank to
#2
2.4a)
The
clear
space,
address
where
is
stored
in the
can
low
order
and
in the
be
immediately
that
higher
(Fig.
2.4b)
Nevertheless,
at
even
it
should
clear
words
be
saved
only
memory
the
addresses
address
(e.g.
00H,
02H,
04H...).
out
of
From
bus
only
fifteen
the
sixteen
l-BRNK
BANK
*2-\
0
Byte
Byte
15
OQ H
Byte
1
Wore
Byte 2
1
02
04H
Worei
2
Byte
Q2
4 6
Hord Word
1.
1
MSByte LSByte
Q6H
08H
Byte
Byte
5
Woni Wor<i
Byte
mH
Word 2 Word
MSByte
LSByte
QRH
0C
3
4
Q6H
08
Byte 3
0E
Byte 4
Word 3 Word 3
MSByte LSByte
Figure
2.4a
Word
and
Byte
organization
Figure
2.4b
space
lines
of
reach
the memory
215
banks, giving
The
of
total that
goes
addressable carries
2x215
bytes
or
words.
line
the
least
significant
bit
and
or
(LSb)
is
a
the
address,
with
select either
unit
used
along
the
word
single
byte
to
access
may be
a
write
at
an
odd
or
even
address.
The
instructions
that
cycle
and gets
to
the
memory
LSb
are
given
in
a
Table
2.1
and
with
the
WORD
address'
combination
at
each
case
the
byte that
written
overwritten.
Every
time
that
byte
is
on
to
be
to
the
memory, LSByte
a
or
16-bit data
value
is
placed
with
its
The
memory
MSByte containing the byte that is to be bank select unit with the help of the
-10-
stored.
address'
least
significant
one
bit
and
the
signal
WORD
allows
-at
in this
the
case
only
that
memory bank
to
change
its
contents
address
the address bus indicates-, finally resulting in storing only the desired byte of the data bus.
Byte Instr STW WORD 1
Addr<0>
(B)
to be
<7:0>
overwritten
<15:8>
B
B
STB,L
STB,H Table The
0 0
2.1
read
Memory
cycle
write
instructions
the
signal
memory
a
always
read
asserts
WORD
to
HIGH,
that the
a
thus
whole
word
is
single
byte is to be
which
decides
data (see
figure
internally
bus have
4
time, This time the CPU 2.2) byte to keep, after the contents of
each even cases read
in the
(Fig.
been
for
loaded
more access
into
the
Memory
on
Data
Register
chapter
.
explanation read/write
structure)
The memory
2.5
(see
next
page
for
farther
description)
Cycle
(Word)
Reed DflTR
Cycle
(Word)
xyyy
xxxx
X
Write
noiH vrxwyy
yooooooocv
yxvxxy
vyyyyyy
xxxx
H[ii)H|-'<*;ywxxv
VMfl
y
X
vmh
RD
HU
HH \
RR
WORD
y
X
/
"V
WORD
Write
DflTR
Yxwra
wrara
xxxxxx/
Cycle
XXXXXXX
xxxx
Write Cycle
(Even Byte)
DflTR
xxxxxx
xxxx
(Odd Byte)
xxxxxxx"
R0DRE5SXSXXXX
xxxxx
RDDR<D>XXXXXX\
/XXXX
VMR
VMR
>^
RU
HR
RD
\_
WR
X.
WORD
WORD
Figure
Memory
Read/Write
Protocol
-11-
System Bus
The bus
Timing
consists
of
cycle
an
three
number
(3)
of
clock wait
cycles,
cycles
with
namely
T.
a
T1
to
T3,
and
undetermined
when
The
slow
wait
cycles
are
inserted
deal
There
some
idle
states,
not
(Fig.
2.6)
the
bus
is
used.
Walt
etatee
while
I
dock
for
interface
.
welting
Tl|T2|Tw|T3|Tl|T2|T3
T1|T1 Tl |T2|Tw|Tw|T3 Ti
Tl|
n_rijnjij"Ljnj"ijnjijnjx^
r Idle
Figure
There
cycles
etotee
between
bus
cycles
Sequence
events and a
of
Bus
Cycles
are
a
different
read
that
occur write
during
:
these
of
bus
the
for
memory
cycle
memory
a)
clock
read
At
the the
and
LOW-to-HIGH
transition to the
get
in
Ti
bus
the
After VMA
the
address
is
transferred
needs
address stable
,
that
address
after
to
signal
HIGH
tD
that
the
RD_bar
signal
on
is
asserted.
During
the
T2
data
with
the
expected
the
the
are not
the
CPU-Memory
after
which
is
t0
nanoseconds
of
the
RD_bar
on
signal
denotes
that
the
data has
and
stable
If the MEMRDY
second
signal
of
the
of
cycle
(T2)
cycles
inserted.
of and
Upon
reception
beginning
Register
address
T3,
the
data
and
are
the
the RD_bar
returns
VMA
signals
get
deasserted
state
and
the
bus
in
:
the the
high
impedance
cycle,
address
after
time
t0TD
b)
the
write
cycle
In
write
at
the
LOW-to-HIGH
transition
address
of
the
clock
in
and
Tir
the
is
transferred
to
bus
and
The VMA is
signal
first time
asserted
after
time
tSETUP
after
During the T2 tD signal is expected and, MEMRDY again, the Tw cycles are cycle, of T2 cycle. than the period longer LOW remains it if inserted the HIGH at asserted signal is MEMRDY beginning of the T3 The cycles have been inserted more or zero after and T bus cycle
from the time that the
asserted.
After it is received configuration. according to the jumper data are removed from the the and address the from the CPU, and the VMA and WR_bar buses data and respectively, address
signals
are
deasserted.
All
and
of
the
are
above
are
described
in
figure
2.8.
tA,
t0,
t0TD
t
-12-
memory
dependent
timing
characteristics
as
table
2.2.
tSETOP
and
they tD
appear are
of
in figure 2.7
standards
and
explained
on
in
bus
and
depend
the
physical
implementation
the bus.
-tfi-
RDDRE5S-
HDDRES
tD
WR
tH-
C5.
^
-
tD
tOTD
,5FTUP
tSETUP DRTR.
to
<
READ CTCLE
DAT
~!
WRITE CTCLE
>
Figure
Memory Timing
Characteristics
Read
Meaning
Access Output Time Enabled to
tA t0
t0TD
Write
Output
Valid
Output
3-state
from Deselection
Meaning
Write Time
tw
Table
Timing
I
I
Characteristics
and
their
Meaning
Tl
CLOCK ADDRESS
T2
T3
CLOCK
!
RDDRESS
Tl
T2
T3
VMR
VMR
_
_
TO
DflTR
MEMRDT
o
XXX)
RERO CTCLE
ORTR
memrdt
^ xyyi
>
WRITE CTCLE
Figure
System Bus
Timing
-13-
The
Memory Organization
a
and
the
Stack
We took
was
glance
on
also
first
and
told
that
addressable
of
occupies
2x215
space
is
given
exact
organization
The
of
first four
the
(4)
memory
contain
addresses
interrupt
I/O
(6)
and
routines. The next six (6) words are used for mapping addresses, like a PIA and a UART in our case. The next six word locations are reserved for possible system expansion, immediately after these, exists the space for a Monitor
as well
Program
as
the
space
interrupt
remaining
available
service
space
routines
of
while
the
memory
In
our
is
eo.
02. GU.
15
8,7
R...t
to
no
the
user.
case
Interrupt
Request
there there
is
are
Monitor
simple
.
Program
routines user
some
but for
Opcoda Error
Rddreea Hleellgnnenl
PIR Control/Stotul
06.
interrupt
place
service code
The
should
08,
BR 0C>
BE.
Reg
his
0300H
CPU
after
which
loads
a
starting from address is the address that the into the Program Counter
This
user
RESET.
address
can
be the the
10. 12.
m. 16.
URRT Control
URRT Statue
Rao.
Rag.
changed contents
by
the
by changing
contain
Heaarwad
Raaarwad
of
the
LSByte
memory
which
locations
address
.
IB.
$207h
MSByte
and and
$209h
1R,
1C,
of next
the
(see
paragraph)
Counter
is
(all
always
1E 20.
incremented instructions
stops
by
are
when
two
the
16-bits)
it
meets
execution
and
it
HLT
only
the
the
of
lrE
260. Interrupt Sarwlce Routlnaa
command.
After the
this
command,
CPU
remains
idle
in
until
it
and
is
again
externally
The
reset. words
The
not
stack is in bytes.
organized
2FE
306. Uaar'a Speca
Stack
Pointer
always
(an
internal to
CPU
register)
points with
even
addresses,
the
address
that
and
will
starting be first
the FFFE,
Stack
161.768 Butaa)
loaded
into
the
it
represents
top
of
stack.
Once
with
the the
Pointer
address
is
loaded
of
first
(Top
Stack)
to
there
is
no
Figure
limitation
stack
of
the
space
that
the
Memory
Organization
is
supposed
include.
should collide
Therefore
the
programmer
be very
with
careful
in the
the
use
of
or
the
stack
because
it may
other or
segments
(data
incorporated two commands, LDSP (Load Pointer, there have been where (Store the Stack Pointer) STSP and the Stack Pointer) of a contents with the loads the Stack Pointer former the Stack the the contents of stores latter the and register
-14-
code)
after
extensive
use.
For
loading
storing
Stack
Pointer the be
another
used
to
register. we a use
We
need
to
store
the
we
Stack
shift
Pointer
in
to
cases
that
multiple
stacks
and
from
one
during
to
program
execution.
stacks
The
LDSP
command
can
also
create
multiple
in
the
memory
when
area.
The
stack
is
useful
for
a one
saving the
subroutine
of
CPU
registers
(R1-R7
we
and
PSW)
to
in
the
case
of
call
or and
need
temporarily
task.
save
the
registers
use
it
for
another
Every
stack
time
that
pointer
gets
the
next
available
location.
stack
then
the
pointer
something is popped off the stack, first increased by two and then
are popped off
the
data
that
it
is pointing to
(Fig.
2.10)
1FEH
(topi
1FEh
IFCh
07h
1FCh
IFEh IFCh
PUSH Rl
POP
*
R2
=>
2 Oh SP = 01FEh
>
(bo t ton)
2 0H
20ri
SP=01FCh R107h R2=FFEFh
SP=Q1FEh
R1-07h R2=07h
R1=07h R2=FFEFh
Figure
2.10
Stack
Operation
Exception
Handling
most
One
of
the
important to
features
of
microprocessor
today
exist
is
its
a
ability
taken
program
handle
the
interrupts.
whenever
Interrupts There
are
special
actions
by
or
CPU
certain
conditions are
within
the
computer
system.
two
general
classes
of
interrupts.
are
usually
caused which
by
interrupts
are
interrupts that the user or I/O devices and the internal caused by a CPU malfunction due to an
The
external an
overflow
unrecognizable
opcode,
or
stack
violation. non-maskable
Each
interrupt
on
can
be be
either
maskable
or
depending
maskable
how
important
can
this
interrupt is
The
interrupts
the
than one
suspended
by
the
special
Flag
has
has
case
in the PSW,
to
Interrupt
more
maskable
be
provided
for
one
interrupt
maskable
there
is
only
-15-
which
is
one
not
only
an extraordinary case, especially when there interrupt source in our system (i.e. us) non-maskable
is
The
interrupts
the
have
always
exist :
the
highest
priority
and
in
It
our
system
following
(a)
CPU
RESET
and
is
up
an
external
interrupt
RESET
which
upon
initializes the
the Once
activation
starts
the
program
execution signal
(HIGH)
HIGH
of
the RESET
at
pin.
The
is
required
to
stay
RESET
for
least
three
(3)
clock
cycles.
the
interrupt is detected, the CPU clears all the Flags except the zeroes the registers of Interrupt Flag which is set to HIGH, register file and loads the Program Counter with the the address contained in the memory location 00H. This address has
saved
the
number
0200H
for the
which
is
the
address
of
the
interrupt
the to
of
service
routine
the
RESET.
and
Inside
program
the
routine
Interrupt
Flag is
where
cleared
the
is
transferred
The
contents
the this
location
routine
user's
program
begins.
could
look
like
this
ADDRESS
INSTRUCTION
<-
STPSW AND
LDPSW
Rl
Rl
,
PSW
Rl, 01111b
Rl Rl,03h Rl,00h
ALW,R1
IF
PSW
<<-
0
Rl
Rl
<-
0300H
to
Jump
(Rl)
code)
(program
opcode is read into invalid combination between the opcode and the IMM and SIGN fields is present. The Program Counter is loaded with the contents of the memory address 04H.
(b)
opcode
error
raised
when
an
invalid
or
when
an
(c)
only
address
misalignment with
raised when
we
try
to
access
an
odd
memory
on
location
even
the
LDW or
operate
addresses.
(PC
<-
(06H) )
The
interrupt
maskable
request
line
of
the
CPU
(/INT)
has
.
represents
the
only
interrupt
and
each
that
our
system
It
at
is
low
end
level
of
active
signal
it
is
examined
by
the
CPU
the
the
execution
of
instruction.
If
it is found
occur
stable
at
the
LOW
level
then
the
following
events
(1) (2)
If the
Interrupt
Disable
Flag is
at
logic
one
(IF=1)
equal
the
If
interrupt the
request
is
ignored.
zero,
Interrupt
prevent
Flag
equals
it
is
set
to
to
further
interrupts
service
from
occurring
starts
until
the
interrupt
the the
present.
routine
(3)
contents
of
the
Program
Counter
are
stack.
-16-
(4) (5)
(6)
The The
PSW
is
stored
onto
the
stack. of
CPU
reads
the
contents
new
the
memory
with
location
02H
The
which
become the
Program
Counter
(PC)
the
program
execution
continues
code
pointed service
by
the
.
new
PC
(start
of
the
interrupt
routine)
One
routine
of
service
should
be
the
modification
of
the
Interrupt
Flag
so
that
interrupt request can be processed, thus supporting nested interrupts. The last instruction before the return of an interrupt service routine should always be :
a new
POP Because
PSW
a return off
there
is
not
from
stack
interrupt
(RETI)
and
instruction
stored restore request
.
which
would
pop
the
use
the
and
PC,
the the
or
the
programmer
must
the
above
instruction
flags
case
to the
a
state
they
were
In
that
the
new
interrupt
"POP the
PSW"
request
before
the
after
above
flags,
of
gets of
operation
CPU
will
the
normal
interrupt.
program
This
include
will
the
now
saving
show
the
flags
of and
and
the
counter,
or
which
the the
address
stack
the
above
instruction
the
one
after
it,
into
the
will
routine
(this
of
one
completion
the
will
execution
of
the
new
interrupt request,
and
service
routine
will
pop
off
the
flags
the
program
counter,
old
and
continue
by
returning the
which,
counter
execution will
to
interrupt
off
service
routine
by its turn,
again
pop
the
flags
and
the
program
continuing
with
initially
interrupted
program.
-17-
The
Trying
Instruction
to follow the RISC
with
Set
designing
five
rules,
an instruction instructions from can instructions
set
was
created
which
only
the
of
(25)
directly
remainder registers
access
the
during
cycle.
The
or
operate
between
The
The
instructions
instruction
flow
control
and
the
fetch
cycle
set
includes
and
instructions
memory (Table 3.1)
Our
for The
as
data data
manipulation
program
-arithmetic
logical-,
support
handling,
.
and
stack
have
to
be
point
integer
in
the
numbers
range
(always
.
considered
system
2's
no
complement)
(-215,215-1)
or
has
to
of
floating
All
system'
manipulation
string
a
handling
long,
fetch
facility.
equal
the
word,
instructions
thus
:
are
16-bit
uniform
the
s as
providing
cycle
three
stages
follows
Load
Load
of
1)
the
of
Memory
the
Address
Register
with
the
contents
Program
Counter.
with
2)
the
Memory
memory
.
Data
Register
the
contents
the
the
location
pointed
by
the
the
Memory
Data
Address
Register
(Memory
Access
Cycle)
in
3)
Pass
instruction
to to the
contained
Memory
and
Register
operands
instruction
two
decoder
.
the
the
temporary
registers
Increase
Program
Counter
by
(2)
The execution cycle is much more complicated and it is dependent. In the next chapter, the different instruction also are given. of each instruction micro-operations In
shown.
table
3.1,
and
the
Rs2
instructions
represent
and
their
actions
are
Rd,
the
Rsl
the
and
CPU the
registers
RO
to
are
R7
Rd
is
destination
register
Rsl
and
Rs2
the
source used
registers.
In
some
instructions,
to be
pushed
register
the
or
Rd
register
is
to
encode
the
register
popped
to/from the
and
.
the
Rsl
to
encode
the
branching
The
instruction
formats kinds
one of
There
are
three
instruction
and
formats.
The
register-source,
the the
short-immediate
the
long-immediate.
The
function
and
of
each
is
shown
below
in
the
figures
3.1,
3.2
three
3.3 instruction
bit
respectively-
common
elements
opcode
and
register
fields.
field
has
five
(5)
bits
and
can
encode
up to 25(=32)
different
instructions
while
the
-18-
INSTRUCTION
ACTION TAKEN
IMM
SIGN
CODE
Add
with
Carry
with
Rd Rd
Borrow
<<-
Rsl Rd + Rsl
Rs2
Rs2
CF
+
0
1
ADC
(IMm1)
-
CF
2. 3.
Subtract
Rd Rd
Rd Rd Rd
<-
CF
-
0 1
<<<<-
Rd
Rsl
(IMm)
AND Rs2
CF
Logical AND
Rd AND Rd AND
Rsl
(IMm) (Imm2)
(IMm) (Imm) (IMm) (Imm)
0 1
1 0 1 1 0 1 1 1 1 1
xb
0 0 0 0 0
1
SBB
AND
Logical
OR
Rd Rd Rd
<<-
OR Rs2
Rd OR Rd OR
Rsl
<<-
0 0 1 0 0 1
0 0
OR
5.
Logical
XOR
Rd Rd
XOR Rs2
XOR
<<-
Rd XOR Rd XOR
Rd
6. 7. 8.
Shift Shift
Rd Rd Rd
<<-
SHLL SHRL
SHRA
Shift
<-
0
V
9.
10. 11. 12. 13. 14 15. 16. 17.
Rd Rd (sign
High
Low
<<-
Rs2]
,Rs2) ,Rs2)
X X
0 1
D
D
X X X
Imm. Imm.
extended) Rd <Rd
PSW
<<-
(,D1
D
X
LDLO
LDPSW
M[Rsl
(LSB) (MSB)
M[Rsl
Rs2] Rs2]
<<-
Rd Rd
STW STB
STPSW
1
Rd
<-
PSW
Branch
PC Condition Always
On
<-
Rd
JMP
Rsl
000
001
Carry
Overflow
010 011
100 101
On On
On
Negative
Zero
On On
On
No
Overflow
110 111
18.
Call
No
Carry
(SP)
SP PC
<<<-
Positive
Subroutine
PC SP
Rd
-
CALL 2
19.
Return
SP
PC
<<-
SP
RET
(SP)
Table
3.1
The
Instruction
Set
integer 2Integer
in
range range
(0,63)
(-32,31)
in
3Integer in
range
(1,8)
location
pointed
Rs2"
4M[Rsl+Rs2] means "the contents of the memory and sum of Rsl by the number which is the
not
considered
(it
can
be
any)
Rs2
fields
(see instruction
formats)
contain
immediate
the
IMM
data
and
7D
means
that
SIGN
1-bit
fields
are
considered
as
Data
-19-
15
11 10
opcode
Rd
nned
te-8
opcode
of
Immediate-8
IMM SIGN
field with the binary representation of the mnemonic instruction. 8-bit field with immediate data. Now the IMM and SIGN 1-bit fields contain the two MSbits of the data. In the above instruction format it is not used, but instead, data are contained.
the IMM 1-bit
5-bit
As the
the
field,
it is
not
used
but it
contains
part
of
8-bit
immediate data.
Figure destination
address
3.3
register
The
field
three
(3)
bits
and
it
can
instruction formats, we can used in cases where two or more actions may be taken (e.g. ADC, SBB, LDB) , in Table 3.2. The opcode, independent of the action, is always the same. What may change is the IMM and SIGN 1-bit fields in some instructions, or the Rsl 3-bit field in some others. This depends on the syntax of the instruction when it is written in assembly language. For the case of the branch instruction for the opcode is always constant and the (01111B) example, condition is given by the 3-bit field Rsl. Here are some in and machine commands language respectively. assembly the instructions are translated the Observe assembly way
now
registers.
the
explain
why
single
mnemonic
is
according
to
their
syntax
Assembly
Machine
opcode
Language Rd
IS
xx
Rsl
Rs2
JMP
C,R7
01111
JMP
111
R7
001
xxx
Jump
to
on
Carry
address
Set
R7
the
contained
by
JMP
ALW,R7
01111
JMP
111
R7
xx
000
ALW
xxx
Jump
the
Always
address
to
R7
contained
by
ADC
R7,R5,R2
00000
ADC
111
R7
008101 R5
010
R2
R7
R5+R2+CF
ADC
R7, 011011b
00000
ADC
111
R7
10
011
011
R7
R7+01BH+CF
Immed-6
XOR
R7,R5,R2
11100
XOR
111
R7
00
101
R5
010
R2
R7
R5
XOR R2
always
zero
in ADC
and
SBB
instructions
-21-
20.
Push
to
Stack
(SP)
SP
<<-
Rd
PUSH
-
SP
Rd
Register
PSW Rl R2
21.
000 001 010 Oil 100 101 110 111 Pop from
Rd
R3
R4
R5 R6
R7
St ack
SP Rd
<<-
SP
POP
(SP)
Register
PSW
Rl R2 R3
R4
R5 R6
R7
Load
Stack
Pointer Pointer
SP
Rd
<<-
Rd SP
X X
V
LDSP
Store
No
St ack
X X
X
STSP
NOP
Opera tion
25.
Halt
HLT
Table
The
Instruction
Set
(continued)
15
11 10
7
IMM
6
SIGN
32
opcode
Rd
Rsl
Rs2
opcode
5-bit
of
the
Rd,Rsl,Rs2
3-bit
source
IMM SIGN
field with the binary representation of the mnemonic instruction. fields with the addresses of the destination (Rd) and (Rsl,Rs2). registers for immediate In used addressing. the field above
.
format it is always zero (0) field that distinguishes if the immediate data is signed not. It is always zero (0) in the above instruction format.
Figure
The
register-source
instruction format
15
11 10
7
IMH
6
SIGN
0 Innadlota-6
opcode
Rd
opcode
5-bit
of
the
binary
representation
of
the
mnemonic
Immediate-6
jMM
SIGN
field that contain immediate data. immediate for In the above used addressing. field instruction format it is always one (1) 1-bit field that distinguishes if the immediate data is signed or not. The immediate data are considered signed if it is one 6-bit 1-bit
.
(1),
Figure
unsigned
otherwise.
3.2
The
short-immediate
instruction format
-20-
XOR
R7, 111111b,
11100
XOR
111
R7
11
111
111
R7
R7
XOR
FFFFB
Immed-6
extended
sign
immediate
XOR
R7, 111111b
11100
XOR
111
R7
10
111
111
R7
R7
XOR
03FH
Immed-6
The table
opcode
assignment
of
the
instructions
is
given
in
3.2.
xxxOO
xxxOl
xxxlO
xxxll
ADC
SBB LDB STB
SHLL SHRL
SHRA
LDW
STW
JMP LDHI
CALL
AND OR XOR
RET PUSH
LDLO
LDSP
STSP
POP
Table
3.2
can
Opcode Assignment
also
Other
with
instructions
specified
be
implemented,
Here
are
some
indirectly,
of
the
instruction
set.
them that
one
usually
finds
in the
instruction
sets
of
other
CPUs:
Instruction
Implementation
(by
move
our
Instruction
Set)
Rs
to
Rd
Rd Rd
of
Rd Rd Rd Rd Rd Rd
<<<<<-
Rs
Rd
+
+
-
R0
increment
decrement
complement
Rd
R0
(1D) (1D)
Rd
negate
clear
Rd Rd
Rd R0
XOR
+
(-1D)
Rd
<-
RO
(CF=0)
exchange
Rd
and
Rs
Rd Rs Rd
<<-
Rd XOR Rs Rd XOR Rs Rs
XOR
<-
Rd
The
The
addressing
supported
modes
addressing
modes
are
only two
a)
Indexed
-22-
i
and
Register
For
a
Indirect
ii)
b)
Linear
byte/word array
Immediate
case
This
a)-ii
.
is
an
an
interesting
example
with
way to
elements
Suppose for
of
that
R1=0FFH
easily and it
:
access
array
the
contains
base
value
address
array
and
256
elements.
When R2
takes
any
between
00H
0FEH
then
the
instruction
LDW
R5, [R1+R2]
the
contents
element into any array array is an array of bytes, command (LDB) and specify which
of or
can
easily
R5 to
.
load
use
register we
In the the to
case
that the
have
we
load byte
(MSByte
byte
want
keep
LSByte)
is
The the
immediate
should
programmer
mode
little
on
tricky,
part. always
so
attention
that
First,
be
the
destination
No
and
source
registers
must
same.
other
immediate data
be
longer than
cases they have to be only 6-bit s immediate operand into any of the CPU registers, we in-structions that were incorporated for this two only: LDHI and LDLO. The instruction :
LDHI
R4, 1010111b
register
of
R4
with
the
binary
number
1010011
leaving the rest of the In exactly the same operation for the LSByte of the registers sign no loaded is unsigned i.e. both cases the operand that is instruction for those format place. The extension takes
register
unchanged.
LDLO
performs
.
instructions
instruction
is
the
long-immediate,
the
where
the
In
LSByte
of
the
now, SIGN
contains
immediate
data. only
the
the
that
sign
that
the
to
immediate be
used
operand
show
is
6-bit in
long,
ADC
'
cases, the
field
has
to
IMM
whether
operand
has
1'
to
be
SBB
extended
or and
not
(not
applicable
and
instructions)
immediate
For
same
the
field has
.
to
be
two
always
(short-
instruction
even
number
format)
the
example,
though
as
following
commands
have
the
binary
are :
immediate in the
that
represented
the
actual
numbers
are
completely
different
XOR
R3
,111111b
;
s
R3 R3
R3 R3
XOR
0FFH(
63D)
XOR
R3, 111111b,
can
XOR FFFFH(=-1D)
we
Sign from
extension
also
happen
of
in the
are
case
load
byte
LDB
sign
the
command
the
registers
(with
the
The
data
8-bit
long.
extension
place
in
the
Add,
is
Subtract
obvious.
and
Shift
could
instructions.
a
as
shift
reason
What
left
to
(-8)
a
times
mean?
shift
right?
But how is
shift
then possible to
operation?
left
command
execute
right
Because
we
wanted
-23-
our
instruction
set use
to be non-ambiguous
of
prohibited
commands.
negative
the
compilers,
for
we
sign
extented
can
operands
mean
the
above
of a
So the
subtraction
never
addition
number, if and only if the immediate addressing mode is and the used, shift left operation can never be a shift right for a negative number of times. Figure 3
.
shows
how the
ADC SBB
XOR OR AND LDW LDB
each
instruction
The
affected
affects
Flags.
not
Interrupt
Flag is
the
1 1
1 1 0 0 0 0 0
0
?
by
of
execution
instruction.
set
or
The
clear
0 0 0
storing
register, Interrupt load back
contents
the
PSW
modify
the then
the the to
0
1
?
Flag bit
the
PSW
LDB(S)
STPSW LDPSW
of
that
set,
register.
about
we
Concluding
instruction
mention
STW
STB
JMP
have
that
it
II
was
greatly
influenced
RISC
sets
by
the
Berkley's
&
as
.
RISC
instruction
appear
they
in
[KAT83]
I
1
1 1
1 1 I
Meaning
&
SHRA SHRL
I
1
Test Not
Set
if
True,
Clear
Otherwise
affected contents ones
Figure depend
on
3.4
New
&
previous
In
the
restriction.
The
integers
reason
but
instructions there is also another shifting immediate data not only have to be positive The they also have to be in the range (1-8)
.
for
Of
no
that
is
make
we
because
more exclude
hardware
eight
number
element
called
per
Power
clock
Shifter
cycle. makes
cannot
than
(8)
of
shifts
course, sense to
zero
because it
shifts.
use
the
shift
command
to
the
the
Another
of
instructions
for
LDB
commands
register
is
the the
that in
includes
These
are
accessing
memory.
STW,
the
STB,
LDW
and use
as
shown
Table
3.1.
mode
These
where
instructions
address of
the
indirect addressing
of
by
the
result
the memory to read or write is determined addition of the the contents of the two
.
source access
Rs2 For Rsl and the registers, (LDB and STB) we have single byte
instructions
also
that
which
to know
memory.
byte
sign
this
is
(MSByte
after
or
LSByte),
its
and
whether
it's going to be
This
extended
loading
-24-
from
the
is encoded into the IMM 1-bit field where the '1' '0' digit means the MSByte while the digit means binary the LSByte of the Rd register. for STB the command, Especially attention has to be paid in its implementation because if the result of the addition of Rsl and Rs2 happens to be even
information
only the memory bank #1 has to be enabled because it the even addresses, in the case that the while result is odd only the memory bank #2 has to be enabled. We have, finally, to say that before the byte has been put on the data bus it should have the right position in the Memory Data
number,
represents
Register
exact
(MDR)
to
reach of of
the the
desired
above
memory
.
implementation
command,
see
bank. in
(For
the 4
chapter
the
micro-operations
the
STB
command)
The
Processor
user
Status Word
visible and
Another
Processor
accessible
.
CPU
register
is the
of
Status Word
(Fig.
are
3.5)
Only
the
five
(5)
LSbits
its
sixteen
(16)
bits
to modify its Flags with We have to use a register that time Flags
can we
used, giving the ability to the user the use of no more than one register.
because
there the
are
no
instructions
every
of registers
access
store
PSW.
Therefore,
on
seven
available
(remember that R0
can
is
always
zero)
can
modification
any
the
new
be
made.
The
PSW
then
be
the
loaded
with
the to
contents pushed
of
that the
register. stack
The
contents
of
the PSW
can
also
be
.
onto
as
with
any
of
registers
Rl
R7
!>MxM>MM>W>ro&<lXi
Interrupt
Flsg
If
1 1.
Enebla
IF Bl
Disable
Nsgotlua
Flag
on
Nsgotius
rasultl
Zsro Flag
an
Zsro
raault)
OwsrfloH
Flag
If
raault < >
-2'*
op
215
raault
-11
Carry Flog
Figure
The
some
Processor
Status Word
to
s modify the instructions that
results.
PSW'
There Flags
we and
are one
of
course
other
ways
of
them
is
:
by
executing
some
know
they
affect
the
Flags,
producing
dummy
The
instruction
for
example
ADC
R0
R0
R0 the
clears
the
only only
one
instructions
register.
flag, by executing changing the contents of any The following instruction, however, affects (clears)
carry
flag
and
sets
zero
and
without
the
carry
flag
-25-
ADC
Even
RO, 000001b
after
if RO is intermediate
seems
zero
the
execution
of
the
instruction,
is
result
that
one and
the
ALU
produces
01H
work
actually,
this to
is the
that
affects
the
PSW's
Flags.
way
all
be
faster
smarter
but
it
doesn't
the
flags.
3.5
Assembly
The
syntax
and
instruction encoding
first
mentioned
instruction
3.2
the
will
paragraph syntax
now
in
the
complete
table
of
instructions and their encoding to the machine is in binary representation will be described. of The mnemonics the instructions that are used for their representation in the assembly language have already been given in table 3.1. As everyone knows it is a lot easier to
of
language
which
write
program
in
we
assembly than
need
in
machine
language
because
and
the
only
of
things
to
know
are
will
the
mnemonics
the
the
of
syntax proper
the
instructions
which
later
interpret
.
to
instruction formats
and
the
instructions,
to
of
thus,
is
The
syntax
with
their
encoding
meaning
the the
machine
language
and
comments
about
used.
the
parameters
the
symbols
that
are
INSTRUCTION
SYNTAX
M.S.
76543
Byte
210
Rd Rd
L.S.
7
Byte
543
Rsl
210
Rs2
1.
ADC
a)
ADC ADC
Rd,Rsl,Rs2 Rd,imm
00000 00000
b)
0 0 1 0 from
to
Immed-6-unsigned
000 111
Rsl
000
111
Rs2
(0D)
(63D)
SBB
a)
SBB SBB
Rd,Rsl,Rs2
00001 00001
Rd
Rd
0
1
to
b)
Rd, imm
0 0
Immed-6-unsigned
000
111
Rsl
000
111
Rs2
(0D) (63J
AND
a)
AND
Rd,Rsl,Rs2
b)
AND
Rd, imm
0 0 1 0 from
to
Immed-6-unsigned
000
111
(0D) (63r)
(-32r) (31L,)
c)
AND
Rd,imm,s
10100
Rd
1
to
Immed-6-signed
from
Rd,Rsl,Rs2
100 011
Rsl
4.
OR
a)
OR OR
11000 11000
Rd
b)
Rd, imm
Rd
0 1
to
0 0
Immed-6-unsigned
from
000
111
;)
OR
Rd,imm,s
11000
Rd
1
to
Immed-6-signed
100 011
Rsl
XOR
a)
XOR
XOR
Rd,Rsl,Rs2
b)
Rd,imm
0 1
0 0 from
Immed-6-unsigned
000
111
000 111
to
(0P) (63D)
Table
3.3
Instruction
syntax
&
encoding
-2
6-
C)
XOR
Rd, imm,
11100
Rd
1
to
Immed 6
signed
from 6.
100 011
(-32J
(31n)
unsigned
SHLL
a)
SHLL
Rd, imm
00010
Rd
1
to
Immed 6
from 7.
SHRL
a)
dD)
(8n)
unsigned
SHRX
Rd, imm
00110
Rd
1 to
Immed 6
from 8. SHRA
a)
000
001
UD) (8ri)
SHRA
Rd, imm
01010
Rd
1
to
Immed 6
unsigned
from
do)
<8D)
000
Rs2 Rs2 Rs2 Rs2 Rs2
9.
10.
LDW
a)
LDW
LDB
a)
LDB
00011
,h
Rd Rd Rd Rd Rd Rd
01000
unsigned
1 1 1
1
0 1
1 1
Rsl
Rsl Rsl Rsl
b)
c)
Load High Byte (MSB) LDB Rd, [Rsl+Rs2] , hs Load High Byte (MSB) LDB Rd, [Rsl+Rs2]
,1
01000
signed
01000
unsigned
d)
11.
LDHI
a)
01000
signed
Load LDHI
Low
(LSB)
10010
Immed -8 -unsigned
from
to
0
1 0
1
X
X
0 1 0
1
X X X
X
000 111
000 111
xxx xxx
000
111
12.
LDLO
a)
LDLO
Rd, imm
10010
Rd
Immed -8-unsigned
from
to
000 111
xxx
LDPSW
a)
a) a) a)
LDPSW
Rd Rd
Rd
01001
Rd
STPSW LDSP
STPSW
LDSP
Rd
Rd Rd Rd
xxx
xxx xxx
X X X
xxx
xxx
STSP
STW
STSP
STW
Rd
a) a)
18.
STB
b)
19. 20.
CALL
PUSH POP JMP RET NOP HLT
a) a)
Rd, [Rsl+Rs2] STB Rd, [Rsl+Rs2] Load High Byte (MSB) LDB Rd, [Rsl+Rs2] Byte Load Low (LSB)
CALL PUSH Rd
Rd
Rsl Rsl
Rs2
,h
Rd
Rd Rd Rd Rd
1 1
X X X
X
0
1
X
X
Rs2
Rs2
,1.
Rsl
xxx xxx xxx
xxx
a) a)
a) a)
POP
JMP
Rd
X
X
Condition, Rd
Rsl
encodes
Rd
.ion
Rsl
the
condit
Rd Rd
Rd
X X X
X X X
xxx
xxx
a)
xxx
Table
Instruction
syntax
&
encoding
(continued)
-27-
The
The
Central
of
Processing
is
that detail
where
Unit
Central
chose
heart
.
Unit
parts
(CPU)
of
This
of
the
we
Processing
to
rest give
of a
description
our
the
more
than
the
the
system.
The
carried
down to
the
a
Register
are as
Transfer
Level
(RTL)
the
key
component
is
(parallel)
register,
other
that
is,
storage and
device
for
words.
There
such
also
combinational
sequential
usually described as boxes with a specified operation. Between these boxes runs a group of lines that carry the data and referred to as buses. In this level, there is a degree of abstraction, in the sense that we don't see what's in inside each of these usually
are
multiplexers,
ALUs,
counters
boxes,
and
quite
soon
we
will
see
that
box
may
sometimes
represent
more
than
one
component.
The
The
CPU
CPU
structure
steps
and
of
some
In the first as an entity is given in figure 4.1. its design, only the necessary registers were placed units like the Arithmetic Logic Unit the (ALU) ,
Control
Unit
(CU)
and
the
Interrupt
are
Unit
all
(IU)
The
registers
that
we
decided
:
to
incorporate
1 6-bit s
and
are
the
following i) ii)
iii) iv)
v)
vi)
Memory
memory
Data
read
Register
and
(MDR)
a
holds
write
the
.
data
after
before
that
we :
memory
:
want
Memory
memory
Address Register
(MAR)
keeps be
holds the
write
address
or
of
the
location Counter
to
to
read
from.
next
Program
program
(PC)
to
:
the
address
of
the
instruction
executed.
always available : contains stack
Stack
Pointer
(SP)
the
it
the
memory
data
address
that
is
next
position.
ALU
that
Front
Input
will
Registers
(Ra,Rb)
operands
they
:
keep
the
be
used
as
in the ALU
operations.
register
the
This
contents
(Ri)
this
as
loads
stage
serves
delay
at
before
the
Far
End
Immediate
Register. the
same
delay is
that
place
time
absolutely loaded is
and
or we
essential
because
which
the
instruction
yet more
decoding
part
of needs
is
the
taking
data
Far
don't
or
know
even
is
End
useful
not,
if
it
some
further
processing.
viii)
Immediate
Register
(Rixnm)
been
End
contains
raw
immediate
their
data
after
they
keeps
PC
have the
or
processed
during
or
transfer
from
the
:
Front
Immediate
of
Register. ALU
of
ix)
Node
Register
(Re)
as
result
an
PS
(Power
Shifter)
such
operation
the
.
contents
other
registers
the
Word
and
:
SP
x)
Processor
Status
(PSW)
this
register
keeps
the
-28-
en
to
V
a.
-?
t
cr
t
z
LU
CO LU
z cc LU
1-
LU o o
cn cn
LU
cc
cc
DC
X LU
u a. o
o
a
a CD
?-?J*
? ?Iv
t:
(6) U0M
h5t=h5
0-'
Figure
The
CPU
structure
-2
9-
flags
(Carry,
Overflow,
was
Negative,
Zero
and
Interrupt)
The Power
considered
as
Shifter
another
mentioned
CPU the
component
were
design
speed
where
the
flow
data
and
paths
assigned
to
up
the
paths
connect
the
various called
The
and
data
they
usually
A
have the
control
so
is
data
activated
over
by
signal,
When
allows
data to be
the
or
we
the
reach
data
a
inactive,
case
data
more
is
data
effectively blocked.
paths
control control
In
the
that
,
two
input
two
or
node
(point)
then
need
more
signals
to
distinguish
which
data
a
path
will
be
transferred to the
not
output. switch
So,
sometimes
control
node
may be
just
single
but
something
more
complex.
4.2
The
Control
Unit
The function
control
unit
implements
of
fe
,
or
group
the
functions
function unit, that
flf f 2,
ldlo
fn.
a
Every
time
is
executed
by
control of events
there
is
sequence
is transferred to the
and
control
points
'RESET
by
the
control
unit
is
that
the
CPU 4.2.
operation
as
shown
in
Interrupt
figure
tion the
It
consists
of
other
sub-functions
such
as
the
instruc
each of
execution
of
the
interrupt
fstch
and access memory our CPU In states. generally the CPU : states possible four are there
services,
sxscu
ts
idle,
After
interrupt,
the
the
power
fetch
and
execute. system
up
of
the
(i.e. CPU
RUN
signal
goes
HIGH)
to
the the
is
always
initialized
idle
state
state
until
it
is
the
and
reset.
It
then
enters
externally interrupt
service
until
the
interrupt
routine continues
is
called
then
it
by
changing
fetch
and
between
states,
the
If
starting
always
the
of a
fetch.
program
during
HLT
the
execution
the
command
is
then
Figure
the
processor
enters
4.2
state
reset.
until
State
Sequence
enters
it
-30-
then the
it
The
continues
by fetching
routine
.
and
commands
of
interrupt
service unit
control
generates
other
a
an
clock
which
is
CPU
distributed
executes
a
to
all
the
CPU
components.
When
the the
freezes
until
memory it
read
or
memory write,
the
MEMRDY
internal
from
clock
CPU-
receives
unit
signal
Memory
handshaking
giving
to
all
components
the
illusion that only one cycle has elapsed while at least three cycles have occurred in the external CPU environment (Fig.
2.1)
Inside decoder
the the
control
unit at
there
is
also
an
instruction
cycle. and
which
is
enabled
the the
third
fetch
It
interprets
operands
instruction,
that
Unit
or
conditions
are
enclosed some
addressing in the
other
mode
the
16-bit
word.
The to
Control
generates
signals,
shown
internal in
figure
or
it,
except
the
control
signals
that
state
are
4.1. the
the the
These to
signals of
are
used
for the
coordination
for CU
issuing
the
ex_end
interrupts,
in
of
like 4.1.
the
The
HIGH
four first
signals
of
that
the
pases
IU
figure
which
these
signals cycle
is
of
signal
becomes
after
the
last
execution
every
that
opcode_error opcode
signal
field
and
used
contained
instruction. The second is informs the interrupt unit that an invalid binary representation
are
the the
and
the
are
third both
fourth to to
signals an
the
write_mem
and
word
which
assert
interrupt
to the
condition
whenever
word
is
attempted
be
written
memory
at
an
odd
address.
The
This
interrupt
unit
unit
is the
four
the
that
portion
of
the
CPU
which
is
responsible
for
and
issuing
INT
as
the
interrupts.
Interrupt
It
has two
from the
external control
inputs,
unit.
RESET
also
bar,
LSbit
and
inputs
It the
has
and
Inputs
the
of
Disable
Flag
is
(IDF)
bit
of
PSW
the
MAR.
an
Every
generates
time
interrupt
the
two
signals
for
control
this
unit
first
execute
one
changes
the
processor
state
from
idle,
fetch
or
to
the
interrupt
type
or
of
and
the
second
signal
contains
information
signals
about
the interrupt
(reset,
.
external
interrupt,
more
opcode
error
address
misalignment)
single
These
two
or
may
not
be
the
necessarily
number
lines the
but
to
RESET
two
according
a
counter
to
of
states
that
of
need
be
encoded.
For
used
the
case
interrupt,
LOW
has
of
been
which
is
and
enabled
by
the
the
to
HIGH
transition
clock
the
RESET
and
line
once
enabled
it
counts
up to three
pulses
it
finally
the
waits
issues the
internal
state
RESET
For
always
external
interrupt,
of
the
(IU)
After
for
HIGH
the
this
is reached, the IU checks the INTJbar line. In the interrupt is issued. In the no that it is stable HIGH, case IDF is checked to see if the the then LOW it is that case interrupt is the external enabled. Eventually, is interrupt IDF and the is zero. request a issued if there is
state
-31-
The the
which
assertion
error
of
quite
easy
since
signal can
is
given
directly by
in figure
the
instruction decoder
be
designed
as
4.3.
error
Figure
Example
address
of
an
instruction decoder
the interrupt
write_mem unit word of
Finally
needs
for the
the
three
signals.
The
two
and
signals
from
control
unit
the
third
is
the
LSbit
a
the
Memory
cycle
Address
Register
(MAR)
Every
time
that
is to be performed and the word signal (i.e. a word is going to be written) the LSbit of the MAR is if it is one or zero. If it is zero there is see examined to no danger since it points to an even address and all the words
write
should
memory is HIGH
be
stored
at
even
addresses
only.
In the
case,
though,
that
the
LSbit
is one,
then
an
address
misalignment
interrupt
is
issued.
The
The
control
points
data
path
switches
as
they
are
depicted
of
in
figure
not such
4.1,
the
are
responsible
for the
proper
traffic But
the
of
data among
components switches
that
assemble
the CPU.
more
some
them are
only
as
but
they
represent
complex
structures
control
decoders,
example,
multiplexers
or
comparators.
The
node,
for
in
c8
figure
4.1
that
more
has
as
inputs
control
the
control
signals shown
c7
and
is
much
complex
structure
than
it
to
be.
-
The
operation
-
of
those
signals signal
is is
of
described
our
in table 4.1
and
as
with
every
other
control
system
the
actual control
design
nodes
can with
look
more
which
like
than
figure
one
4.4.
Generally,
signal
the
control
as
inputs,
of
perform
function
is
more
complex
than
that
switch.
Every
of
control
node
(point)
Table
signals
controls
either
all
the transfer
the
control
data
or
an
operation.
4.1
and
or
shows
points, encode,
affect.
their
and
control
the the
same
function
other
units
that
finally
in
of
the
registers
that
make
they they
the
Later,
chapter
5,
this
table
will will
sensitivity
list
for
the
VHDL
processes
that
implement
the
operation
those
registers.
-32-
-iLOAD
C1B
FKIt:
Figure
control
signals
Re
Data Bus
cl9 c36
PC SP
c25
c26 c21
vector
MAR
MAR Proqram
<<-
Re
int
c23
Counter
<<-
PC PC
Stack
PC+2
c22 c24
Re
Pointer
<<<-
SP SP SP
Ri Ri
Rimm
SP+2
SP-2
Re
-
(0,1) (1,0)
(immediate
Reqister
front
end)
cl8
<-
MDR
(immediate
<<-
Reqister
Rimm
Rimm Rimm
Ri
Ri<5:0>,u Ri<5:0>,s Ri<7:0>,u
<<-
Rimm
Rimm
Rimm
=
=
<<<-
Ri<7:0>,s
Ri<15:8>,u Ri<15:8>,s
Rimm
(cl2 (Cl2
Table
Tranf ers
and
Operations
-33-
Rd,Rsl,Rs2
Rd
Rsl Rs2
<<<-
MDR<10:8>
MDR<5:3>
c20 c2
MDR<2
0>
c20
External
" "
Signals
<<<<<<<-
WR_bar
c30
c31 c32
HIGH HIGH
MDR MAR
c33
c34
c37
c35
File
<<<-
Rf (Rd)
Rf(Rd)<15:8> Rf(Rd)<7:0>
Re
Rimm<7 Rimm
zeros :
0>
Rimm<7:0>
Rf (Rd) R( (Rd)
Ra,Rb,Rc
Ra
Ra
<<-
(ALU
registers
destination)
C7
<<<-
Rb Re
Re
c8 e9
<<<-
bus bus
c40
c41 c2
;
;
switched
i :rom ALU
from
!SHIFTER
Re Re Arithmetic
ALU_bus ALU_bus
PC
SP
Unit1
<-
c42
Logic
<<-
Ra'
Rb
Ra-
Rimm3'4
ALU_bus
PSW
PSW
ALU_bus<7: 0> ALU_bus<15: 8>
<<<<-
PSW:
Rimm"
Ra<15:
Ra<7
8>2
<-
0>2
ALU_bus
ALU_bus
<<<-
Ra
+
-
(Rb (Rb
v v
Rimm)
v v
3'4
CF CF
Ra Ra
Ra Ra
Rimm)3"1
ALU_bus
ALU_bus
AND
Rimm)-'4
OR
XOR
+
Rimm)3'"
Rimm)3'"
ALU_bus
ALU
bus
POWER
<-
Ra
(Rb
Rimm)
3'4
(el, c2, c3, c4) (el, c2, c3, c4) (cl, c2, c3, c4) (cl, c2, c3, c4) (cl, c2, c3, c4) (cl, c2,c3, c4) (cl, c2, c3, c4 ) (cl, c2, c3, c4 ) (cl, c2, c3, c4 ) (cl, c2, c3, c4) (cl, c2, c3, c4) (cl, c2, c3, c4) (cl, c2, c3, c4)
.
(0,0, 0, (0,0, 1, (0,0, 1, (0,1, (0,1, 0, (0,1, 1, (0,1, 1, (1,0, 0, (1,0, (1,0, (1,0, (1,1, (1,1,.1,
0,
.0,
,1, .1,
0,
1) 0) 1) 0) 1) 0) 1) 0) 1) 0) 1) 0)
.1)
SHIFTER5
PS
bus
<<<-
* * *
PS~bus PS~bus
Table
Transfers
and
operations
(continued)
^10,
ell
must
=
have
been
set
before
chosen
any ALU
operation
2(cl0,cll)
(0,0)
(0,1)
None Rb
3(cl0,cll)
4(cl0,cll)
5The
This
chosen chosen
(1,0)
of
Rimm
are
contents number
Ra
shifted
as
must
be
greater
than
contained
in Rimm.
-34-
4.4.1
This
above
The
immediate
the four
registers
is
one
of
sub-paragraphs
that
follow
on
the
the
list
of
with
the
control
signals
and
as
their
result
CPU
some
transfers
the
and
operations,
parts.
having
purpose :
to
clarify
written
The
assignment
Rimm
<-
Ri<5:0>,u
with
means
that
Ri
Rimm
is
loaded
rest
the
six
(6)
LSbits
zeros
of
the
Ri
.
register
filling
the
of
with
(unsigned)
If
the
register
contains
Ri then
Rimm
->
10010110101110101
will
the
with
above
assignment
number :
have
as
result
the
loading
of
the
Rimm
->
00000000000110101
assignment
:
In
contrary,
the
Rimm
<-
Ri<5:0>,s
of
first
and
checks
the MSbit
the
the
6-bit
to
with
number
(bit 5
of
the word)
then
rest
transfers
of
.
this
of
number
the
Rimm
or
register,
filling
the that
bits
what
Rimm
zeros
bit
Look
'=>'
happens
for
example
cases
(the
symbol
represents
the
=
above
Ri
10010110101110101
=>
Rimm
1111111111110101
I
bit
Ri
is
1
=>
10010110101010101
Rimm
0000000000010101
I
bit
The
is
0
assignments used. of
same
action
Rimm,
except
that
data to
4.4.2
In
register
The
register
file
the
and registers
of
the the
of
assignments
concerning
the
file,
for
case
both that
loading
may
of of
them
transferring
is
we
their
repre
contents,
sentation
cause
confusion register
the
In
the
registers
the
file.
loading
the
any
of
the
:
registers
the
register
file
have
assignment
Rf(Rd)
<-
register
-35-
where one
"register"
can
be
a
one
of
is
not
of
actually
the
means
register
the Re, Rimm or zeros. The last but a state which is loaded
the
into
CPU.
all
registers
during
R (Rd)
that
Rd
the
register
register
"001"
file
Rd.
(Rf)
If
that
for
of
of
the the
by
the
example
contains
will
binary
number place:
then the
Rl
following
<-
assignment
actually take
register
In the
case
the
register
change,
then
rest
of
the
register
unchanged.
4.4.3
The
Arithmetic
and
(ALU)
but
not
only
passes
performs
the
arithmetic
logical
operations
it
or
also
transfers
the
a
data bus
(PSW)
contents
its
input
and
registers
to
the
ALU_bus
which an
is
ALU the
16-bit
that ALU
maintains
After Re
operation
is
complete
the the
data
are of
stable
on
ALU_bus,
and so
the the
triggers
LOAD
input
the
,
register
ALU_bus
stored.
with
data to Re
signal
where
they
it
has
are
temporarily
Re
register
control
that
loads
and
unit
the
by
and
the
ALU_bus the
is
(indirectly)
c41 is
to
the
controlled controlled
perform
by by
by
control
.
(like the
the
cycle
and
Power
Shifter)
The
ALU
ability
of
operation
any of is triggered by the LOW-to-HIGH transition clock. It is performed if any of the control internal
to
its
operations
within
one
clock
every
signals
cx
c4
The
is
of
other
than
zero.
sources
for
the
ALU
Rb
operation
are
the
registers
Ra
and
one as
the
registers
or
Rimm.
The
control and
point
which
has
inputs
As
we point
the
can
control
signals
c10
two ALU.
cxl
manages
enter
the
latter.
control
see
in
figure
Rb
and
4.1
one
data
It
paths
the
one
(one
from
and
from
Rimm)
is
and
but
only
one
data
the
path
leaves
Rimm
it
enters
the
important
any
to
of
remember
that to
before
any
ALU
operation
that
needs
Rb
or
registers
(see
Table
4.1),
in
c10
cn
must
have
the
been
set
the
proper
combination
order
to
provide
proper
data
to
the
ALU.
4.4.4
The
Power
Shifter
This
shifter
obtained
the
adjective one
"power"
because (left
of
it
or
our
has
CPU
the
right)
from
cycle.
to
eight
shifts
This
important feature
are needed
speeds
up
its
or
operation, division
since
shifts
for
any
multiplication
operation.
In
our
-36-
Shifter
register
number
(PS)
as
must
shifts
left
as
or
right
the
contents
of
the
Ra
contained
and
in Rimm.
than
nine
This
less
(9)
and
it is loaded
immediate
operand with
the instruction.
these
Therefore, the checking for the number of shifts (to be within limits) must be done during the translation of the code
into
machine
language.
case
The
assembler
number of
should
always
provide
or
an
error
in the
eight.
that the
of
shifts
is
zero
greater
than
The
result
operation
the
one
PS
looks
outputs
like
the
the
which
first
stable
result
to
the
Re
once
and
the
data
get
it
of
triggers the
the to
control
signal
c41
stores
the
contents
bus
the
register.
4.5
Instruction Decomposition
This
was
one
of
the
most
difficult
the the
It
parts
of
the
thesis
project.
During
instructions
CPU changed
give
into micro-operations,
times
and more and
data
path
inside the
added
several
control
nodes also
were
to
a
better
faster
performance.
is
true
that
at
VLSI
point
implementation
.
wasn't
taken
into
consideration
this
Each
instruction,
the
cycle
after
it
for
is
fetched
must
from
the
memory
The
and
following
execution
steps
given
in
3.1,
all
be
executed.
is
not
uniform
the
instructions
it
may
be
from
clock
two
(2)
to
seven
about
cycles
inside
clock
they
may
not
necessarily
the to to the
the
are
clock
cycles
generated
by
(2)
than
which
common
and
uninterruptable
various
components
clock
of
the
system.
So,
more
these two
seven
(7)
internal
clock
cycles
may
sometimes or
be
less
the
external
cycles
a
by
three
access
cycles,
when
the
instruction has to do
memory
and
the
internal
clock
freezes.
pages,
.
In the
next
into
are
micro-instructions
ascending
clock
executed.
order, If
and
according to the clock cycle in which two or more instructions belong to the
are
separated
they
same
cycle
(A)
are
that
means
that
they they
the
can
by
the
conjunction
operator
can
be
executed
concurrently.
If
they
that
separated
by
disjunction
operator
(V)
it
and
means
only
on
one some
of
them
be
executed
at
that
cycle
it depends
other
data,
such
as
mode
the
et
flags,
cetera,
.
the
about
branching
which
conditions,
will
the
are
addressing
one
be
(these
conditions
are
also
instructions
operator
not
separated
it
means
that
by they belong
of
If
the
or
micro
(A )
the
or
(V
to
the
same
group
(i.e.
signals
the
.
same
control
node
they
or
to
the
PS)
-37-
On
control affect
the
a
right
side
of
the
micro-instructions
appear
the
signals
that
of
they
affect.
which of
In
the
cases
that
they
0
group
signals signals
is
assigned
to
particular
node, to 1)
then
are
only the
also
that
are
group that
assumed
change
(from
mentioned.
The
rest
zero.
The
control
.
signals
are
separated
by
the
(A )
or
the
"-"
(V
operators
Besides
these to
operators
there
is the
minus
operator
that
side right refer
is
used
show
that
set
the
control
signal
on
its
on
left
should side.
have been
To
before the
function
all
control of
signals
control
its
interpret
4
.
the
the
signals
to
table
that
describes
operation.
the
control
signals
and
the the
or
result
of
their
The
are
control
signals
inside
parenthesis
imply
that
they
triggered
by
either
the ALU
the
PS
through
the
Control
Unit.
INSTRUCTION
DECOMPOSITION
ADC 1.
Add
with
<-
Carry
Ri<5:0>,u
(Rimm
Ra
<-
<-
Rf (Rd) )
(IMM=1)
(IMM=0) (IMM=1) (IMM=0)
V
2.
(Ra
<-
Rf(Rsl)
<-
A
+ +
Ra
Rf(Rs2))
+
(ALU_bus
Ra Ra
Rimm Rb
+
CF)
V
3
.
(ALU_bus
<-
CF)
Rf (Rd)
-
<-
Re
SBB
Subtract
(Rimm
<-
with
Borrow
1.
Ri<5:0>,u
Ra
<-
<-
Rf (Rd) )
(IMM=1) (IMM=0)
c7 Cl
-li
A A
V
2.
(Ra
<-
Rf(Rsl)
<-
A
-
Ra
Rf(Rs2))
(ALU_bus
Ra Ra
Rimm
CF)
(IMM=1) (IMM=0)
c4 c
(C40)
V
3.
(ALUJDUS
<-
Rb
CF)
<=i
c
(c40)
Rf(Rd)
<-
Re
if
AND
Logical
AND
Ri<5:0>,s
1.
(Rimm
<-
Ra
<-
R (Rd) ) Rf (Rd) )
-14
(IMM=1, SIGN=1)
V V
2
(Rimm
<-
Ri<5:0>,u
Ra
<-
(IMM=1,SIGN=0)
(Ra
<-
Rf(Rsl)
<-
Ra
<-
Rf(Rs2))
=0)
c7
A
Ci Ci Ci7
C9 c3 c3
(ALU_bus
Ra AND
Ra AND
Rimm)
(IMM=1) (IMM=0)
c10 Cn
(C40) (C40)
V
3
(ALUjbus
<-
Rb)
R(Rd)
<-
Re
-38-
OR
Logical OR
(Rimm
<-
1.
Ri<5:0>,s
A A
Ra
<-
Rf (Rd) )
Rf(Rd))
ci3
c14
c8
(IMM=3.,SIGN=1)
V V
2.
(Rimm
<-
Ri<5:0>,u
Ra
<-
Cl3
A A
c8
(IMM=1,SIGN= =0)
(Ra
<-
Rf(Rsl)
<-
Ra
<-
Rf(Rs2))
(IMM=0)
C10 Cn
~~
c7 c3 c3
c9 c4 c4
(ALU_bus
Ra
Ra
OR
Rimm)
(IMM=1) (IMM=0)
Ci Ci
(c4 (c4
o)
V
3.
(ALU_bus
<-
OR Rb)
o)
Rf(Rd)
-
<-
Re
Cl7
XOR
Logical XOR
(Rimm
<-
1.
Ri<5:0>,s
A A
Ra
<-
Rf (Rd) )
(IMM=1
C13
C14
A
ce
C8
,SIGN=1)
V
V
2.
(Rimm
<-
Ri<5:0>,u
Ra
<-
Rf (Rd) )
(IMM=0)
Cic Cn
ci3
\
=0)
(IMM=1,SIGN=
(Ra
<-
Rf(Rsl)
<-
Ra
<-
c7
~
A
Ci cx
c9 c2 c2
(ALU_bus
Ra Ra
XOR XOR
Rimm)
Rb)
(c40)
V
3
.
(ALU_bus
<-
(c4(
R (Rd)
-
<-
Re
|c17
NOP
No
Null
Operation
1.
HLT 1
.
Halt
proc_state
<-
idle
Status
Word
STPSW 1
.
Store Processor
<-
ALU_bus
PSW
c;
c4 c17
(c40)
Rf (Rd)
-
<-
Re
LDPSW
Load Processor
<-
Status
Word
Ra
PSW
Rf (Rd)
Ra
|c7]
fil
High
<-
LDHI
Load
<-
immediate
Ri<7:0>,u
<-
1. 2.
Rimm
c12
Cl6
Rf(Rd)<15:8>
Rimm<7:0>
LDLO
Load immediate
<-
Low
1.
Rimm
Ri<7:0>,u
<-
c12
0>
Rf (Rd)
<7 : 0>
Rimm<7 :
Cl6
Cl7
-39-
JMP
Jump
Ra
<-
(conditional
or
not) c8
Rf (Rd)
<-
ALU_bus
MAR
<-
Ra
c
<-
(C40)
c21
3.
Re
PC
Re
c24
(if
STW 1.
-
condition
is
true)
Store Word
Ra
<-
R(Rsl)
<-
A
+
Ra
<-
Rf(Rs2)
ALUJbus
MAR
<-
Ra
Rb
<-
[cTT
Rf (Rd)
(c40)
3
4
Re
<-
Ra Ra
ALUJbus
MDR
<-
Re
<-
6.
LDW
-
write_mem
'1'
(write
to
memory)
Load Word
Ra
<-
1. 2
.
Rf(Rsl)
<-
A
+
Ra Rb
<-
Rf(Rs2) (c40)
ALUJbus
MAR
<-
Ra
Re
<'1'
4.
read__mem
Ri
<-
MDR
<-
6
7
Rimm
Ri
Rimm
-14
Rf (Rd)
-
<-
STB
Store
Ra
<-
Byte
1.
Rf(Rsl)
<-
A
+
Ra Rb
<-
<-
Rf(Rs2)
-ii
ALUJbus MAR
<-
Ra
Re
<-
Ra
Ra
<-
Rf (Rd) (MSB,
MAR MAR
ALUJdus
(0) (0)
=0) =1)
C4 c2 c2 C4
(C40)
c3 c3
V V V
5
ALU_bus<7:0>
ALU_bus<15:8>
Ra<15:8>
(MSB,
(c<
C4
<-
Ra<7
0>
(LSB,MAR(0)
=0)
<c40)
ALUJdus MDR
<-
<-
Ra
(LSB,MAR(0)=1)
(c4 0)
Re
mem
<'1'
6
LDB
-
write
(write
to
memory)
Load Byte
Ra
<-
1.
Rf(Rsl)
<-
A
+
Ra Rb
<-
Rf(Rs2)
c2
-7
A
(c40)
ALUJdus MAR
<-
Ra
c3
Re
<'1'
C21
4.
read_mem
Ri
<-
MDR
-18
-40-
Rimm Rimm
<-
Ri<15,8>,u Ri<15:8>,s
-13
<-
Rimm
Rimm
<-
Ri<7:0>,u
<-
Ri<7:0>,s
Rimm
c12
Cl5
-14
Rf (Rd)
LDSP 1
.
-
<-
Ra
Rf (Rd)
<-
2 3
ALUJdus
SP
<-
Ra
(c40)
-43
Re
STSP
1
.
Store
<-
Stack Pointer
-42
Re
SP
<-
Rf (Rd)
-
Re
CALL
Call
<-
Subroutine
PC Re
Re
MDR
A A A
Ra
<-
Rf (Rd)
SP
2 3
4
<-
MAR
<'
<-
A
-
ALUJdus
<-
Ra
(c40)
C24
write_mem
'
PC
<-
Re
SP
<-
SP
c27
RET
1
.
Return SP
MAR
<-
from Subroutine
+
SP SP
<-
3.
4
.
read_mem
<-
'1'
Ri
<-
MDR
<-
Rimm
Ri
<-
6
7
ALUJdus PC
<-
Rimm
(c40)
Re
SHLL 1.
Shift
<-
Left
Logical
Rimm
Ri<5:0>,u
<-
Ra
<-
R (Rd)
Cl3
A
c6 Cl7
Ce
2. 3.
PSJdus
Rimm Re
(SHLL(Ra)
<c4
Rf(Rd)
<-
SHRL
Shift
<-
Right
Logical
1.
Rimm
Ri<5:0>,u
<-
Ra
<-
Rf (Rd)
C13
ce
2. 3.
PSJbus
Rimm
(SHRL(Ra)
(c4i)
Rf(Rd)
<-
Re
-41-
SHRA
1.
Rimm
Ri<5:0>,u
<-
Ra
<-
Rf (Rd)
Cl3 Cs
A
c6
ce
2.
3.
PSJdus
Rimm
(SHLL(Ra)
--4l)
Rf(Rd)
-
<-
Re
c 17
PUSH
Push
<-
into Stack
1.
Ra
Rf(Rd)
<-
( va r_t o_pu s h
(var_to_push
R0-R7)
PSW)
V
2.
NULL
ALUJdus
Ra PSW
( va r_t o_pu s h
(var_to_push
<-
R0-R7)
PSW)
c4
(C4
c4
l)
V
3.
4.
ALUJdus
MDR SP
<-
<-
c3
c19
c 27
(c 4l)
c 26
Re SP
-
A
2
MAR
SP
<-
POP 1
.
Pop
SP MAR
<-
from Stack
SP SP
<'1'
c 28 c 26
<-
3.
4 5
.
read_mem
Ri
<-
MDR
<-
c 18
c 14
Rimm PSW
Ri
<-
Rimm
<-
(var_to_jDop
PSW)
c10
c2
C4
V
Let's
Rf (Rd)
also
cycle
Rimm
c15
micro-operations same
give
which
the
that the
we
need
for
:
the
fetch
FETCH
is the
for
all
instructions
CYCLE
<-
1 2
MAR
PC
<'
1'
readmem
PC Rsl
<<-
PC
2
'1'
Ri
<-
MDR
<-
Ri
<-
MDR<10:8>
MDR<5:3>
<-
Rs2
MDR<2:0>
decode
c22
the
cie
C20
If
not
one
wonders
about
with
loading
contents
of
the MDR
register
(which is have
to
mentioned)
the
of
the
data
bus,
.
we
inside the memory cycle initiated by '1' Both time it becomes the signal read_mem the every for the signals initiate processes write_mem and read mem and inside those processes, the memory read and write cycles
mention
(according
registers
to
the
so
the
a
read/write
of
or
transferring
and
the
data
and
address
to
the
buses
occur
that
successful
communication
is
established
between
the
CPU
the
memory
-42-
VHDL
The
Description
paragraph
of
of
the Architecture
chapter
first
to
this
is
and
brief
intro
duction
hardware
Speed
description
Integrated
-
languages
Circuits
We
are
especially the
Hardware
Very
High
(VHSIC)
Description
going to use VHDL in the remainder of this chapter to describe and simulate (in the next the architecture we described in the three chapter)
or
Language
VHDL.
previous
chapters
Hardware
After
Description design
of
Languages
the
and
the
phase
of
the
evaluation.
time consuming process, the use Hardware Description Languages between the design the
a use
of
computers
are of a
was
incorporated.
link
system.
(HDLs)
the connecting
computer
and
the
evaluation
By
as
-to
these
or a
languages, every
source
design the
can
be transferred
of
schematic
file
or
combination
both
computers,
and
simulation
where
the
evaluation
procedure
can
accurately.
This
evaluation
is
nothing
almost
of
the
to
design.
ensure
Therefore,
the
incorporated
been the
compiled
simulator
where error
input to the
results
simulator
and
the
final
that
check
are
obtained.
If
are
not
the
ones
were
designers
should
go
back,
the
the follow
then
the
after
corrections,
procedure.
they
should
again
verification
By
the
and
was
validating task of
may
be
simulation, prototyping the design is avoided case of a design that saved in the
design
through
the
The
main
applications,
and
thus,
of
of
the
HDLs
are
two that
some
the
comes
documentation
the
an
modeling
design.
After Until
a
the
simulation
by
HDL
supported
simulator.
years
specific of
them
HDLs
were of
developed
and
around
structures.
Some
the the
architecture
therefore
they
were
Architecture
Description
register
Languages
or
(ADLs)
and
others
could
only
was
describe
one
gate
level
and
even
finally
more
.
there
that
could
do
all
of
the
above
5.1.1
VHDL
first developed
part
of was
by
the US Department
of
Defense,
Circuits
after
as
its Very
and
High
as
Speed
an
Integrated
standard
Later
of
it
proposed
IEEE
and
number
revisions
changes,
it became
standard
in
late
1987 level
(IEEE
of
1076)
a
VHDL
has
the
unique
digital
and
system,
architecture
the
silicon
lowest
level
which
is
a
abstraction
levels
of
-43-
digital
the
system
are
shown
in figure
of
5.1
[ARM89]
The
shape
of
pyramid
shows
the
amount
detail that
each
level
which as
we
represents,
gradually
approach
increases
the
silicon
PMS
CHIP
\
\ \
\
/
/
/ /
description
with
three the
the Switch
higher
pyramid
REGISTER
GATE CIRCUIT
SILICON
levels
which
Processor
Memory
(PMS)
,
level level
.
the
an
Chip
and
\ \
the
PMS
at
Register
level
The
is
abstract
look
the
/
Figure
the
and
CPU-memory
through the
performance
connection
buses
specifications.
The
chip
Description Levels
of
level
the
contains
the
various
Digital
Memories
Systems
parts of
the
system such as
microprocessor,
components.
the
Random
Access
(RAMs)
and
other
Finally
MUXes
which
goes
inside these
parts.
can
components
describes
other
the the
:
operations
or
ALUs,
combinational
sequential
Two
are
descriptions
The
we and can
VHDL
provide
for
digital
system
structural
the
behavioral.
By
the
structural
description
of
components
the
system
its
levels.
These
a
levels
of the complete list interconnection at any of co-exist in the same description mean
their
file,
is
giving
hierarchical
we
of
behavioral
description,
at
model can
mean
algorithm
By (procedure) that
system.
the
performed
of
system.
Since the
behavioral
circuit
at
chip,
we
level for
in
design,
at
of
modeling
Now
without
different
present
parts
different the
levels.
let's
some
basic
features
the
and
of
VHDL
getting
not
into
with
details. the
We
suppose
that
reader
is
already familiar
This
some
language,
its
structure
its
use.
is
of
tutorial but a brief explanation of going to be a the most important parts of the language that have
been
used
for
the
description
of
our
system.
Entity
Every
can
design
is
expressed
in terms
our
of
entities.
Entities
represents
be
nested
and
the
of
top-level
entity
the
uppermost
level
design.
of
Architecture
The
architecture
the
entity-
single
tectures
but
only
one
archi
enabled
for
simulation
run.
Package
A
used
package
is
file
with
collection
of
commonly
data
types
and
subprograms
in
design.
-44-
More than
one
package
can
be
linked to
or
design.
If
they
then
same
data types
linked
of
subprograms,
of
the
last
package
is
used.
Process VHDL.
It
of
is the basic
the
and
unit
sequential
PROCESS1
execution are
in
All
commands
inside
executed
sequentially
after
zero.
their
execution
is
of
scheduled
At
time
their
activation.
of
Any
number
At
Because
extra
this
strange
behavior,
.
proper need
simulation,
implementations
(see
that
PROCESSes
attention
5.8)
Block
of
Blocks,
parallel
execution
like PROCESSes, represent the basic unit in VHDL. That means that all of the
a
statements all
inside is
BLOCK are
activated
after
executed
concurrently
time
and
(i.e.
their
the
events
are
at
the
.
same
execution
scheduled
At)
5.2
Getting
We
started
stared
the
description
of
phase
of
the
design
of on
with
big
problem
for
project
this
size.
The
we
version
the
Mentor
Graphics
Corporation VHDL
was a
compiler
had to
use
the Apollo It
was made
allow
Workstations
available
preliuminary
academic
or
Alpha-version.
corporate
to
certain
and
users
to
them
to
obtain
some
preliminary
compiler
experience
with
the
language
before
not
were
the
complete
was
finished.
of
The
compiler
did
recognize
some
the lack
GENERICS,
and of
very the
useful
parts
the
language.
the
attributes. some
These
With
Resolution
Fuctions,
QUIET
COMPONENT
declarations
the
STABLE
(x)
and
(x)
the
GENERICS
we
couldn't
entities.
pass
timing
of
characteristics
into
our
design
was
With the
lack
a
the
Resolution
Fuctions
there
no
way
to
to
implement
signals
data bus
that
are of
that
can
be driven
more
by
both the
are
CPU
and
the memory
at
a
(generally,
The
Resolution
Functions
used
define
to
of
driven the
by
that
one
active
signal
time)
lack
one
COMPONENTS
of
didn't
permit
us
give
structural
description
the
system.
With the
use
COMPONENTS,
can and
describe
each
component
separately,
can
using
entities
architectures,
components
and
then
map
these
architectures
into
.
of
higher
level the
design
(uppermost
entity)
In
clearly described for this way, the inputs and them are fully between interconnections each component and the for [ARM8 9] (see declarations component in the
outputs
are
demonstrated
more
information)
Finally,
gave
us
the
some
lack
of
of
the
STABLE
(x)
and
QUIET
a
(x)
attributes
difficulty
time but
in determining if
'x'. Some
other,
exp-
signal
was
stable
for
also
period
minor
problems
were
present,
like the
ones at
mentioned
above,
we
found
some
ways
to
overcome
them,
even
the
xFrom
now
capital
the
VHDL
keywords
will
be
written
in
-45-
ense
of
the
integrity
of
our
design
as
we
will
explain
later
5.2.1
We
Packages
briefly
we
-
mentioned one
packages
in
5.1.1.
In
all
this the
thesis
project,
constants
our
used
package
that
contained
timing
-
instead
and
of
description
of
using GENERICS we used constants the functions that were mainly used
of one
of
for
The
conversion
variables
data
type
to
another.
source
file
of
of
the
package
must we
always
be
in
the
parent
we want
directory
one
the
directory
to.
The
that
have the
file that
to link the
package
directory
structure
in
figure
5.2.
/no i
pock
hdl
/no i
des i
n/cpu
/no 1
n/rout
ines
gn
hd 1
Figure
'/main'
Directory
(or
the
Organization
'login'
In the
In
the
directory
of
directory)
with
we
have
our
source
file
the
('
package
"pack.
hdl"
the
functions.
of we compile
/main/cpu'
subdirectory
)
:
we
main
design
package
which
has
the
the
name
"design
After
the
with
command
$ hdl
from the
root
main
pack.
hdl
'/main/routines'
('/')
a
directory,
the
of
directory
'
/main'
.
is
created
as
subdirectory
This
directory
files
we
contains
some
other
directories
compilation.
with
the
binary
to
that
were
created
by
to
the
In
binary
include
files the
our :
source
file
link these
have
to
line
USE
work. routines.
ALL;
use of
of
that
file
that
used
and
before the
given
any data
A. It
or
function
was
The
package
that
we
is
package.
-46-
contains
the
data
function,
constants
.
the
resolution
and
some
Component
We
description
to
represent
was no of
each
decided
since
component
by
be
BLOCK The
structure
there
chance
to
use
COMPONENTS.
can
BLOCK
structure
is
part
the
code,
that
executed
concurrently with other BLOCK structures of the same level and it can contain smaller structures such as BLOCKS or PROCESSes
which can
also
be
executed
concurrently.
the
various
components
to
BLOCKS
or
assigned
shown
in
figure
5.3.
:
ARCHITECTURE
BLOCK BLOCK BLOCK
:
SYSTEM
BLOCK UNIT BLOCK
DATA BUS S RESOLUTION FUNCTION
:
:
CPU
:
CLOCK
GENERATOR
CONTROL
INTERRUPT
:
PROCESSES*
REGISTERS
BLOCK SHIFTER
:
BANK UNIT
PROCESS PROCESS
ALU POWER
PROCESS
:
MEHORT
IN1TIRLIZRTI0N
PROCESS
BLOCK : CPU-MEMORY HANDSHAKING UNIT
MEMORY
MEMORY
BANK
BANK
PROCESS
Figure
+
5.3
the
cpu
BLOCKS
BLOCK The
and
PROCESSes that
The
symbol
in
of
means
there
are
as
many
units
PROCESSes
consist and
as
registers.
control
and
interrupt
also
some
other
PROCESSes
as
shown unit
in
figures
5.4
5.5.
:
The
execute
BLOCK in the
control
BLOCK,
contains
BLOCK
CONTROL
:
UNIT
BLOCK
PROCESS FETCH
INTERRUPT UNIT
:
PROCESS
i
RESET
INTERRUPT
PROCESS
BLOCK
DECODE
zn
C00RDINRTION)
ACTION
PROCESS
PROCESS
EXTERNAL
INTERRUPT INTERRUPT
EXECUTE
:
OPCODE ERROR
PROCESS
STATE
PROCESS
PROCESS
INTERRUPT
Figure
Control Unit
BLOCK
Figure
5 5
.
Interrupt
BLOCK
Unit
-47-
all
the
PROCESSes for the execution of each instruction and interrupts PROCESSes. four are There (4) actually interrupt service PROCESSes which are called in the case of an CAUTION : These interrupt to produce some preliminary actions interrupt PROCESSes are not the interrupt service routines
the
which
reside
in the
memory.
They
and
are
also unit
different
BLOCK
or
from
the
four
(4)
PROCESSes
unit
in
the
interrupt
for
because
taken
the the
interrupt
recognizes
allows
prohibits
it is not responsible any interrupt is issued. The next paragraphs explain with details some of the boxes in figures 5.3, 5.4 and 5.5.
interrupts;
an
action
after more
The
In
data bus
contrast
to
the
address
bus
the
which
and
can
driven be
only
by
of
the
a
CPU,
driven
the
by
both the
CPU
memory.
in 5.2,
use
Resolution Function
wasn't
available as
and
consequently we had to define two different driven by the CPU and another one data bus, memory. These two signals couldn't be defined
-
signals
the
driven
as
by
of
the this
buses
we'
another
disadvantage
-
VHDL
version
so
of
defined
of
Gl
them
where
as
arrays
16
was
elements
each
element
type
G3
G2 VCC
Figure
gsim_state.
This
type
supports signal
four
states
(4)
:
different
LOW
('0'),
and
HIGH
and
('1'),
HIGH
IMPEDANCE
('z')
be
UNKNOWN
('x')
therefore the
quite
reali
simulation
can
6 Wired OR logic
in
our
system. with
stic.
used
This for
data the
type
was
also
all
signals
that data
were
used
Before
we
continue
further
need
explanations
on
the
bus
that
let's
first
see
why
that
we we
a a
bus
and or
resolution
function.
Suppose
for
example,
have
Gl
single
wire
which
(figure
can
when
5.6)
as
is
driven
one of
by
the
the
two
gates
G2,
LOW
have
output
states
HIGH
('1')
('0')
G1\G2
0
0
X
1
X
0
1
X
0
1
X
1
X
0
1
Table
Resolution
Table
for the
input
of
G3
enabled
or
HIGH
IMPEDANCE
('z')
when
disabled.
This
wire
is
-48-
the
according to the resolution table 5.1 it '1' states 'x', The input of or '0', G3 enters state if any of the driving gates have the unknown input (so the output is unknown too) , or when one of them drives the wire at logic HIGH and the other at logic LOW. The above table is easily implemented by the function below which resides in the package with the various functions:
of
input
G3
and
can
be in
one
of
the
'z'
'x'
FUNCTION
wired_or
(k,l
: : :
qsim
state)
RETURN
qsim_state
IS
2 3
4
ret a,b
qsim
qsim extra
state; state;
state vect
dumvec
to
to
extra
extra
extra
DOWNTO
0)
5 6
7
qsim
qsim
(k)
b
: :
(1);
1 D: 1 1:
=>
=> => => =>
qsim
qsim
:= := :=
:=
'0'
"01"
'X'
1 2:
1 3:
"0Z"
qsim
'0'
'X' '1' '1'
'0'
"10"
ret_qsim
1 i
WHEN WHEN
WHEN WHEN
WHEN WHEN
"11"
ret ret
ret ret ret
qsim
:=
1 5:
1 6:
"1Z"
:=
"ZO"
:=
1 7:
1 3: 1 9:
"Zl"
"ZZ"
:=
OTHERS
ret
:=
2 0: 2 1: 2 2:
END
CASE;
ret
RETURN
qsim; or;
END
wired
Figure the
In to
and
7
1
Resolution
Function
In
line
1,
and
parameters
are
two
the
inputs
from
need
of
the type
this
function.
qsim state
lines
and
they
(see
are
converted
data
of
extra_state
5.8
two
conversion)
after
they
5.1.
form
The
element
array in line 8,
and
they
the
CASE
are
resolved
by
the CASE
statement
follows because
fully
means
implements
"xx"
the
table
which
"WHEN
OTHERS"
statement
case
couldn't
be
of n
mentioned
in
every
we can always
statement
3n_1
in
which
row
signals
is examined,
which
to
different
OTHERS"
cases
plus
more
.last
one
has
"WHEN
OTHERS".
If
than
3n_1
cases an
are
examined
the
"WHEN
statement
is missing,
error
during
the
compilation
will
be
issued.
CPU_DATfl_0UT
CPU
vMEM_DflTA_0UT
MEMORY
<
Figure
J
DflTR BUS
Data
bus
decomposition
-49-
After
this
we
rather
discussion
other
which
had
about
let's
of
go
back
to
the
buses,
represent
respectively.
signals pass
and the mem_data_out cpu_data_out namely the the data coming out of the CPU and the memory The real data bus is formed after these two a resolution
through
function
(Fig.
are
5.8)
The
as
data bus then, contains the correct data that inputs to the CPU and the memory.
These the two
signals
available
form
the
PROCESS
which
is described below
resolution
data bus
function BLOCK.
DATA BUS
data_bus_res
BEGIN
BLOCK
res_func
PROCESS (mem_data_out
cpu_data_out
)
DOWNTO
VARIABLE
VARIABLE BEGIN
l,r dumbin
: :
qsim_state;
qsim_state_vector
(15
0)
FOR i
END
IN
mem_data_out'
RANGE
LOOP
(mem_data_out
data bus(i)
_
<= wired_or
(i)
cpu_data_out
(i) )
LOOP;
PROCESS data
res_func;
END
END
BLOCK
bus
res;
Figure
Data
bus
PROCESS
on which the sensitivity list is a list of signals of the If depends. PROCESS of the of the body execution any statements then the list changes, of the signals sensitivity
The
inside
In
the
our
PROCESS
case
start
to
be
executed.
the
PROCESS
statement
FOR-LOOP
statement
which
assigns
to
each
data
bus
data
the
result applied
of
the
resolution
function,
of
when
function
cpu
is
out
to
same
bit
positions
both
and
the
mem_data_out
If
for
example
data-out
cpu~data number
signal signal
is
"OlOlOlzx"
out
is
binary binary
bus
and
"zxlllzzl"
then
shown
the
assigned
to
the
data
be
the
one
in
figure
5.10.
Oxxlxlzx
Figure
5.10
Example
of
the
data bus
formation
-50-
The
secondary
units
units unit
are
and
the the
to
system
clock
CPU-Memory Handshaking
implement
5.12
and
They
code some
are
quite
simple
units
in
VHDL
and
their
is
presented
in figures 5.11,
comments.
5.13,
followed
by
explanatory
CLOCK
clk_gen :
GENERATOR
BLOCK
BEGIN
system_clk :
PROCESS
(run, clock)
AND
BEGIN
IF
((run'
EVENT)
<=
(run
AND
'1'))
=
THEN
starts always
clock
ELSIF ELSE
(clock'
'1'; EVENT)
NOT
from HIGH
(run
'1'))
THEN
clock
<=
(clock)
AFTER period/2;
clock
<=
'0';
if RUN is
LOW
then
clock
remains
LOW
END
END
IF;
PROCESS
system_clk;
END
BLOCK
elk
gen;
Figure
MEMORY
mem
5.11
SELECT
:
System Clock
UNIT
Generator
BANK
bank_sel_unit
BLOCK
BEGIN
mbsu
PROCESS (word, rd_bar, wr_bar, addr_lsb, vma) VARIABLE int_l , int_2 , int_3 : qsim_state;
BEGIN
(NOT(wr_bar) ) AND (word) ; (NOT (wr_bar) ) AND (addr_lsb) AND (NOT (word) ) ; (NOT (addr_lsb) ) AND (NOT (wr_bar) ) AND (NOT (word) ) int_3 '0')) '0') AND (wr_bar ASSERT NOT((rd_bar REPORT "wr bar & rd_bar cannot be both
int 1 int~2
:= := := = =
LOW"
SEVERITY
oe_bar cs_bar wrl
<= <=
ERROR;
rd_bar;
NOT
(vma);
OR OR
bar
<= <=
NOT(int_l
NOT(int_l mbsu;
wr2_bar
int_3) int_2)
;
;
PROCESS
END
BLOCK
mem
bank
sel_unit;
Figure
12
Memory
HANDSHAKING
Bank
UNIT
Select
Unit
CPU MEMORY
cpu
TIME
:
mem_time_unit
BLOCK
BEGIN
handshake
PROCESS
count
integer;
UNTIL
ON
rd
bar,wr_bar
IF
((rd
bar'
EVENT)
<=
'
AND
'0')
AND
OR
(wr_bar
=
'0'
) )
(vma
'
'
) )
Tl T2
THEN
mem
rdy
ON
'
WAIT
clock clock
<=
'1'
; UNTIL
UNTIL
AFTER
(clock
'
'
end end
WAIT
mem
_
ON
(clock
'1');
*
rdy
(w_states
period);
wait
states
END
IF;
-51-
IF
(wrjbar'
EVENT)
<=
'
AND
(wr_bar
'0')
=
AND
(vma
'1'))
Tl T2
THEN
end end states
mem_rdy
WAIT WAIT ON
'
clock
clock
<=
'1'
UNTIL UNTIL
AFTER
ON
(clock (clock
'1'); ' 1 ) ;
'
mem_rdy
END END END BLOCK
(w_states
period);
wait
IF;
PROCESS
handshake;
cpu_mem_time_unit ;
Figure
5.13
CPU-memory handshaking
unit
The memory
The
memory
at
BLOCK
has
three
PROCESSes.
of
The
first
one
is
and
activated
the
to
LOW-to-HIGH transition
the RUN
signal
it
the
transfers
the
two
memory
banks,
service
routines
simulation.
which
This
memory integer arrays that represent interrupt vectors, the interrupt for which is used the and some code PROCESS is described in the next chapter
two the
simulation ones
of
is dedicated to the
two PROCESSes Let's
are
a
the
entire
system.
The
other
thp
which
banks.
take
a
Ice way
.
one
implemented in
similar
l 2
bank2
access
PROCESS
mem_val
3 4
wr2_bar)
qsim_state_vector
(7
DOWNTO
0)
5 6
7
interm_dat
qsim_state_vector
(7
DOWNTO
=
0); '0'))
THEN
EVENT)
:= :=
AND
(oe_bar
8 9
10 12
dum
int
val
qsim_to_int
(cs_bar
mem_bank2
(dum_int
:=
dum~bin(7
DOWNTO
0)
0
int_to_8bit
(mem_val)
AFTER
FOR END
ELSIF
IN
DOWNTO
LOOP
<=
13 14 15
16
17
mem_data_out
(i)
dum_bin(i)
(wr2_bar DOWNTO
=
t_o;
(cs_bar
=
LOOP;
(wr2_bar'
EVENT)
AND
'0')
;
AND
'0'))
THEN
interm_dat
mem val
:=
:=
data_bus (7
0)
qsim_to_int
18
int
ELSIF
:=
qsim_to_int
<=
19 20 21 22
bank2 (mem_val)
(oejbar'
EVENT)
DOWNTO
AND
'1'))
THEN
IN
LOOP
<=
mem_data_out
(i)
AFTER tot d;
23 24
25
LOOP;
26
27
NULL; IF;
bank2
access;
PROCESS
Figure
5.14
Memory
this
Bank
#2
memory bank in the
These
as
As
figure
5.14
OE
shows,
is
has
the
as
#2
and
the
PROCESS
that
list
the
provided
signals
sensitivity
signals
are
and
WR2_bar. Unit
Select
explained
After
signal
has
changed,
it
is
first
checked
in 2.2. if this is a
-52-
memory
read
(lines
7-13)
If
it
is,
the to
binary
number
contained
in the
address
bus
is
converted
integer
(line
8)
in order to find the memory (array) location we want to read In from. line 9, the number contained in that location is stored in a temporary variable and in line 10 it is converted to an 8bit binary number. This number is transferred to the
eight
bus
(8) LSbits of the me/n_data_out bus (remember the data decomposition?) in lines 11 to 13 and after time t0 (see
and
2.3
table
of
2.2)
If
it
is
are buses 0>) integers (lines 16-17) converted to The eight (8) LSbits of the data bus have first to be transferred to a temporary which an then is 8-bits and the variable long, array of contents
the
address
and
then
both
the
conversion
function
call
has
a
to
be
called.
The
reason
for
that
is
a
that
we
cannot
of a
function
by specifying
.
as
parameter
portion
variable
(scalar)
error :
Therefore
the
following
command
issues
compiler
dum_int
:=
qsim_to_int
(datajbus (7
DOWNTO
0) )
After
and
the
conversion
of
the
data
.
bus
(<7:0>))
part
the
of
two
(address
place
bus
(line
18)
In the third
the PROCESS
of
returns
the
eight
LSbits
(lines 19-22) the memory the data bus to the HIGH IMPEDANCE
state
after
its
we
output
is
disabled.
The
with with
PROCESS
one
for
the
the the
described
MSbits
of
eight
memory bank #1 is almost identical with only difference that it works the data and jne.m_data_out buses.
5.7
The
The
CPU
CPU The
that
we are paragraph going to describe in this CPU implemented (as of September
is the
latest
.
version
of
the
first CPU had only the ability to write and read implementation to/from the memory and we used it to verify the as and the the buses, they memory the of secondary units, first After this paragraphs. previous the in described
1,
1991)
version,
a
the
and
various
units
and
registers
were
added
one
at
time
by
the
use
of
small
programs,
verified.
they
were
simulated
and
their
proper
operation
was
5.7.1
The
registers
This
was
the
easiest
part
of
the
CPU
to
describe.
signals
The
as
loading
thev
that
an
signals
of
each
register
depends
on
some
control
were
described
consist
in
of
4.4
and
table
4.1.
of
These
control
can
the
describe
the
behavior
the
PROCESSes
We
will
take
as
example
.
the
description
the
Memory
Address
Register
(MAR)
as
By
destination
table 4.1 all the assignments that have searching in the MAR we find the following :
<~ <-
MAR MAR
PC SP
c:5 c26
-53-
MAR
MAR
<<-
RC
int_vector
C21 c23
We
take,
thus,
these
control
signals
of a
build
the
c21,
with
: PROCESS (c21 , c23, c25, c26) VARIABLE dumbin : qsim_state vector (15 BEGIN
DOWNTO
0)
ASSERT
NOT( ( (c21
((c21
AND
AND
'1'
'1' '1'
'1'
'1'
'1'
)) OR )) OR )) OR )) OR )) OR )))
sources"
"MAR assignment
Multiple
THEN THEN
SEVERITY
MAR
<=
(c21
AND
AND
'1'))
=
ELSIF
ELSIF
((c25'
MAR
(c25 (c23
:=
'1')) '1'))
THEN
dumbin (15
MAR
DOWNTO
0)
ELSTF
ELSE END END
((c26'
MAR
<=
AND
(c26
'1'))
THEN
NULL; IF;
mem_addr_reg;
PROCESS
Figure
We
15
VHDL
description
for MAR
signal at a
first
want
to
we
make
sure
that
ASSERT
:
just
one
time
is
and
asserted,
REPORT
so
have
the
statement
to
check
it,
whenever
it
happens
"MAR
assignment
error
Multiple
sources"
to
the
an
person
who
runs
the
.
time
ERROR
(lines
In the
4-11)
case
the then
same
the that
assignment
takes
place
was
asserted.
to
the
control
signal
assignment
contained pointed
(lines
16-18)
signal
the
of
MAR
an
is
loaded
of
the
number
in
the
the
position
array
four
16-bit
elements a
by
vec
num.
CPU
that
"contains
the
represents
vectors
that
to
interrupt
same
occurs
The
and
rest
of
registers
implemented in the
mention
way
we
don't
think
that
we
should
them.
5.7.2
This
that
are
The
control
unit
unit
is
BLOCK
itself
and
of
contains
arrange
the
normal :
operation
the
CPU.
the
following
-54-
5.7.2.1
The
internal
clock
This is the clock that is distributed to the CPU parts Its operation is suspended during a memory read or write cycle that is when either the write_mem or the read_mem signal is
.
asserted
(they
the
are
code
and it resumes when these signals are deasserted deasserted by the MEMRDY signal) Figure 5.16 shows for the internal clock implementation.
-
internal_clock
BEGIN
IF
PROCESS
=
mem) THEN
( (write_mem
NULL;
'1')
(read_mem
'1'))
ELSE
elk
<=
clock;
END
END
IF;
PROCESS
internal_clock;
Figure
5.16
Internal
Clock
5.7.2.2
The three
and
The
fetch PROCESS
of
steps
the fetch
were
cycle
were
explained
in 3.1 imple
use of
the
micro-operations
mentioned
with
in
4.5.
on
The
mentation
is
.
shown
in figure 5.17
comments
the
the
commands
fetch_instr
BEGIN
PROCESS
=
(proc_state, f_cyc)
THEN
IF
(proc_state
IF
(f_cyc
c25
<=
fetch) 1) THEN
=
1st
MAR MDR Ri
fetch
<-
cycle
'1','0'
ELSIF
(f_cyc (f_cyc
<=
2)
'
PC
MEM
MDR
<'
read_mem
<=
=
<-
[MAR]
ELSIF
3)
cl8 c20
c22
'1','0'
<-
<= <=
'l'.'O'
decode
PC
<-
'
'1','0'
AFTER period/2;
PC
IF;
PROCESS
Figure
5.17
The
fetch PROCESS
5.7.2.3
This
BLOCK
The
execute
BLOCK
contains
twenty
.
five
at
(25)
the
PROCESSes
contains
proper
(i.e.
as
many
As
an
as
the
instructions)
figure
Each
PROCESS
the
micro-
operations
that have to be
executed
clock
cycle.
example,
of
5.18
shows
the
code
for
the
execution
PROCESS
the
OR
instruction.
are
The
control
signals
that
where
each
instruction instruction
uses,
easily
was
obtained given.
from
4.5
the
decomposition
orr_in
BEGIN IF
(proc_state
execute)
AND
(instruction
orr)
THEN
CASE
ex_cyc
IS
-55-
WHEN
=>
IF
(immediate
IF
(sign
cl3
cl4
<= <=
'1'
'1','0' '1','0'
ELSE
cl3
<=
'1','0'
END
c8
IF;
<=
'1','0'
ELSE
c7
<= <=
'1','0' '1','0'
c9
END
WHEN
=>
IF
IF; (immediate
clO
<=
'1')
THEN
'1','0'
ELSE
ell
<=
'1','0'
END
cl
IF;
<= <= <= <=
'1','0'
'1','0' '1','0' '1','0'
c3
c4
WHEN WHEN
=>
cl7
ex_end
<=
'
'
OTHERS
=>
NULL;
END
END
END
CASE;
orr_in;
IF;
PROCESS
Figure
The
5.18
The
OR execution PROCESS
check
"WHEN
number"
statements and
the
clock
cycle proper
an
that
the
is
at,
are
asserted.
to
that
the
of
control
execution
signal
instruction
at
an
the
end,
the
it
CU
asserts
ex_end
and
the
next
cycle,
after
the
finishes
with
interrupt,
instruction
starts an
the
checking fetch
was
for
of
external
the
next
if
no
such
interrupt
issued.
5.7.2.4
This It
The the
the
state
coordination
is
most
right
important
state
PROCESS
of
the
control
unit
maintains
sequence
for the
CPU's
fetch
and
execute
states.
This PROCESS
goes
(Fig.
5.19)
is
enabled
the
internal
clock
If the CPU
advances
.Then
fetch
cycle
(f_cyc)
from
it
to
the
changes
state,
fetch
the
execution
cycle
(ex_cyc)
until
is
the
initiated to
ex_end again
1. the
The
execution
cycle
is
Then
increased
the
state
signal
becomes state,
cycle
HIGH
('1').
execute
PROCESS
changes
from to
to
fetch,
if
no
external
it
the
fetch
state
PROCESS
BEGIN
WAIT
ON
elk
UNTIL
=
(elk
'
'
IF
(proc_state
fetch)
+1;
=
AND
(f_cyc
AND
<
3) )
=
THEN
eye
<=
f_cyc
((proc_state
ex_cyc
<=
fetch)
(f_cyc
3))
THEN
1;
<=
proc_state
execute;
=
ELSIF
(proc_state
execute)
AND
(ex_end
/=
'1'))
THEN
-56-
ex
eye
<=
ex_cyc
=
1;
=
ELSIF
7(proc_state
((intjoar
=
execute) AND (ex_end = '1') AND '1') OR (PSW (4) '1'))) THEN
f_cyc
ex_end
<=
1;
<=
'
proc_state
<=
fetch;
;
'
ELSE END
END
NULL; IF;
state;
PROCESS
Figure
5.19
The
state
coordination
PROCESS
5.7.2.5
In
actions
The
interrupts
we
chapter
4,
didn't
taken the
of mean
give
any
of
of
the
an
that
have
to
we
be
in
case
preliminary interrupt. By
that have to
routines
.
preliminary
be
executed
actions
micro-operations
before the be
the
call
the interrupt
of
service
These
actions
of
loading
Counter
are
may interrupt
the
clearing
the
all
registers,
the
and
the
the the 1.
micro-operations
for
saving of the Program Word and many others Here external interrupt (Fig. the
.
5.20)
on
and
their
of
VHDL
implementation 5.20
represent
(Fig.
clock
5.21).
The
numbers
left
figure
<-
cycles.
ex_end
'0'
A
1
f_cyc
<-
'
1'
write_mem
<-
'0'
'0'
A A
2. 3.
4
.
vec_num
<-
A
<-
read_mem
<-
<-
'0'
ex_cyc
<-
Re
<<-
PC
A A
<-
MAR
SP
-
A
2
INTA
<-
'1' '1'
MDR
Re
<<-
SP
SP
Re
write_word
<-
write_mem
'1'
ALUJbus
PSW
'1'
<<-
ALU Re
bus
SP
A
<-
MAR
<-
SP
5.
PSWT4)
MAR
<-
A
'1'
MDR
SP
6.
7
.
write_mem
<-
int_vector
<'
8 9
10
read_mem
'
Ri
<-
MDR
<-
Rimm
Ri
<-
11.
12.
ALU_bus
<<-
Rimm
Re
PC
<-
Re
13.
Figure
INTA
'0'
5.20
Micro-operations
for the
external
interrupt
interrupt_action
PROCESS
BEGIN WAIT
ON
proc_state
UNTIL THEN
(proc_state
interrupt);
IF
(int
state
rst)
<ACTIONS
for
the
=
RESET
interrupt>
ELSIF
(int_state
<=
ext)
THEN
<=
1:
f_cyc
vec
<=
1;
<=
ex_cyc
1;
<=
ex_end
<=
'0';
<=
num
1;
'0'
read_mem
'0';
write_mem
'0';
<=
'1','0'
AFTER
period/2;
Re
PC SP
'
c26
c34
<= <=
'1'
AFTER
period/2;
MAR
<= <=
'1';
elk
INTA
UNTIL
'
WAIT
2.
ON
<=
(elk
'1');
cl9
'1','0'
AFTER period/
2;
MDR
<=
Re
-57-
c27
<=
'1','0'
AFTER period/2;
SP
<=
SP-2
write_word
<=
'1';
(elk
=
WAIT ON 3: 4:
WAIT
c3
c4
<=
elk
UNTIL
'1');
write_mem
<=
'1';
(elk = ' 1 ' ) ; AFTER period/2 ;
ALU_bus <= PSW Re <= ALUJdus
MAR
<=
ON
elk
UNTIL
'1','0' '1','0'
AFTER period/2; '1','0' c26 <= AFTER period/ 2; WAIT ON elk UNTIL (elk = '1');
PSW
cl9 c27
<=
SP
(4)
<= <=
<='!';
'1','0'
'1','0'
MDR SP
<=
Re
<=
SP-2
write_word
<=
WAIT
ON ON
<=
elk
1 ; UNTIL (elk
'1');
6
7
write_mem
<=
'1';
UNTIL
WAIT
c23
elk
(elk
'1')
'1','0'
WAIT
ON
mem
elk
<=
8
9 10: 11:
read
'1';
UNTIL
0'
WAIT
cl8
ON
<=
elk
1','
(elk (elk
(elk
'1'
AFTER period/2
=
WAIT
Cl4
ON
<=
elk
1','
UNTIL
0'
'1'
)
)
AFTER period/2
=
WAIT
elO c3
ON
<=
elk
1','
1'
,
UNTIL
0' 0' '
'1'
AFTER
period/2
<=
AFTER period/2
WAIT
ON
<=
<=
elk
1',' 1','
UNTIL
0' 0'
(elk
'1'
12:
c21 c24
AFTER
period/2
AFTER
period/2
=
WAIT
ON
<=
'
elk
UNTIL
<=
(elk
'1'
13:
ELSE
END
proc
c34
state
0'
fetch;
NULL; IF;
no
actions
for
the
OPCODE
ADDRESS
MI VVVI
IMENT
have
END
PROCESS
interrupt_action;
Figure
5.21
VHDL
implementation the
of
the
external
interrupt
the
RESET The
are
The
implementation
error
of
micro-operations
for
also
and not
the
misalignment
interrupts
be
recognized
but the
implemented.
Their
code
should
similar
to
that
of
external
interrupt.
access
5.7.2.6
This
and
The memory
contains
PROCESS
the
protocol
proper
external
signals
operation.
It
uses
the
time
constants
that
were
declared
in
the
package
and one
explained
in
2.3
the
implementation
looks
like
the
in
figure
5.22.
mem_access
PROCESS
BEGIN
WAIT
ON
read_mem,
=
write_mem
UNTIL
(read_mem
'1'
OR
'
write_mem
'
;
<=
IF
(read_mem
c35 c32
<= <= <=
'1')
THEN
address
word
<= <=
<='!';
'1';
'
bus 1 1
<=
MAR
c33
c31
1'
AFTER tsetup;
AFTER
vma
'1'
(tsetup+td) ;
rd_bar
=
WAIT WAIT
UNTIL UNTIL
(mem_rdy (mem_rdy
-58-
'0'); '1');
c36
c31 c35
c32
'1' '0'
'0'
AFTER period/2;
MDR
rd
<=
bar
<= <=
<=
data bus 1
'0'
address
'0'
word
'0'
bus 0 0
<=
high
imp
c33 read
vma
<=
'
mem
'
END
IF
IF;
(write
c35
c37
mem
'1'
'1')
THEN
address
cpu
<= <=
;
'1'
bus
out
<=
MAR MDR
;
word
'1'
=
data
<=
<=
IF
(write
c32
'
'
THEN
word
or
<=
ELSE
c32
<=
'
0'
END
c33 c30
IF;
<= <=
'1'
'1'
vma
<=
1
<=
(tsetup+td)
(mem
;
=
wr
'
'
bar
WAIT WAIT
c35
c37
ON ON
<= <= <=
<= <=
'
mem mem
0'
rdy rdy
0 1
'
'
) )
; ;
address
bus
out
<=
high high
'0' '0'
cpu word
data
<=
<=
imp imp
0 0
<=
'
0'
vma wr
<=
'0'
i
<=
'0'
bar
write
-
mem
END END
IF;
mem
PROCESS
ac
:ess;
Figure If
5.22
to
change
The
memory
of
access
PROCESS
someone
needs
some
the
timing
time
he/she
has
to
change
the
values
of
the
package, then compile the package and file to link it to the new package.
finally
the
main
5.7.3
This
control
The
interrupt
or
unit
unit
issues
main rules
inhibits is to
2.5.
the
After
interrupts
the
to
the
unit.
Its
purpose of
recognize
interrupts
an
according
to
the
interrupt,
maskable,
it
and and
enables
or
disables
it,
type
is
to
then
it
changes
the the
RESET
state
the
CPU to
interrupt
CU
it
the
sends
the
interrupt
take the
(int_state)
is
the
The
in
order,
latter,
to
of
analogous
actions. shown
code
for
the
recognition
interrupt
in
figure
5.23.
:
interrupt_unit
BLOCK
BEGIN
PROCESS
resetjnt
BEGIN
WAIT
ON
elk
'
UNTIL
(elk
IF
( (reset
LAST_EVENT LAST_EVENT
=
>=
(reset'
(reset
'1'
) )
THEN
int_state
proc_state
<= <=
rst;
interrupt;
END
IF;
PROCESS
resetjnt;
END END
BLOCK
interrupt_unit ;
-59-
Figure
5.23
RESET
recognition
by
the
IU
Hints
This
for
future VHDL
comes
users
paragraph
as
little
of
help
to the
future VHDL
mistakes
users
we
so
that
or
they
can
avoid
some solve
the
most
common case
made, have already make them. Especially when these the VHDL compiler implementation to or misunderstanding
works
.
to
learn how to
them
in the
that
a
they
due
mistakes
are
to
general
of
how
this
hardware
description
language
statement
a
sensitivity
WAIT
list
and we
inside
get
the
we
want
to
use
the
statement
will
the
[Error
1594]
Line
Halt
statement
not
allowed
when
process
statement
includes
sensitivity list
The
a
way to the
avoid
it
and
use
WAIT-ON-UNTIL
statement
the
first
line
of
the
the
PROCESS
(after that
BEGIN
statement).
Figure
5.24
shows
error
PROCESS
version.
issues the
:
error
and
figure
5.25 the
free
dummy
c
PROCESS
(a, b)
dummy
PROCESS
BEGIN
<=
BEGIN
a; FOR
WAIT
ON
a;
a,b;
WAIT
c
<=
10
ns;
<=
b;
dummy;
END
WAIT
c
<=
FOR
10
ns;
END
PROCESS
b; dummy;
This
will
PROCESS
Figure
5.24
will
This
PROCESS
an
error
Figure
5.25
PROCESS
pass
issue
for
the
Array
When
shift
shifts
we use
qsim
state
commands
VHDL
SLL
and
an
SRL
to
make
logical
left
and
right
respectively to
array
which
is defined
of
as
qsim
qsim
state_vector
(i.e.
each
element
is
:
type
state)
'0'
then the
variable
shifted elements
is
not
but
'x'.
So,
if
we
have
the
array
"011010"
and
we
perform
three
left
shifts
to
it,
we
will
get
as
result
the
array
:
x"
"0 be
which
can
no
longer
used
in
any
The
operation.
There
make
are our
two
own of
solutions
to
the
above
problem.
first to
is
to
SRL
and
SLL
functions
The
second
is
convert
the
array
-60-
type
qsim_state_vector
to
binary
will
type
and
then
perform
the
shifts.
In
this
case
'O's
fill
:
the
shifted
positions.
comes
explanation
manual of
for that
is the
following
and
from
Mentor
Graphics
"The
value
shift
left
logical
(SLL2)
operator
shifts
the
left
operand
object
and places
in the
right -most
position. value
is
the
predefined
initial
for the
Because
qsim_state
as
TYPE then
'x'
qsim_state
'
x'
'
0'
'
1'
'
z'
is
the
initial
default
value
which
is
placed
in the
empty
'x'
positions.
and
'z'
states
states gave
a great
These
wanted
two to the
trouble
to
our
in
statements
'x'
where state.
we
compare
we
variable sure
:
either
or
'z'
In
'x'
cases
where
were
that
variable
was
in
the
state,
comparison
IF
(var
'x'
THEN
was were
always not
FALSE
and
the
statements
inside
the
IF
statement
a
new
executed.
We
solved
the
to
problem
by developing
package
data type,
A. We
also qsim
the
extra_state a
as
shown
in the
we
in Appendix
from
converted
built to
function them.
convert
the
used
variables
state
extra_state
and
then
the
variables
to
compare
Later,
"...
we
learnt
manual
of
anything
a
compared
to
an
'x'
with
the
equality
operator
false."
returns
and
also,
'z'
"A
as
the
left
or
right
operand
maps
to
an
'x'
This
'='
manual
suggested
to to
use
the
SAME
operator
instead
an
'x'
of or
the
'z'
in
.
cases
we
want
compare
something
to
state
Functions
that
don't
we
work
in
packages
We
had this
strange
experience
steps
of
our
project,
when
were
developing
package
them
main
into
the
then
functions, trying to
resides
one
by
call
one, them
program.
Every
,
function
which
was
"qsim_to_int"
function
still
program
instead
of
the
package
and
it
was
always
giving
run-
2Same
for
the
shift
right
logical
-61-
(SRL)
time
error and
when we
we
were
obvious
think
that
size
calling is the
function
of
it.
and
The
explanation
:
is
not
following
its
data
this
type.
When
we
defined the
input
We
parameter
we
on
didn't
purpose
its
use
did
to
that
wanted
to
function
an
convert
qsim_state_vector we
signal
of
any
size
into
for
define this function in the package, no input parameter and obviously the the
the
are no
right
provide
problems
pointers
when
to
the
actual
parameters.
These
main
solved
run-time
we
define
the
function
in
the
file
and
error
is
issued.
Signal This
assignments
is
actually
not
a
us
VHDL
a
"secret"
but
mistake
we
lot
the
'b'
.
of
time to
'd'
debug
to
the PROCESS
results. value
without
giving the
signal of
expected
figure
'a'
5.26
we
first
the
want
take
the
and
after
execution
the The
<OTHER
result
STATEMENTS>
we
want
will
happen.
The
'
d'
dummy
d
d
END
PROCESS
(a, b)
signal value
finally
value
have the
ever
BEGIN
<=
of
'b'
without
a;
STATEMENTS>
having
the the
made
the
of
'a'.
If
<OTHER
<=
reader
remembers
about we
of
b;
(b
<=
d; )
PROCESS
description
PROCESS
dummy;
serious error
in
the
beginning
and
this
chapter
the At time
Figure he/she
5.26 A
between
the
various
instructions two
events
inside
(signal
of
a
'
PROCESS,
d'
will
understand
that the
assignment)
in
add
figure
5.26
have
But
a
we
finite
number
At
time difference
number
in their
the
execution.
already
words,
know
that
any
of
Ats
the
second
cancels
few
was
scheduled
zero
time
it.
occur
The
same a
same
error
also
in the
to
that
we
inside the
assign signal new
PROCESS
(see
parenthesis
in figure 5.26)
first
value
to
signal
and
later
try
assign
this
to the
another.
The
second
signal
then,
but
will
never
take the
value
of
the
first
because
the
execution
of
the
assignment
to
latter
has
been
scheduled
not
happened
were of
yet. will
If
some
someone
reads
carefully
VHDL.
chapter
5 he/she
a
discover
the CASE
other
tips
about
These
about
statements,
and
the indirect
definition
construction
resolution
function
the
The
user
of
bus.
given
complete
program
listing is
since
in Appendix B.
description
of
Not
many
comments
were
included
most
the
VHDL
parts
is
self-explained
and
of
the important
the
program
were
thoroughly
explained
in this
chapter.
-62-
Simulation
of
the
System
The VHDL simulator for this project is supported by the Mentor Graphic's Quicksim II tool. This simulator can load the program in ASCII form and trace the execution, and it can also
give
all
the
signals
we
need
to to
observe,
simulate
in
the
binary,
we system
hexa
will
decimal
present
most
or
decimal
code
form.
we of
In
the
following
paragraphs
the
that
ran
and
the
important
results
the
simulation.
The
We
code
promised
in
and
5.6 it
the
to
talk
memory BLOCK.
the
RUN
It is activated
by
signal
transfers
to
the
memory
arrays
the the
a
interrupt
RESET
and
vectors,
external which
.
service
a
routines
program of
for
small
with
subroutine
is
called
the
execution
the
RESET
interrupt
arrays.
The assignment of the code uses both memory (2.5) instruction is 16-bits long and the 8 MSbits are Every
while
saved
in memory bank #1
arrays
the
8 LSbits
in memory bank
#2.
Because the
arrays of
that
represent
hexadecimal LSByte
of
the
MSByte
of
and
the the
data
to
locations location
service
external
is
assignment
the
6.1.
The
memory
contain
vectors.
At memory
200H
(512D)
and
begins
at
the
for
the
RESET
interrupt
for
at
routine
220H
(544D)
the
begins
The
the
code
the
interrupt
service
routine. and
program
starts
the
.
memory
location
:
300H
(768D)
subroutine
at
320H
(800D)
memjnit
PROCESS
(run)
AND
BEGIN
IF
((run'
EVENT)
(run
'1'))
THEN
Interrupt
mem_bankl(0)
mem
vectors
"0200"
<=2;
<= <=
bank2(0)
0;
reset
"0220"
<=
2; 32;
64; 96;
external
"0240"
interrupt
<=2;
<=
opcode
error
<=2;
<=
bank2(3)
address
misalignment
FOR
for
I/O
and
stack
(i) (i)
<=
<=
0; 0;
END
LOOP;
for
RESET
<= <=
105;
"6900"
Code
memjbankl
(256)
STPSW
Rl
mem_bank2(256)
0;
Figure
Memory Loading
-63-
(257) (257) mem (258) mem (258) mem (259) mem (259) mem bankl (260) mem bank2 (260) mem bankl (261) mem_bank2 (261)
mem
mem
<=
<= <=
161;
14 3;
"A18F"
^AND
Rl, 01111b
Rl
<= <=
<=
<= <=
<=
<=
"4900"
LDPSW LDHI
"9103"
Rl,03h
"B100"
LDLO Rl,00h
JMP
"7900"
ALW,R1
Code
mem mem
mem mem mem mem mem mem mem mem mem mem mem mem
for external inte rrupt "C900" bankl (272) <= 201; bank2 (272) <= 0;
PUSH
Rl
(273) (273) (274) (274) (275) (275) (27 6) (276) (277) (277) (278) (278)
code
<=
"6900"
STPSW Rl
OR
"C187"
Rl, 00111b
Rl
"4900"
<=
<=
<= <= <= <=
"E900"
"E800"
PSW
"A800"
<=
Program
mem mem mem mem
mem
14 9;
"9506"
LDHI
R5,0 6h
(385)
bank2 (385) bankl (386) bank2 (386) bankl (387) bank2 (387) bankl (388)
bank2
mem mem
mem mem mem mem mem mem mem
<= <=
<=
<=
bankl bank2
bankl bank2 bankl bank2 bankl
mem mem
mem
mem_bank2
mem
mem mem mem
bankl
bank2 bankl bank2
(388) (38 9) (389) (390) (390) (391) (391) (392) (392) (393) (393) (394) (394)
<= <=
<=
<=
<=
<= <= <=
<= <=
<=
6; 181; 32; 189; 0; 14 8; 0; 18 0; 255; 5; 32; 6; 36; 145; 3; 177; 32; 137; 0; 40; 0;
'B520"
LDLO R5,20h
LDSP
'BD00"
R5
R4,00h
9400"
B4FF"
0520"
0624"
'9103"
LDHI
Rl, 03h
'B120"
'8900"
'2800"
Subroutine
mem
mem
bankl
bank2
mem
mem
bankl
bank2
mem
mem_bank2
mem
mem_bank2
mem
mem
mem mem
bankl bank2
(400) (400) (401) (401) (402) (402) (403) (403) (404) (4 04 ) (405) (405)
14
6;
'9204"
LDHI
R2,04h
<=
<= <= <=
4; 178; 176; 6;
131; 206; 0; 236; 0; 219; 0;
'B2B0"
LDLO R2,B0h
ADC PUSH POP
0683"
R6, 01 IB
R6 R4 R3
CE00"
<=
<= <=
'EC00"
<=
<=
'DB00"
STSP
Figure
Memory Loading
-64-
(continued)
mem mem
mem mem mem mem
bankl bank2 bankl bank2 bankl bank2 bankl bank2 bankl bank2 bankl bank2 bankl bank2 bankl
(4 06
(4 0 6 (407
(4 07 (4 08 (4 08 (4 0 9 (4 09 (410 (410
<=
<= <= <= <= <= <= <= <= <=
<=
<=
mem
<=
59; 6; 26; 6; 18; 130, 50; 131; 98; 152, 67; 24; 19; 136; 168; 0;
"3B06"
STW
LDW
"1A06"
"1284"
"3284"
"62
98"
[R3+R0]
,h
"4318"
R3, [R3+R0]
,1
"1988"
SHLL R3,1000B
RET
"A800"
END
END
IF;
PROCESS
init;
Figure
Powering up
As
the
system
figure
6.2
shows,
signal
at
the
beginning
low,
no
of
the
and
when
the RUN
is
still
clock
..
olook
elk
r~
..
4 4
4 4
4 4
4
run una
wr
1 t_nen
4
4
4 4
4
4
4
4
4
4
wr_Jor
r0od_nen rd_bor
word
4
4
:;
:
[XXXX [XXXX
1
ri0n_rdy
reset
4 4
4
lnt_bor into
eddras_bus
4 4
4 4
dote_bus 5QI3
100
200
300
400
Figure
Beginning
clock
of
the
simulation
generated
from the
system
in the
the
previous
chapter,
no
memory.
At
time
200ns
generator and, as we explained data have been transferred yet to when the RUN signal goes from LOW-
to-HIGH
the
clock
cycles
begin
which
to
get
generated
(clock)
and
the
internal
clock
(elk)
distributed
and
it
waits
for
the
RESET
interrupt
the
to
start
and
appendix C
state
are
(page Cl)
shown,
state
the
various
registers
Everything is in
is
idle.
unknown
the
processor's
6.3
Issuing
At
the
RESET
interrupt
time
the
two
clock
cycles.
follows
appendix and
we make the RESET signal HIGH but only for We do that to ensure that our Interrupt Unit rules for the RESET interrupt recognition. As
500ns
650ns
RESET
C shows, didn't
signal
the processor's
change
state
but
it
remained
the
for
more
than
three
(3)
(Fig.
6.3).
Figure
3
up",
RESET
interrupt
the
recognition
The
CPU
"wakes
initializes
state signals of
registers
and
the
flags
Unit
processor's control
The Control
and
the
MAR
proper
with
registers
loads
the
the
address
memory
location
.
that
contains
the interrupt
a
vector read.
(00H)
shows
After
that,
the signal memory read. the Observe the for assignments memory similarity of where 2.8 we first developed figure with 6.4 figure and write protocol. read As we can theoretically the memory
it
performs
6.4
see
the
read
mem
signal
goes
internal
clock
(elk)
freezes. MAR
and
address
is
transferred
to
the
data bus
goes
from the
HIGH, This
after
time
t
the
the
VMA
signal signals
nanoseconds
after
that,
RD_bar
goes
LOW.
in the CPU-memory handshaking unit which triggers the jumper setting will issue some wait external according to the after the second bus cycle (T2) The our case) (one in cycles
counter
.
memory
mem
in the
out
meantime
and
after
time
t0
LOW
transition
of
the
which
RD_signal,
will
puts
data
the
on
the
data
which will
bus
be
resolved state.
the
cpu_data_out
correct
with
is in
the HIGH
on
IMPEDANCE
Finally,
will
data
appear
the
data bus
they
be the
same
-66-
the data
of
the to
mem_data_out
bus
-.
The
operation
and
the data
assignment
the
buses
is
shown
in figure
6.5.
clock 4
? 4 4
elk
1
4 4
1
4 4
vne
wrl
t_n0n
wr_bor
L
4
*
4
1
1
L
4 4
1
4
nen_rdy
reset
lnt_bar
Into
oddreas_bue
XXXX xxxx
X.1B1
4
xxxxx
4XR18FXXXXX4
dete_bus
2100
cycle
1800
1900
2000
Figure
After
Memory
is
bus
read
the
MEMRDY
unit
signal
asserted
by
the
HIGH
CPU-memory
signals get
handshaking
deasserted
state.
(figure
6.4)
the
VMA
and
RDJoar
and
the
of
address
returns
in the
IMPEDANCE
Because
the
mem_data_out
the memory deselection (VMA signal goes LOW) bus returns also to the HIGH IMPEDANCE state
and
after
time to
The
t0TD
the the
consequently
IMPEDANCE
continued
the
data
bus
(Fig.
6.5)
returns
HIGH
state
too.
execution
is
vector
to
s
MAR
and
PC
registers
processor'
state
from
1350ns)
routine
The CPU
and
now
time the
service
immediately
of
that the
program
code,
since a
last
to
instruction
address
the the
interrupt
program
service
routine
is
"jump"
the
that
begins.
zzzzzzzzzzzzzzzz
7350 7490
zzzzzzzzzzzzzzzz
1000100100000000 1000100100000000
zzzzzzzzzzzzzzzz
zzzzzzzzzzzzzzzz
1000100100000000 1000100100000000
zzzzzzzzzzzzzzzz
00000110 0010000
ZZZZZZZZ zzzzzzz
0000001100010100
zzzzzzzzzzzzzzzz
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
zzzzzzzzzzzzzzzz
1001001000000100 1001001000000100
zzzzzzzzzzzzzzzz
1001001000000100 1001001000000100
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
ZZZZZZZZ zzzzzzz
00000011 0010001
zzzzzzzzzzzzzzzz
'address
bus
cpu_dat a_out
'"mem
data
out
'Mat a
bus
Figure
6 5
.
Operation
of
the buses
-67-
Program
Once
execution
and
external
interrupt
HIGH
and
the
RUN
signal
is
stable
the
RESET
interrupt has been issued, the CPU is going to fetch and execute instructions from the memory until it finds a HLT instruction or until the RUN signal returns to the LOW state.
execution the Stack Pointer (SP) is has been we issue the external set, interrupt (the INTJoar goes LOW) We have to be sure that the SP has been set before we issue this interrupt because the CPU saves the flags and the Program Counter into the stack. The service routine for the external interrupt just changes the flags (to show that something is happening) and then it pops the PSW (remember 2.5?) and returns to the program that was under execution while the interrupt was issued. Figure 6.5
set.
During
After
the
program
the
SP
shows
the
various
signals
during
the
INTJoar
assertion.
clock
!
1
j
4 4
elk
4
?
4
4
4
vne wrl
_J
4
*
4
4
te_nen
wr_bor
J
1
+
+ 4
+
4
4
4
4
4
4
reod_ren
rd_bor
word
_J
J
1*
4
4
4
4
4
4
L nen_rdg
reset
t_
4
lnt_per Into
J
4
~
Xxxxx
4
4
&3i&
X03BC
eddre88_bu8
XQ520+XXXXX
do to_bu8
6000
6100
6200
6300
64G0
6500
assertion
Figure
External C
we
interrupt
that
cycle
Looking
signal
again
at
appendix
see
even
of
if the
the
INT_bar
was
asserted
during
(6350ns)
the fetch
the
Then the
the CPU
of
(6000ns)
state, to
13
it
of
wasn't
acknowledged
until
.
completion
execution
the instruction
execute
processor
changed
from
show
to
interrupt,
saves
and
the INTA
signal
was
asserted next
that
the
acknowledged.
In the
cycles,
resumes start
the
CPU
by
changing
the
of
from
executing
routine.
instructions
the
most
of
the
external
interrupt
service
The
contents as
important
C.
'z'
registers
during
fetch
and
the
and
simulation
well
as
the
processor appendix
state
and
the
execute
cycles
are
given
in
The
address are
data
HIGH
buses
are
represented state
by
'x's
shows
when
they
in
the
IMPEDANCE
(Quicksim
the
state
only
in
binary
-68-
Between
the
simulation
results
of
appendix
have
can
been
inserted
taken the
comes
(from
us)
regarding
requests)
more
the
so
that
were
externally
trace C
appendix
(interrupt
simulation appendix
that
the
the
reader
easily.
with
Immediately
contents
after
(page Dl)
register checked
of
the
eight
.
(8)
The
registers
results was
of
the
file
and
in
the
integer
proper
represenation operation
have
been
of
the
system of
verified.
which
That
was
also
the
all
purpose
the
program we
was
shown
in
the
first
we
paragraph.
By
of
the
commands paths
had
ten
put
in
two
of of
the
out
tested
the
data
the
operations
Power the
thirteen
operations
of
out out
the the
twenty-five
formats,
stack
instructions of our instruction set in various subroutine calls and included unconditional jumps,
We
also
operations.
tested
the
we
check
buses
read
and
write
protocol
and
issued
the the
(RESET
unit
and
INTjDar)
to
operation
the
and
the
execution
of
interrupt
through
service
If the
reader
is
patient
on
enough
to
Dl
go
appendices
and
which
start
all
page
Cl
and
respectively,
he/she
will
discover
the
system
has
to
follow
in
necessary order to
steps
that
a
every
computer
execute
program.
-69-
Conclusion
The
a
program
Recommendations
of
objectives
this
thesis
system
-
project
plans
were we
clearly
to
run
fulfilled.
VHDL
Even
on
the most
ambitious
the
and
simulated
obtained.
a great of structural system way behavioral description by the use of BLOCKS and PROCESSes One can start describing the system from the highest level first and then one can gradually decompose every
offers
decomposition
level
into
the
parts
that
until
constitute
that
level.
the
was
This
procedure
can
continue
which
the
of
designer
reaches
lowest
the
use
description
The
of
of
level
use
is the
part
silicon
implementation.
project various
most
difficult
are
the thesis
sure
one
VHDL. the
To
that the be
errors
aspects
with
language
s
understand,
and also
must
able
to
a
deal
the
compiler'
messages
one must
correct
the
in
relatively
events
are
short
time
and
scheduled
during
and
simulation
start
the
description that
with
the
system
representation
be for
that the
various
functions
checked
are
used
in
the
main
file
have
been
previously
operation. simulator
an
small
programs
their
cases
proper
It
is
in the
of a
that
the
aborts
during
the
simulation
design
use
issuing
of
an
error,
then
this is due to an incorrect function, by passing to it wrong parameter types or by assigning its result to an improper signal or variable. It is highly recommended to
a
either
the
VHDL
users,
to
check simple
the
and
proper small
.
operation
of
their
functions Some
thesis
by
incorporate
them
using in
programs,
can
before done
be for
they
this
large
programs
improvements
and
further
Power
work
be
project.
First,
the
Shifter
could
included
be control signals could its and unit space have since we ALU. the to inputs Second, transferred for seven (7) more instructions in our instruction set, some and essential frequently used instructions could be very or for could be used instructions clearing These added. or interrupt software a returning setting the flags, issuing (so there is no more need from an interrupt service routine
inside
the
ALU
as
for
the
POP
PSW
command
at
also
the
end
of
such
routine)
The
address
bus,
could
be
made
20-bits
(1) may a memory space of one the segment concept) and an external pin for could be added so that the addresses of the I/O
mapped
long,
the
don't
to
be
in the
give
memory. of
In
should
the
first the
and
opportunity
new
VHDL
be
desirable
to
real
structural
-
compiler, description
BLOCKS
it
of
the
system
by
-
use
of
COMPONENTS
a
and
not
with
and
PROCESSes
develop
data
bus
without
declaring
.
the
and
auxiliary
signals
cpu_data_out
and
mem_data_out
Finally,
all
the CPU
gates
could
be described at the
control
gate
level
the
structures
that for
the
a
points
represent
could
be
decomposed
to
more
detailed
simulation.
-70-
References
[ARM8 9]
[DAS8
9]
[GLA91]
[GRE88]
Armstrong, James R. : Chip level modeling with VHDL, Prentice-Hall, Inc., 198 9. Subrata : Computer John Dasgupta, Architecture, Wiley & Sons, Inc., 1989. Brett : "SPARC Revealed", BYTE Glass, magazine,
April
1991.
Joseph
and
Greenfield,
D.
&
Wray,
Williams
-
C.
Using
microprocessors
microcomputers
The
Motorola
[HAR77]
family, John Wiley & Sons, Inc., 1988. Hartenstein, Reiner W. : Fundamentals of structured hardware design, North Holland Publishing Company,
Amsterdam
1977.
P.
:
[HAY88]
[INT8
[INT8 [KAI8
Hayes,
INTEL
:
John
Computer
architecture
and
orga
nization,
McGraw-Hill,
8] 8] 9]
Memory
1988
I
.
Components
Inc., Handbook,
and
1988.
Intel
Corpo
ration, INTEL :
Volume
Microprocessor
Peripheral
Handbook
[KAN87]
[KAT83]
Corporation, Microprocessor, Volume I, Kain, Richard Y. : Computer Architecture 1989. Prentice-Hall, Inc., Kane, Gerry : MIPS R2000 RISC Architecture, Prentice Hall, Inc., 1987.
-
Intel
1988.
Katevenis,
Computer
Manolis
Reduced
Instruction
-
Set
Architectures
for
VLSI
ACM
Doctoral
Dissertation,
The
MIT
Press,
:
1985.
Computer
[KLI77]
[LIU8
Kline,
Raymond
M.
Digital
design,
6]
Inc., Microcomputer : Liu, Yu-Ching & Gibson, Glenn A. 8086/8088 Family, Inc., Prentice-Hall, The Systems,
Prentice-Hall,
1986.
Mentor Graphics
:
1977.
[MEN90]
VHDL
System-1076 Graphics
Reference Manual
Alpha
Release,
Douglas
Mentor
[PER91] [SMA84]
Perry,
and
L.
VHDL,
:
Smardzewski,
Elsevier
Richard R.
Microprocessor
scientists
applications
for
Science
:
Publishers
B.V.,
1984.
[TAB90]
Tabak,
Daniel
RISC systems,
LTD,
1990.
-71-
APPENDIX A
PACKAGE LISTING
USE
USE
std.mentor_base.ALL;
std. mentor
extended.
ALL;
PACKAGE
routines
CONSTANT CONSTANT
period
ta
clock
period
Access Write
Time Time
t set up
td
w
Output Enabled to Output Valid Output 3-State from Deselection Address Setup Time VMA HIGH to RD (or WR) LOW
CONSTANT
states
integer
1;
TYPE TYPE
FUNCTION
FUNCTION FUNCTION FUNCTION FUNCTION
extra_
extra
state
IS
(' 0'
,
'1' ,
'X'
,
'Z'
state
vector
IS ARRAY
(NATURAL RANGE
RETURN
RETURN
<>)
OF
extra
state;
integer) integer)
qsim_state_vector;
qsim_state_vector;
bin_to_qsim
wired or
(inp^'. (input
:
qsim_to_extra
FUNCTION END
routines;
(a,b
qsim_state;
state;
PACKAGE
BODY
routines
IS (input
vec
: : :
FUNCTION
int
to
16bit
ret
integer)
RETURN
qsim_state_vector
IS
VARIABLE
VARIABLE
qsim_state_vector
(15
DOWNTO
0)
VARIABLE
BEGIN
dummy inp
integer; integer;
inp
input ;
NOT
ASSERT
(inp
>
65535)
too
REPORT
"Integer
large
to
fit
into
16
bits"
SEVERITY
ERROR;
LOOP
FOR
IN
ret_vec'REVERSE_RANGE
dummy
CASE
0 1
=> =>
ret_vec(i)
ret_vec(i)
=>
:=
:=
'0'; '1';
OTHERS
NULL;
END
END
RETURN
ret_vec;
END
int_toJ6bit; int
to
FUNCTION
8bit
(input
: : :
integer)
RETURN (7
qsim_state_vector
IS
VARIABLE VARIABLE
ret_vec
qsim_state_vector
DOWNTO
0)
VARIABLE BEGIN
dummy inp
integer; integer;
inp
:=
input;
NOT
ASSERT
(inp
>
255)
too large to
REPORT
"Integer
fit
into
bits"
SEVERITY
ERROR;
vec'
FOR
IN
ret
REVERSE_RANGE
LOOP
-Al-
dummy
CASE
WHEN
WHEN END
0 1
=> =>
ret_vec(i)
END
inp
RETURN END
:=
ret_vec;
int
to
8bit;
qsim_to_bin
FUNCTION
(input
:
qsim_state_vector
(15
DOWNTO
0))
RETURN
bit_vector
BEGIN
IS
ret_bin
VARIABLE FOR i
IN
0)
CASE
'
=> =>
ret_bin(i) ret_bin(i)
OTHERS
:=
'1'; '0';
CASE; LOOP;
retjbin;
to_bin;
bin_to_qsim IS
ret_bin
FUNCTION
(input
: :
bit
vector
(15
DOWNTO
DOWNTO
0))
RETURN
qsim_state_vector
VARIABLE VARIABLE
qsim_state_vector
(15
0)
dummy
bit;
LOOP
BEGIN FOR
(dummy
'
0'
)
:=
THEN
'0'
ret Join
<i)
ELSE
retjoin(i)
:=
'1'
END
ret_bin;
END
bin_to_qsim;
qsim_to_extra
FUNCTION
(input
qsim_state)
RETURN
extra_state
IS
BEGIN
CASE
input
WHEN WHEN
WHEN
'
IS
'0'
'0' '
'X'
'X' '
Z'
OTHERS
return
CASE;
qsim_to_extra;
FUNCTION
wired_or
(k,l
ret
qsim_state)
: :
RETURN
qsim_state
IS
qsim
qsim_state;
extra extra
,b
St ate;
dumvec
"state
BEGIN
a
:=
qsim qsim
:=
to to
e stra(k) ;
extra
:=
(1)
dumvec CASE
(a
"00"
&
b)
dumvec
WHEN WHEN WHEN WHEN
WHEN WHEN WHEN WHEN WHEN
IS
'
0'
; ;
;
'X'
"01"
"0Z"
'
0'
"10"
^=
'X'
; ;
;
"11"
ret_qsim
'
l'
'1'
"1Z"
ret ret
qsim
qsim
=
"Z0"
' '
0' 1'
Z'
; ; ;
"Zl"
ret_qsim
"ZZ"
ret_qsim
'
-A2-
OTHERS
=>
ret_qsim
:=
'X';
CASE;
ret_qsim;
RETURN
wired_or;
routines;
-A3-
APPENDIX B
VHDL PROGRAM LISTING
std.mentor_base.ALL;
std.mentor_extended.ALL;
work. routines.
ALL;
ENTITY
system
IS IN
IN IN
PORT
( run
reset
qsim_state;
qsim_state;
qsim_state;
qsim
int_bar
int a
END system;
OUT
state) ;
behave OF
system
IS
RANGE OF integer; interrupt) ;
mem_type
states
IS
ARRAY (natural
<>)
IS IS IS IS
(idle, fetch,
(rst
,
execute,
TYPE
TYPE TYPE TYPE TYPE
interrupts
push_pop_vars
byte_order
jump_conditions
instruction
set
IS IS
(CCR, R1,R2,R3,R4,R5,R6,R7) ; (msb,lsb); (ALW,C,NC,Z,NV,N,V,P) ; (error, sbb, andd, orr,xorr, shll, shrl, shra, ldw, ldb, ldhi, adc, stsp, ldsp, ldlo, ldpsw, stw, stb, stpsw, jmp, call, ret, push, pop, nop, hit) ;
qsim_state_vector qsim_state_vector
qsim_state_vector
= "0000000000000000'
CONSTANT CONSTANT
zeros
unknown
"XXXXXXXXXXXXXXXX' "ZZZZZZZZZZZZZZZZ'
CONSTANT
CONSTANT
highjmp
rom
int
addr
mem_type
(0,2,4,6,8);
=
SIGNAL
SIGNAL SIGNAL
qsim_state
'
0' '
rd_bar, wr_bar, word,mem_rdy wrl_bar, wr2_bar, cs_bar cl, c2, c3, c4, c5,
c6,c7
qsim_state
l';
0' 0'
0'
qsim_state;
qsim_state qsim_state
qsim_state qsim_state
SIGNAL SIGNAL
SIGNAL SIGNAL SIGNAL SIGNAL
cl3
Cl4,cl5,cl6,cl7,cl8,cl9 C20,c21,c22,c23,c24,c25
0'
0'
0'
c31 c37
qsim_state
qsim_state
SIGNAL
SIGNAL SIGNAL
c43
qsim_state
qsim_state qsim_state qsim_state
write_mem
mem_dat a_out
c qs im_st at e_ve ct or
:=
(15
DOWNTO
0)
0)
"ZZZZZZZZZZZ2 ZZZZZ";
data_bus,ALU_bus,PS_bus
or qsim_state_vectc or qsim_state_vectc
PSW
Ri,Rimm,Rc,Ra,Rb
or qsim_state_vectc
or qsim_state_vectc
Rsl,Rs2,Rd
registers
mem_bankl,mem_bank2
or qsim_state_vectc mem_type(0
mem_type(0
0) 0) DOWNTO 0) (2 DOWNTO 0) ;
TO
); 7)
7! 99 >;
TO
proc_state
int_state
f_cyc,
ex_cyc,vec_num
instruction
condition stack_var
instruction_set ;
jump_conditions;
push_pop_vars;
byte (input
:
byte
order; RETURN
FUNCTION
qsim_to_int
qsim_state_vector)
integer
IS
VARIABLE
retint
integer;
-Bl-
BEGIN
ret
int
i
:=
0;
=
FOR
' input REVERSE_RANGE LOOP ASSERT NOT ( (input (i) = 'X') OR (input (i) REPORT "Invalid state in integer SEVERITY ERROR; CASE input (i) IS
IN
'Z'))
conversion"
WHEN WHEN
WHEN END END END RETURN
'0' '1'
=> =>
NULL;
retint
=>
:=
(2**i)
retint;
OTHERS
NULL;
CASE; LOOP;
retint;
qsim_to_int;
BEGIN CLOCK
clk_gen
GENERATOR BLOCK
BEGIN
system_clk
PROCESS
(run,
AND
;
clock)
=
BEGIN
IF
((run'
EVENT)
<=
'1'
(run
AND
'1'))
=
THEN
clock
ELSIF
(clock'
EVENT)
(run
'1'))
THEN
clock
<=
NOT
'
0'
(clock)
;
AFTER period/2;
ELSE
clock
<=
END
END
IF;
system_clk;
PROCESS
END
BLOCK
elk
gen;
__###########f###########################################################
cpu
BLOCK
BEGIN BLOCK
interrupt_unit
BEGIN
resetjnt
PROCESS
BEGIN
WAIT
ON
elk
UNTIL
(elk
'
'
IF
(reset'
LAST_EVENT LAST_EVENT
=
>= <=
(reset'
(3*period)) (4*period) )
AND
AND
(reset
'1'
) )
THEN
int_state
proc_state
<= <=
rst;
interrupt;
END END
IF;
reset
PROCESS
int;
externaljnt
PROCESS
UNTIL
=
BEGIN
WAIT
ON
clock
((clock AND
IF
((int_bar
'0')
<=
<=
(PSW
'1'));
int_state
proc_state
ext;
interrupt;
END
END
IF;
externaljnt;
PROCESS
opcodejnt
PROCESS
BEGIN
WAIT
ON
instruction
=
UNTIL
(instruction
error) ;
IF
(proc_state
fetch)
ope;
THEN
int_state
proc_state
<=
<=
interrupt;
END
IF;
-B2-
END
PROCESS
opcode
int;
addressjnt
PROCESS
UNTIL (write_mem
=
=
BEGIN
WAIT IF
ON
write_mem
=
'1');
THEN
((word
'1')
<=
AND
(MAR(O)
'1'))
int_state
proc_state
addr;
<=
interrupt;
IF;
opcodejnt;
PROCESS
interrupt_unit ;
:
control_unit
BLOCK
BEGIN internal_clock
BEGIN IF
:
PROCESS
=
(clock, write_mem,
OR
read_mem)
( (write_mem
NULL;
'1')
(read_mem
'1'))
THEN
ELSE
elk
<=
clock;
END END
IF;
internal
clock;
PROCESS
interrupt_action
BEGIN
WAIT IF
PROCESS UNTIL
THEN
ON
FOR
proc_state
(proc_state LOOP
interrupt)
(int
state
rst)
<=
'
"i
IN
15
DOWNTO
'
;
<=
(4)
num
<=
<=
<=
<=
0'
0'
1'
f_cyc
read
'
1;
<=
ex
0'
eye
<=
1;
mem
<=
0;
mem
0'
,
write
'
c2
<=
c3
<= <=
0
'
'
;
,
'0'
c6 clO
cl4
0'
c7 ell
<= <=
<= <=
'
0'
c8
cl2
<= <=
<=
0'
'0'
<= <=
<=
0'.
'0'.
'
'0'
'
cl5
0'
'0' '0'
'0'
cl6 c20
c24
0'
cl9
c23
c27 c31
'0'
<=
<=
<=
<=
0'
'0'
'0'
'
0' 0'
'
0'
c28
c32
'0'
<= <=
'0'
0'
0'
'
0'
'0'
c35
<=
'0'
'0'
c36
FOR
IN
TO
LOOP
<=
registers
(i)
0;
=
END
WAIT
c23
LOOP;
ON
<=
elk
UNTIL
(elk
'1') '1')
'1');
'1','0'
AFTER
period/2
=
WAIT
ON ON
<=
elk
<=
UNTIL
'
(elk
(elk
read_mem
'
;
=
WAIT
cl8
elk
UNTIL
UNTIL
'1','0'
AFTER period/2;
WAIT
cl4
ON
<=
elk
(elk (elk
'1');
'1'
1','0'
AFTER period/2;
=
WAIT
ClO
ON
<= <=
elk
1'
, '
UNTIL
0'
1','0'
c3
WAIT
c21 c24
ON
<= <=
elk
UNTIL
1','0'
1','0'
WAIT
ON
elk
'1'
'
1'
proc_state
<=
=
fetch;
ext)
eye
ELSIF
(int
eye num
state
<=
THEN
<=
f
c2
1;
<=
ex
1;
<=
ex
end
<=
'0'
vec
1;
read_mem
'0';
write_mem
<=
'0';
<= <= <=
"<=
<= <=
1','0'
AFTER
period/2;
Re
MAR
PC
1','0'
c26
c34
AFTER period/2;
SP
'
1'
INTA
'
-B3-
WAIT
cl9
c27
ON
<= <=
elk
UNTIL
(elk
'1');
MDR SP
<=
'1','0'
'1','0'
Re SP-2
<=
write_word
<=
'1';
(elk (elk
=
WAIT
write
ON ON
elk
UNTIL
'
'
1 1
'
) )
mem
<=
'
;
=
WAIT
c3
c4 c2
<= <=
elk
UNTIL
'
'
ALUJdus
Re
<=
<=
PSW
<=
WAIT
PSW
cl9
c27
ON
<= <=
elk
<=
UNTIL
;
(elk
'
'
(4)
'1'
'1','0' '1','0'
write
word
<=
'1';
(elk (elk
=
WAIT WAIT
c23
ON
ON
<=
elk
<=
UNTIL
'1');
write_mem
'1';
=
elk
UNTIL
'1')
'1','0'
WAIT WAIT
cl8
ON ON
<=
elk
<=
read_mem
'1';
UNTIL (elk
=
elk
'1')
'1','0'
WAIT
Cl4
ON
<=
elk
'
1',
elk
'
WAIT
ClO
ON
<=
<=
UNTIL
0' 0'
'
c3
1', 1',
elk
WAIT
C21 C24
ON
<=
<=
UNTIL
'
(elk
'
1'
1', 1',
elk
0'
0'
'
WAIT
ON
<=
UNTIL
<=
(elk
'
1'
proc_state
c34
fetch;
'0';
no
actions
ELSE
END END
NULL; IF;
interrupt
for the
OPCODE
ERROR
and
ADDRESS
action;
MISALIGNMENT
have been
implemented
PROCESS
state
PROCESS UNTIL
=
BEGIN WAIT
ON
elk
(elk
+
=
'1');
AND
IF
( (proc_state
f
eye
<=
fetch)
1;
(f_cyc
AND
<
3))
=
THEN
f_cyc
(proc_state
<=
fetch)
(f_cyc
3))
THEN
ex_cyc
1;
<=
proc
state
execute;
=
ELSIF
(proc_state
<=
execute)
+
AND
(ex_end
/=
'1'))
'1')
THEN
THEN
ex_cyc
ex_cyc
state
=
=
1;
AND
ELSIF
((proc
<=
(<int_bar
'1')
f_cyc
1;
<=
'
proc_state
fetch;
;
ex_end
<=
'
ELSE
NULL;
END END
IF;
state;
PROCESS
fetch IF
instr
PROCESS
(proc_state, f_cyc)
THEN
BEGIN (proc_state
=
IF
(f
eye
<=
fetch) 1) THEN
=
'1','0'
C25
ELSIF
(f_cyc (f_cyc
<=
2)
'
read_mem
<=
=
ELSIF
3)
'1','0'
cl8
-B4-
c20
c22
<= <=
'1','
0'
AFTER pe riod/2;
'1',' 0'
AFTER
pe riod/2;
ELSE END
END
NULL; IF;
fetch
IF;
END
PROCESS
:
instr,
decode
PROCESS
VARIABLE
dumbin
UNTIL
qsim_state_vector
(4
DOWNTO
0)
BEGIN
WAIT ON
c20
:=
(c20
DOWNTO
'1'
);
dumbin
CASE
MDR (15
11)
;
<=
dumbin
WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN
WHEN
IS instruction
"00000"
immediate
"00001"
<=
=>
instruction instruction
<= <=
"00010"
"00011"
=> =>
"00100"
sbb;
"00101"
"00110"
=>
=>
shrl;
immediate
"00111"
<=
'1';
<=
=>
instruction
write_word
stw;
"01000"
=>
<=
MDR
(6)
<= <=
'
WHEN WHEN
WHEN
"01001"
=> =>
instruction instruction
ldpsw;
shra;
1'
"01010"
immediate
"01100"
<=
=>
instruction
<=
=
stb;
IF
(MDR
(7)
<=
'1'
THEN
byte
ELSE
msb;
byte
END
"01101"
<=
lsb;
<= <= <=
IF; '0';
stpsw;
write_word
WHEN WHEN
=>
instruction
instruction
"01111"
=>
jmp;
CASE
MDR (2
WHEN WHEN WHEN
DOWNTO
=>
=>
0)
IS
<=
'000"
condition
condition
ALW;
'001"
<=
<=
010"
condition
condition
WHEN
WHEN WHEN WHEN WHEN WHEN
'011"
<= <=
<= <=
'100"
"101"
"110"
111
OTHERS
<=
C; V; N; Z; NV; NC; P;
NULL;
END
"10001"
CASE;
<= <=
WHEN
"10010"
=>
instruction
write_word
call;
WHEN
"10100"
=> =>
instruction instruction
WHEN
andd;
immediate
sign
<=
<=
MDR(7);
<=
<=
MDR(6) ;
ret;
WHEN
"10101"
instruction
instruction instruction instruction
"10110"
WHEN
"10111"
<= <=
WHEN
"11000"
ldlo; ldsp;
orr;
WHEN
immediate
sign
<=
<=
MDR(7);
;
<=
MDR
(6)
<=
WHEN
"11001"
=>
instruction
write_word
push;
'1';
CASE
MDR(10 WHEN
DOWNTO
=>
8)
IS
var
<=
"000"
stack
CCR;
-B5-
WHEN
WHEN
"001"
=>
=>
stack stack
stack stack stack
var
<=
<=
Rl R2
"010" "Oil"
"100"
var var
var var
=> =>
=>
R3
R4
"101" "110"
R5 R6
R7
stack
stack
var var
WHEN END
WHEN
"11011"
"111"
WHEN OTHERS
NULL;
CASE;
<=
=> =>
instruction instruction
stsp; xorr;
WHEN
"11100"
<=
immediate
sign
<=
<=
MDR(7);
;
<=
MDR
(6)
WHEN
"11101"
=>
instruction CASE
MDR (10 WHEN WHEN WHEN WHEN WHEN WHEN
WHEN
pop;
DOWNTO
=>
8)
15
var var var var var var var
var
<= <= <= <= <= <=
<=
"000"
CCR
"001"
=> =>
=>
"010"
"011"
"100"
"101"
"110"
WHEN WHEN
END
"111"
<=
OTHERS
<=
NULL;
CASE;
error;
WHEN END
OTHERS
=>
instruction
BLOCK
stpswjn
BEGIN
IF
( (proc
CASE
execute)
c3
c4
<= <= <=
AND
(instruction
stpsw)
THEN
IS
'1','0'
WHEN
1 2
=>
AFTER AFTER
period/2;
period/2
'1','0'
WHEN
=>
cl7
'1','0'
AFTER
period/2;
ex_end
<=
'
'
WHEN
END END END
OTHERS
=>
NULL;
CASE;
stpswjn;
IF;
PROCESS
ldpswjn
BEGIN
IF
(proc_state
execute)
<= <=
ldpsw) )
THEN
CASE
ex
eye
IS
'1','0'
WHEN WHEN
1 2
=> =>
c8 c2
'1','0'
ex_end
<=
'
'
WHEN END
END END
OTHERS
=>
NULL;
CASE; ldpswjn;
IF;
PROCESS
ldhijn
RFCIN
IF
(proc_state
execute)
ldhi) )
THEN
CASE
ex
eye
IS
=> =>
Cl2
<=
'1','0'
Cl6
<=
'1','0'
ex_end
<=
'
'
OTHERS
=>
NULL;
CASE;
IF;
END
PROCESS
ldhijn;
-B6-
ldlojn
IF
PROCESS
(proc_state,ex_cyc)
=
BEGIN
( (proc_state
CASE
ex_cyc
execute)
cl2
<= <= <=
AND
(instruction
ldlo) )
THEN
IS
=> =>
'1','0' '1','0' '1','0'
WHEN WHEN
1 2
cl6
cl7
ex_end
<=
'
'
OTHERS
=>
NULL;
CASE;
ldlojn;
IF;
PROCESS
:
anddjn
PROCESS
(proc_state,
=
ex_cyc) AND
BEGIN
IF
( (proc_state
CASE
ex_cyc
execute)
(instruction
=
andd)
THEN
IS
=>
WHEN
IF
(immediate
IF
(sign
cl3
cl4
<= <=
'1'
'1','0' '1','0'
ELSE
cl3
<=
'1','0'
END
c8
IF;
<=
'1','0'
ELSE
c7
<= <=
'1',
0'
period/2;
c9
'1','0'
AFTER period/2;
END
WHEN
IF;
(immediate
clO
<=
=
=>
IF
'1')
THEN
'1','0'
AFTER period/2;
ELSE
ell
<=
'1','0'
AFTER period/2;
END
cl
IF;
<= <= <=
'1','0'
AFTER
period/2;
'1','0'
c3
AFTER period/2;
AFTER period/2;
WHEN
'1','0'
=>
cl7
ex_end
<=
'
'
WHEN
OTHERS
=>
NULL;
END
CASE;
anddjn;
END
END
IF;
PROCESS
orr
in
IF
"BEGIN
(proc_state
execute)
AND
(instruction
orr))
THEN
CASE
ex
eye
IS
=>
WHEN
IF
(immediate
'1')
THEN
IF
(sign
cl3
cl4
'1'
THEN
AFTER
period/2;
<= <=
'1','0'
'1','0'
AFTER period/2;
AFTER period/2;
ELSE
cl3
<=
'1','0'
END
c8
IF;
<=
'1','0'
AFTER period/2;
ELSE
C7
<= <=
'1','0'
'1','0'
C9
2;
END WHEN
IF;
(immediate
clO
<=
=
=>
IF
'1')
THEN
'1','0'
AFTER period/2;
AFTER period/ 2;
ELSE
Cll
<=
'1','0'
END
cl
IF;
<= <= <=
'1','0'
AFTER period/2;
'1','0'
C3
c4
'1','0'
-B7-
WHEN
WHEN
=>
Cl7
<=
'1','0'
AFTER period/2;
ex_end
<=
'
'
OTHERS
=>
NULL;
CASE;
orr_in;
IF;
PROCESS
xorrjn
PROCESS
(proc_state,
=
BEGIN IF
( (proc_state
CASE
ex_cyc
execute) IF
xorr)
THEN
IS
=>
WHEN
(immediate
IF
(sign
cl3
cl4
'
1'
<= <=
'1','0'
'1','0'
ELSE
cl3
<=
'1','0'
END
c8
IF;
<=
'1','0'
AFTER period/2;
AFTER period/2; AFTER
period/2;
ELSE
c7
<=
'1','0' '1','0'
c9
<=
END WHEN
IF;
(immediate
clO
<=
=
=>
IF
'1')
THEN
'1','0'
AFTER period/2;
AFTER
period/2;
ELSE
ell
<=
'1','0'
END
cl c2
IF;
<= <= <=
'1','0'
AFTER
period/2;
'1','0'
WHEN
=>
cl7
'1','0'
ex_end
<=
'
'
WHEN
OTHERS
=>
NULL;
END END
END
CASE;
xorr_in;
IF;
PROCESS
jmpjn IF
BEGIN
(proc CASE
state
execute)
<= <=
AND
(instruction
jmp) )
THEN
ex
eye
IS
'1','0'
1 2 3
c8
c4
AFTER
period/2;
'1','0'
AFTER period/2;
CASE
condition
=>
IS
c21 c24
<= <=
'
1','0'
WHEN ALW
AFTER AFTER
period/2; period/2;
'1','0'
ex_end
<=
'
1
=
'
WHEN
=>
IF
(PSW(O)
c21
c24
<= <=
'
'1')
'
THEN
1'
0'
,
'1','0'
ex_end
<=
'
1 1
'
ELSE
ex_end
<=
'
'
END
WHEN
IF;
NC
=>
IF
(PSW(O)
c21
c24
<= <=
'
'0')
' , '
THEN
'1','0'
1'
0'
ex_end
<=
1 1
'
ELSE
ex_end
<=
'
'
; THEN
period
END WHEN
IF;
(PSW
=>
IF
(2)
'1')
c21 c24
<=
'1','0'
AFTER
/ 2;
<=
'1','0'
AFTER period/2;
;
ex_end
<=
'1'
ELSE
ex_end
<=
'
'
END
IF;.
-B8-
WHEN NV
=>
IF
(PSW(l)
c21 c24
<= <=
'0')
THEN
'1','0' '1','0'
ex_end
<=
'
1 1
'
ELSE
ex_end
<=
' '
END
WHEN N
=>
IF;
(PSW
IF
(3)
'1')
'
THEN
c21 c24
<=
<=
'1' , '1'
,
0'
'0'
'
ex_end
<=
1 1
'
ELSE
ex_end
<=
'
'
END WHEN V
=>
IF;
IF
(PSW(l)
c21
<=
'1')
' , 0'
THEN
'1'
c24
<=
'1','0'
ex_end
<=
'
1
1
'
ELSE
ex_end
<=
' '
END
WHEN P
=>
IF;
(PSW
IF
(3)
'
'0')
' , 0'
THEN
c21 c24
<= <=
1'
'1','0'
ex_end
<=
'
1 1
'
ELSE
ex_end
<=
' '
END WHEN
OTHERS
=>
IF; NULL;
END
END
END END
IF;
PROCESS
adcjn
PROCESS
(proc_state,
=
ex_cyc)
"BEGIN
IF
((proc
CASE
state ex_cyc
execute)
AND
(instruction
adc)
THEN
IS
=>
WHEN
IF
(immediate
cl3 c8
<=
'1')
THEN
'1','0'
'1','0'
<=
ELSE
c7
<=
<=
'1','0'
c9
'1','0'
END WHEN
IF;
(immediate
clO cl
<= <=
=
=>
IF
'1')
'1','0'
'1','0'
ELSE
ell cl
<= <=
'1','0'
'1','0'
END WHEN
WHEN END
IF;
<=
'1','0'
=>
cl7
AFTER period/2;
ex_end
<=
'
'
OTHERS
=>
NULL;
CASE;
adcjn;
END END
IF;
PROCESS
sbbjn
PROCESS
(proc_state, ex_cyc)
=
BEGIN
IF
((proc
CASE
state
execute)
AND
(instruction
sbb)
THEN
ex
eye
IS
=>
WHEN
IF
(immediate
cl3 c8
<= <=
'1')
THEN
'1','0'
AFTER period/2;
'1','0'
AFTER period/2;
ELSE
-B9-
c7
<= <=
'1'
,
'0' '0'
AFTER
period/2 ;
c9
'1'
AFTER period/2;
END WHEN
IF;
(immediate
clO cl
c4
<=
<= <=
'1'
=
=>
IF
'
'
THEN
'1'
,
'0' '0' ,
'1'
ELSE
ell cl c4
<= <= <=
'1'
'1' , '1' '
'0'
0'
END
WHEN WHEN
IF;
<=
'1','0'
=>
cl7
AFTER period/2;
ex_end
<=
'
'
OTHERS
=>
NULL;
END
END END
CASE;
sbb
IF;
PROCESS
:
in;
stwjn
PROCESS
(proc_state,ex_cyc)
=
BEGIN IF
( (proc_state
CASE
ex_cyc
execute)
c7
<= <= <=
<=
'1'
AND
'0' ,
'0'
(instruction
stw)
THEN
IS
=>
WHEN WHEN
1 2
c9
=>
'I'
, '1'
ell cl c2 c3
c4
,'0
AFTER period/2;
AFTER period/2; AFTER period/2;
'
0'
<=
<=
,
'1'
,'0
WHEN WHEN
WHEN
3
4
=>
c21
AFTER period/2;
c8
=> => =>
'1'
, '1'
'0' 0'
c4 cl9
'
,
'1'
,'0
5 WHEN 6
WHEN
AFTER
period/2;
write
ex
mem
<=
<=
'1'
'1';
end
=>
OTHERS
NULL;
END END
END
CASE
IF;
stw
PROCESS
in
ldwjn IF
PROCESS (proc_state,ex_cyc)
BEGIN
(proc_state
execute)
<= <=
<= <=
'1'
'1'
AND
0' 0' '
(instruction
ldw) )
THEN
CASE
ex
eye
IS
=>
WHEN
c7
AFTER period/2;
c9
AFTER period/2;
'
WHEN
=>
ell cl
'1
'1' '1' '1' '1'
AFTER
period/2;
c2
<=
<= <= <=
period/2; period/2;
period/2;
c3
c4
WHEN
WHEN
=>
=> => => =>
c21
read
'1
'1'
0
'
mem
<= <=
<=
<=
,
cl8 cl4
'0 '0
'1'
,
'1'
cl5
,'0
ex_end
<=
'
'
WHEN
OTHERS
=>
NULL;
CASE;
IF;
ldwjn;
PROCESS
stbjn
PROCESS (proc_state,ex_cyc)
BEGIN
IF
(proc_state
execute)
<=
AND
(instruction
stb)
THEN
CASE
ex
eye
IS
'1','0'
WHEN
=>
c7
AFTER period/2;
-B10-
c9
'1'
, '1'
'0' '
,
WHEN
=>
ell
cl c2
0'
'1'
'0'
,
'1'
, '0'
c3
c4
WHEN WHEN
3
4
=>
=>
AFTER period/2; AFTER period/2; IF (byte = msb) THEN ' IF (MAR( 0 ) 0 ' ) THEN
c21
,
c8
<=
'1'
'0'
c4
<=
1','0'
ELSE
c2 c3
<= 1','0' 1','0'
<=
END ELSE IF
IF;
(MAR( 0 )
C2
<= <= <=
'
'
THEN AFTER
period/2 ;
c3 c4
ELSE
c4
<=
1','0'
END
END WHEN WHEN
IF; IF;
'
5 6
=>
cl9
<=
1' ,
'0'
AFTER period/ 2;
=>
write_mem
ex_end
<=
'1'
WHEN END
END END
OTHERS
=>
NULL;
CASE ;
stb
IF; in;
PROCESS
:
ldbjn
IF
PROCESS
(proe_state,
=
ex_cyc
BEGIN
( (proc_state
CASE
ex eye
execute)
c7
<=
'1'
AND
(instruction
'
'
ldb) )
THEN
IS
=>
,
WHEN
1 2
'0 '0
'
c9
<= <=
<= <= <= <=
'1' , '1'
WHEN
=>
ell cl
0'
' '
'
, '1'
, '1' , '1' , '1' , '1' ,
c2 c3 c4
'0 ' 0
'0
AFTER
period/2
'0
'
'
0'
WHEN
WHEN
3 4
=>
=
c21
read
<=
>
mem
<=
<=
'
'1';
0'
=
WHEN WHEN
5 6
=>
cl8
'1'
=>
IF
(MAR(0)
IF
(sign
cl2
<= <=
'0') '0')
'1','0'
'1','0'
cl3
ELSE
cl2
<= <= <=
'1','0' '1','0' '1','0'
cl3
cl4
END
IF;
(sign
cl2
<=
=
ELSE IF
'
0' )
THEN
AFTER
period/
'1','0'
2;
ELSE
cl2 cl4
<= <=
'1','0' '1','0'
AFTER
period/2;
AFTER period/2;
END
END WHEN
IF; IF;
<=
'1','
0'
=>
cl5 ex
AFTER period/2;
end
=>
<=
'
WHEN
END
OTHERS
NULL;
CASE;
END
IF;
-Bll-
END
PROCESS
ldbjn;
nopjn
PROCESS
(proc_state,
=
ex_cyc)
AND
'
BEGIN IF
( (proc_state
CASE
ex_cyc
execute)
ex_end
=>
(instruction
'
nop)
THEN
IS
=> <=
WHEN
NULL;
CASE;
nopjn;
IF;
END
PROCESS
:
hltjn
IF
PROCESS
(proc_state,
=
ex_cyc) AND
<=
BEGIN
( (proc_state
CASE
ex_cyc
execute)
(instruction
hit))
THEN
IS
=>
WHEN
proc_state
=>
idle;
WHEN END
END
OTHERS
NULL;
CASE;
hit Jn;
IF;
END
PROCESS
:
ldspjn
IF
PROCESS
(proc_state,
=
ex_cyc)
BEGIN
( (proc_state
CASE
ex_cyc
execute)
c8
c4
<= <=
AND
(instruction
ldsp) )
THEN
IS
=> => =>
'1','0'
'1','0'
c4 3<= ex_end
'1','0'
AFTER period/2;
;
<=
'
'
WHEN
OTHERS
=>
NULL;
END END
END
CASE;
ldsp_in;
IF;
PROCESS
stspjn
PROCESS (proc_state,ex_cyc)
state
ex_cyc
=
BEGIN
IF
((proc CASE
execute)
<= <=
AND
(instruction
stsp)
THEN
IS
'1','0'
WHEN
1 2
=> =>
c42
cl7
'1','0'
WHEN
WHEN END
ex_end
<=
'
'
OTHERS
=>
NULL;
CASE;
stspjn;
END END
IF;
PROCESS
call_in
BEGIN
IF
((proc CASE
state
execute)
call))
THEN
ex
eye
IS
=>
WHEN
1 2
c2
<=
'1','0'
AFTER
period/
2;
c8
'1','0'
AFTER period/2;
AFTER period/2;
'1','0'
WHEN
=>
cl9
c26 c4
'1','0'
'1','0'
3 WHEN 4
WHEN
=>
write_mem
c24<=
<=
'1';
AFTER
period/2;
'1','0'
=>
C27
<=
'1','0'
AFTER period/2;
ex_end
<=
'
'
OTHERS
=>
NULL;
CASE;
calljn;
IF;
PROCESS
retjn
BEGIN
IF
((proc
state
execute)
AND
(instruction
ret))
THEN
-B12-
CASE
ex
eye
IS
=>
=>
1 2
<= <=
'1'
'1'
'0' '0'
3 4
mem
<=
<
'1
'0'
'
cl8
cl4 clO c3
5 WHEN 6
WHEN
0'
'0'
0'
'0'
=>
c24
ex
end
=>
<=
NULL;
CASE;
ret
IF;
PROCESS
:
in,
pushjn
PROCESS
(proc_state,
=
ex
~~
eye)
BEGIN
IF
( (proc_state
CASE
ex_cyc
execute)
AND
(instruction
push)
THEN
IS
WHEN
=>
CASE
stack_var
IS
c8
<=
'
CCR
=>
NULL;
=>
1'
, 0'
WHEN OTHERS
AFTER period/2;
CASE;
stack_var
=>
=>
CASE
IS
c4
<= <=
'1' , '1' , '0' '0'
WHEN CCR
WHEN END WHEN WHEN
c3
OTHERS '1','0
'1'
,
=>
c4
<=
'1',
AFTER period/2;
CASE;
<= <= <=
3
4
=>
cl9
c2
AFTER
period/2
=>
c27
'
1'
,
'0 ' 0
1
'
write_mem
<=
'
'1';
;
ex_end
<=
WHEN END
END END
OTHERS
=>
NULL;
CASE; IF;
push_in;
PROCESS
pop
in
IF
PROCESS
(proc_state, ex_cyc)
=
BEGIN
( (proc_state
CASE
ex_cyc
execute)
<= <=
AND
(instruction
pop)
THEN
IS
c2
WHEN
WHEN WHEN
=> =>
8 6
'1','0'
c2
'1'
,
'
0'
'
WHEN WHEN
3 4
read_mem
<=
cl8
cl4
<=
<=
'1' , '1'
,
'0' '0'
5 WHEN 6
CASE
stack_var
WHEN
CCR
=>
'1
0'
AFTER period/2;
AFTER
period/2 ;
<= <=
'1','0' '1','0'
WHEN
OTHERS
<=
'
=>
cl5
<=
END OTHERS
CASE;
1
'
ex_end
WHEN
=>
NULL;
CASE;
popjn;
IF;
PROCESS
shlljn
PROCESS (proc_state,ex_cyc)
=
BEGIN
IF
((proc
CASE
WHEN WHEN WHEN
state
execute)
<= <= <= <=
AND
(instruction
period/2;
shll)
THEN
ex~cyc
IS
cl3 c8
'1','0'
'1','0'
1 2
=>
AFTER
=> =>
c6
Cl7 ex
'1','0' '1','0'
end
<=
'
'
-B13-
WHEN
OTHERS
=>
NULL;
END
shrljn
PROCESS
(proc_state,
=
ex_cyc)
AND
BEGIN
IF
( (proc_state
CASE
ex_cyc
execute)
<= <=
<= <=
(instruction
shrl)
THEN
IS
cl3 c8
'1','0'
'1','0' '1','0' '1','0' ' '
WHEN
WHEN
1 2
=>
=> =>
c5
cl7
WHEN
WHEN END END
AFTER period/2;
ex_end
<=
OTHERS
=>
NULL;
CASE; IF;
shrljn;
END
PROCESS
:
shra_in
PROCESS
(proc_state,
=
ex_cyc) AND
BEGIN IF
( (proc_state
CASE
ex_cyc
execute)
<= <= <= <=
-
(instruction
shra)
THEN
IS
cl3 c8
'1','0'
1 2
=>
AFTER period/2; AFTER period/2; AFTER period/2; AFTER period/2; AFTER period/2;
=>
c5
c6
=>
c^7
OTHERS
BLOCK
execute
Jnstr;
;
BLOCK
control_unit
ALU_regs
PROCESS
(c7,
c8
c9)
VARIABLE
dumint
dumbin AND
integer;
qsim_state_vector
VARIABLE
(15
DOWNTO
0)
BEGIN
IF
<(c9'EVENT)
dumint
:=
(c9
'1'))
THEN
;
qsim_to_int
(Rs2)
dumbin(15
DOWNTO
0)
:=
int_to_16bit (registers
(dumint) )
Rb
END
<=
dumbin;
=
IF;
NOT((c7
ASSERT
'1')
AND
(c8
'1'))
Multiple
sources"
REPORT
"Ra
assignment
error
SEVERITY
ERROR;
AND
IF
((c7'
EVENT)
:=
(c7
dumint
Ra END
<=
qsim_to Jnt
'1')) (Rsl)
THEN
dumbin (15
DOWNTO
0)
:=
))
dumbin;
AND
IF;
((c8'EVENT)
dumint
<=
:=
IF
(c8
'1'))
THEN
qsim_to_int
(Rd)
dumbin(15
DOWNTO
0)
:=
))
Ra END
END
dumbin ;
IF;
ALU_regs;
PROCESS
Rc_reg
PROCESS
(c40, c41,
=
c42
c29) (c41
=
BEGIN ASSERT
NOT(((c40
((C40
((c40
((c41
AND
AND
(c42
AND AND
(c29
(c42
OR
OR
OR
OR
-B14-
((c41 (<c42
REPORT
'1') '1')
AND
AND
(c29 (c29
'1')) OR '1')))
Multiple
sources"
"Rc
assignment
error
ERROR; IF ((c40'EVENT) AND Rc <= ALU_bus; END IF; ((c41' IF EVENT) AND Rc <= PS_bus; END IF; ((c42' IF EVENT) AND Rc <= SP; END IF; ((c29' IF EVENT) AND
Rc END
END
<=
PC-
SEVERITY
(c40
'1'))
THEN
(c41
'1'))
THEN
(c42
'1'))
THEN
(c29
'1'))
THEN
IF; Rc_reg;
PROCESS
:
ALU
PROCESS
qsim_state;
qsim_state_vector qsim_state_vector qsim_state_vector
(2
DOWNTO
0)
j
&
c2
integer;
&
c3
(cl
' 1'
&
c4);
IF
(cl
THEN
=
ASSERT
NOT((clO
'0')
AND
error
(ell
'0'
))
Rimm missing
REPORT
'
"ALU
1'
input
THEN
Rb
or
SEVERITY IF
ERROR;
(clO
operand
:=
Rimm; Rb;
ELSE
operand
:=
END
IF;
concat
CASE
IS
WHEN
"1000"
"1111"
=>
IF
(concat
"1000")
PSW(0)
'
THEN
carry
ELSE
:=
END FOR
sum
carry IF;
&
:=
0'
i
:=
IN
Ra'REVERSE_RANGE
operand
LOOP &
(Ra(i)
sum
carry)
CASE
IS
000"
WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN END END
=>
=>
=
res
0'; carry
l'
: :
:
'0' '
001"
carry carry
0'
'010"
>
1'; carry
0'
'0'
011"
: : : :
'
'
1'
0'
'100"
1'; carry
0'
'101"
carry
'1'
110"
111"
'1'
'1'
OTHERS
=>
NULL;
CASE;
=
LOOP;
(concat
IF
"1000")
carry;
<=
THEN
PSW(0)
<=
carry bit
PSW
AND ( (NOT(Ra (15) ) ) (NOT (operand (15) ) ) (res (15))) OR (((Ra(15))) AND AND (operand (15) ) AND (NOT (res (15) ) ) ) ;
(1)
ELSE
END WHEN
"1001"
NULL; IF;
:=
=>
borrow FOR
PSW(0)
&
IN
:=
Ra'REVERSE_RANGE
LOOP
&
diff
(Ra(i)
diff
operand
(i)
borrow)
CASE
IS
-B15-
WHEN
"000"
=>
res
(i)
'0';
borrow
:
=
'0'
WHEN
WHEN WHEN
"001"
=>
res(i) res(i)
res
'l';
borrow
:
=
'0'
"010"
=>
'l';
borrow
:
=
'0'
"011"
=>
(i)
(i)
'0';
borrow
:
=
'1'
"100"
=>
res
'1';
borrow
:
=
'
0'
"101"
=>
res(i)
res
'0'
;
:
=
borrow
"110"
'1'
=>
(i)
'0'
;
:
=
borrow
"111"
'1'
=>
res(i)
'1';
borrow
:
=
'1'
NULL; CASE; END LOOP; PSW(0) <= borrow; carry bit PSW(l) <= ((Ra(15)) AND (NOT (operand (15) ) ) AND (NOT(res(15) ) ) ) OR ( (NOT (Ra (15) ) ) AND (operand (15) ) AND (res (15) ) ) ;
=>
WHEN OTHERS
END
WHEN
"1010"
=>
res
:=
Ra AND
<=
operand;
PSW(0) PSW(l)
WHEN
"1011"
<=
'0'; '0';
OR operand;
'0'
carry bit
overflow
bit
=>
res
:=
Ra
<=
<=
PSW(0) PSW(l)
WHEN
"1100"
'0';
XOR
'
=>
res
:=
Ra
<= <=
operand;
; ;
PSW(0)
WHEN END IF
0'
OTHERS
=
=>
PSW(l) NULL;
THEN
'0'
CASE;
(concat
"1111")
NULL;
ELSE IF
(res
PSW
zeros)
<=
THEN
zero
(2) (2)
'1';
'
bit
ELSE
PSW
<=
0'
END
IF;
(res (15)
PSW
=
IF
(3) (3)
<=
'1') '1';
'0'
THEN
negative
bit
ELSE PSW
<=
END
IF;
<=
END
c4
IF;
res;
<=
'1','0'
ALU_bus
AFTER
period/2;
ELSE CASE
concat
IS
=>
=>
WHEN
"0000"
NULL;
ALU_bus
c40
<=
<=
WHEN WHEN
"0001"
Ra;
AFTER period/2;
'1','0'
"0010"
=>
IF
(clO
c4
'1')
<=
'1'
THEN
ALU bus
Rimm;
AFTER period/2,
'0'
<=
AFTER period;
ELSE ALU_bus
c40
<= <=
Rb;
AFTER period/2;
'1','0'
END
WHEN
"0011"
IF;
<=
=>
ALU_bus
c4
PSW;
AFTER
period/2;
<= <=
'1','0'
WHEN WHEN
"0100"
=> =>
PSW
Ra;
=
"0101"
IF
(clO
PSW
'1')
THEN
<=
Rimm;
ELSE
-B16-
PSW END
<=
Rb;
DOWNTO
<=
IF;
i
IN
:=
WHEN
"0110"
=>
FOR
0
Ra
LOOP
END
c40
(j)
<=
'1','0'
WHEN
"0111"
=>
FOR
IN
:=
15 DOWNTO
j
END
c40
ALUJms
i-8; (i)
Ra
(j)
LOOP;
<=
'1','0'
AFTER period/2;
WHEN END
OTHERS
=>
NULL;
CASE; ALU;
:
END
END
IF;
PROCESS
POWER_SHIFTER
PROCESS
dumint, j
"
dumbit
res
bit_vector (15
DOWNTO
0)
qsim_state_vector qsim_state_vector :
concat
store_sign
qsim_state;
IF
qsim_to_int
ASSERT
NOT
(c6
>
8))
shifts"
REPORT
"POWER
SHIFTER
error
Number
of
SEVERITY
store_sign
ERROR; := Ra(15);
& c6) ;
concat
:=
(c5 IS
"00"
CASE
concat
WHEN WHEN
=> =>
NULL;
"01"
:=
16
PSW(0)
<=
dumint; Ra(j) ;
0)
SLL
:=
:=
qsim_to_bin
(Ra)
dumint;
bin_to_qsim (dumbit
(15
DOWNTO
-
WHEN
"10"
=>
:=
dumint
<=
0) 1;
;
PSW(0)
dumbit
res
Ra( j)
dumbit (15
:=
DOWNTO
0)
SRL
:=
:=
qsim_to_bin
(Ra)
dumbit
dumint;
bin_to_qsim (dumbit
(15
DOWNTO
-
0)
1;
;
WHEN
"11"
=>
:=
dumint
<=
PSW(0)
dumbit
res(15
Ra(j)
dumbit (15
:=
DOWNTO
0)
SRA
:=
:=
qsim_to_bin
(Ra)
dumbit
dumint;
DOWNTO
0)
bin_to_qsim (dumbit
WHEN
OTHERS
=>
NULL;
END
IF
CASE;
(res
PSW
=
zeros)
<=
'1'
THEN ;
(2)
ELSE
PSW
<=
'0';
END
IF;
(res
PSW
=
IF
'1')
'1'
THEN
<=
ELSE PSW
<=
'0'
IFn)(:(store_sign
'1')
AND
(res
(15)
'0'))
THEN
psw(i)
ELSE
<=
'l'; '0';
END
PSW(l) IF;
bus
<= <=
<=
PS
c41
res;
'1','0'
AFTER
period/2;
END
IF;
-B17-
END
PROCESS
:
POWER_SHIFTER;
PROCESS
stack_ptr
VARIABLE
dumbin
concat
qsim_state_vector
(15 (1
DOWNTO
VARIABLE VARIABLE
qsim_state_vector
DOWNTO
0) 0);
dumint
=
integer;
OR
'1')
(c28
error
'1'))
AND
(c43
'1'))
"SP (c27 IS
assignment
Multiple
sources"
SEVERITY
concat
:=
ERROR;
&
c28);
=>
CASE
concat
WHEN
"01"
dumint := qsim_to_int (SP) ; dumint : = dumint + 2 ; := dumbin (15 DOWNTO 0) int_to_16bit (dumint) ;
SP
<=
dumbin;
=
-
WHEN
"10"
=>
dumint := qsim_to_int (SP) ; dumint : dumint 2; dumbin(15 DOWNTO 0) := int_t oJ 6bit (dumint ) ;
SP
<=
dumbin;
OTHERS
=>
NULL;
(c43
=
CASE;
(c43'
EVENT)
Rc;
AND
'1'))
THEN
SP
<=
IF;
stack_ptr;
PROCESS
:
Ri_reg
PROCESS ON
cl8
BEGIN WAIT
UNTIL
(cl8
'1');
<=
Rimm_reg
PROCESS (cl2
cl3,
: :
cl4
)
(2
DOWNTO
concat
ptr
qsim_state_vector
0)
integer;
&
cl4);
(cl2
IS
"000"
&
cl3
CASE
concat
NULL;
Rimm FOR
<=
"001"
"010"
IN
Ri; 5 DOWNTO 0
LOOP
;
Rimm
(i)
<=
Ri
(i)
LOOP
=>
FOR
LOOP; i IN 5 DOWNTO
<=
LOOP
;
Ri
(i)
(Ri(5)
FOR
'1')
15
THEN
IN
DOWNTO
<=
'1'
6
;
LOOP
FOR
IN
15 DOWNTO
<=
'0'
6
;
LOOP
IF;
i
IN
=>
FOR
DOWNTO
<=
LOOP
;
Rimm(i)
LOOP; FOR i IN 15
END
Ri
(i)
8
;
DOWNTO
<=
'0'
LOOP
Rimm(i)
END WHEN
"101"
=>
FOR END
LOOP; i IN 7
Rimm(i)
DOWNTO
<=
LOOP
;
Ri
(i)
LOOP;
-B18-
IF
(Ri(7)
FOR
'1'
THEN
IN
15 DOWNTO
<=
'
8
;
LOOP
1'
IN
15 DOWNTO
<=
' 0'
8
;
LOOP
=>
FOR i
IN
7
:=
DOWNTO
LOOP
ptr
8+i;
<=
END
Rimm(i) LOOP;
IN
Ri
(ptr)
FOR i
END
WHEN
"111"
Rimm
(i)
7
:=
LOOP
LOOP;
IN
=>
FOR i
LOOP
ptr
8+i;
<=
END
Rimm(i) LOOP;
Ri
(ptr)
THEN
IF
(Ri(15)
FOR
'1')
<=
IN
15 DOWNTO 8
' 1'
LOOP
IN
15 DOWNTO
<=
' 0'
8
;
LOOP
Rimm(i) LOOP;
END
WHEN
OTHERS Rimm
>
IF; NULL;
END
END
CASE;
reg;
PROCESS
reg_file_ptrs
PROCESS
UNTIL
BEGIN
WAIT
ON
<= <= <=
c20
(c20
'
'
Rd
Rsl Rs2 END
MDR(10
DOWNTO DOWNTO
DOWNTO
8);
MDR(5
MDR(2
3)
;
0);
PROCESS
reg_f ile_ptrs
reg
file
_
PROCESS
VARIABLE VARIABLE
VARIABLE
dumbin
concat
(15 (2
DOWNTO DOWNTO
0);
0)
dumint
ptr
integer;
VARIABLE
integer;
&
cl7) ;
BEGIN
concat
:=
(cl5
&
cl6
CASE
concat
IS
=>
"000"
WHEN
"001'
NULL;
IF
WHEN
=>
(Rd
"000")
THEN
NULL;
ELSE dumint
:=
qsim_to_int
(Rd)
registers
(dumint)
<=
qsim_to_int
(Rc)
END
"010'
IF;
:=
WHEN
=>
dumint
qsim_to_int
(Rd)
dumbin (15
DOWNTO
0)
8
:=
int
FOR
to_16bit (registers
(dumint) )
IN
15
DOWNTO
LOOP
ptr
END
LOOP;
registers
(dumint)
DOWNTO
<=
qsim_to_int
(dumbin)
WHEN
"011"
=>
dumint
:=
qsim_to_int
(Rd)
dumbin (15
0)
:=
int
FOR
to_16bit (registers
(dumint) )
IN
DOWNTO_0
LOOP
-B19-
dumbin (i)
END
WHEN WHEN
"100"
:=
Rimm(i);
<=
LOOP;
registers
=>
(dumint)
(dumint)
0
TO
qsim_to_int
dumint
FOR i END
(dumbin)
:=
qsim_to_int
<=
(Rd)
qsim
registers
"101"
to
~
int (Rimm) ;
=>
IN
LOOP
<=
registers
(i)
0;
LOOP;
WHEN
OTHERS
regjile;
:
=>
NULL;
END END
CASE;
PROCESS
mem_data_reg
BEGIN
ASSERT NOT((cl9 = '1') AND REPORT "MDR assignment SEVERITY ERROR; IF ( (cl9' EVENT) AND (cl9 =
MDR
<=
'1'))
Multiple
THEN
sources"
'1'))
=
Rc;
ELSIF
EVENT) AND (c36 '1')) THEN data_bus; ASSERT NOT( (data_bus highjmp) OR (datajbus unknown)) bus" REPORT "MDR assignment error Floating
MDR
<=
= =
((c36'
SEVERITY
ELSE END END
ERROR;
NULL; IF;
PROCESS mem_data_reg;
:
mem_addr_reg
BEGIN
PROCESS (c21
VARIABLE ASSERT
dumbin
=
qsim_state_vector
(15 DOWNTO
0)
NOT(((c21
((c21 ((c21
AND AND
(c23
AND AND
AND AND
assignment
ERROR; ((C21' IF '1')) THEN EVENT) AND (c21 MAR <= Rc; (C25' ELSIF '1')) THEN EVENT) AND (c25 ( MAR <= PC; ((c23' ELSIF '1')) THEN EVENT) AND (c23 int_to_16bit (rom_int_addr (vec_num) ) dumbin (15 DOWNTO 0)
= = =
:=
MAR
<=
dumbin;
EVENT)
AND
ELSIF
ELSE
((c26'
(c26
'1'))
THEN
MAR
<=
SP;
NULL;
END END
IF;
mem_addr_reg;
PROCESS
prgm_cntr
PROCESS
(c22,
c24 :
)
(15
DOWNTO
VARIABLE VARIABLE
dumint dumbin
=
integer;
qsim_state_vector
0);
BEGIN ASSERT
NOT(((c22
'1')
AND
(c24
'1')))
Multiple
sources"
REPORT
"PC
assignment
error
SEVERITY IF
ERROR;
AND
<<c22'EVENT)
dumint dumint
PC
<=
:= :=
(c22
+
qsim_to_int
'1')) (PC) ;
THEN
dumint
DOWNTO
2;
:=
dumbin(15
ELSIF
((c24'
0)
int_to_16bit (dumint) ;
=
dumbin;
EVENT) Rc;
AND (c24
'1'))
THEN
PC
<=
-B20-
ELSE
END
NULL; IF;
END
PROCESS prgm_cntr;
:
mem_access
PROCESS
read_mem,write_mem
BEGIN WAIT ON IF
UNTIL
(read_mem
OR
write_mem
(read_mem
c35
c32
'1')
THEN
address
word
vma
<= <=
<='!'; <='!';
<=
bus
1
1
<=
<=
MAR
c33
c31
<=
WAIT WAIT
c36 c31
c35 c32
'1'
rd_bar
=
ON mem_rdy
<=
<=
'1','0' '0' '0'
'0'
UNTIL
(mem_rdy
'0'); '1');
MDR
<=
AFTER period/2;
databus
<=
rd_bar
1
<=
<=
<= <=
address
word vma
<= <=
bus 0 0
highjmp
c33
'0'
read_mem
<=
'0';
END IF
IF;
(write_mem
c35
c37
<= C=
=
'1')
THEN
address
'1'; '1';
=
bus
1
or
<=
MAR MDR
cpu_data_out
<=
IF
(write_word
c32
<=
'1'
'1')
THEN
word
<=
ELSE
c32
<=
'0'
;
<=
END
c33 c30
IF;
<=
<=
WAIT
'1'
vma
1
<=
wr_bar
=
'0');
WAIT
c35
c37 c32
ON
<= <=
<=
<=
mem
'0'
rdy UNTIL
(mem_rdy
'1')
address
bus 0
<=
'0' '0'
'0'
cpu_data_out word
vma wr
<=
'
<=
highjmp high_imp
<=
<=
c33 c30
0
<=
<=
'0' 0'
bar
write_mem
END END
IF;
mem_access;
PROCESS
i_o
PROCESS (C30,c31,c32,c33,c34,c35,c37)
((c30'
BEGIN
IF
EVENT)
<=
AND
;
(c30
AND
'1'))
=
THEN THEN
wr
bar
'0'
ELSIF
T(c30'EVENT)
<=
' 1'
(c30
'0'))
wr_bar
ELSE
NULL;
END
IF;
<(c31'
IF
EVENT)
AND
(c31 AND
'1'))
=
THEN
ELSIF
7(c31'
rd_bar
<=
(c31
'0'))
THEN
ELSE
NULL;
END IF
IF;
((c32'EVENT)
word
<=
' 1'
AND
;
(c32
'1'))
=
THEN
ELSIF
ELSE
<(c32'EVENT)
<=
'0'
AND
(c32
'0'))
THEN
word
NULL;
END
IF;
((c33'
IF
EVENT)
AND
(c33
'1'))
-B21-
THEN
vma
<=
'
'
((c33'
EVENT)
0
'
AND
(c33
'0'))
THEN
vma
<=
'
NULL; IF;
<(c34'
EVENT)
<=
' 1'
AND
;
(c34
AND
'1'))
=
THEN THEN
inta
ELSIF ELSE
END
((c34'
EVENT)
'
(c34
'0'))
inta
<=
0'
NULL; IF;
IF
((c35'EVENT)
address_bus
addrjsb
<=
AND
<=
(c35
MAR(15
AND
'1'))
DOWNTO
=
THEN
1);
THEN
MAR(O);
(c35
0
<=
'
ELSIF
((c35'
EVENT)
14
'0'))
;
IN
DOWNTO
LOOP
Z'
addressjDus
(i)
;
LOOP;
<=
' Z'
addrjsb
NULL; IF;
((c37'
IF
EVENT)
AND
<=
(c37
'1'))
=
THEN
THEN
cpu_data_out
MDR;
(c37
ELSIF
((c37'
EVENT)
AND
'0'))
cpu_data_out
<=
highjmp;
ELSE
MEMORY
BANK
SELECT
:
UNIT
mem_bank_sel_unit
BLOCK
BEGIN
PROCESS
mbsu
(word,
VARIABLE BEGIN
qsim_state;
(NOT(wr_bar) ) AND (word) ; (NOT (word) ) ; (NOT (wr_bar) ) AND (addrjsb) AND (NOT (addrjsb) ) AND (NOT (wr_bar) ) AND (NOT (word) ) int_3 '0')) ASSERT NOT((rd_bar '0') AND (wr_bar REPORT "wr bar & rd_bar cannot be both
int_l
:=
int
:=
:=
LOW"
SEVERITY
oe_bar cs_bar
wrl_bar wr2_bar
<= <=
ERROR;
rd_bar;
NOT (vma);
NOT(int_l
<= <=
OR int_3 OR
NOT (int
int
2) ;
END
PROCESS
mbsu;
END
BLOCK
mem
bank
sel
unit;
__###########f####f
###?###################################################
CPU MEMORY
cpu
TIME
:
HANDSHAKING
UNIT
mem_time_unit
BLOCK
"BEGIN
handshake
:
PROCESS
count :
VARIABLE
integer;
UNTIL
BEGIN
WAIT
ON
rd
bar,wr_bar
(rd_bar
=
'0')
OR
(wr_bar
=
'0'));
IF
(rdjbar'
EVENT)
<=
'
AND
; UNTIL
(rd_bar
'0') '1');
AND
(vma
'1'))
THEN
mem_rdy WAIT ON
'
clock
(clock
Tl
end
-B22-
WAIT
ON
clock
<=
'1'
UNTIL
(clock
'
'
T2
end states
mem_rdy END IF
AFTER AND
;
(w_states
=
period); AND
wait
IF;
(wr_bar'
EVENT)
<=
'
(wr_bar
(clock (clock
0')
'1'); ' 1 ) ;
'
(vma
'1'))
THEN Tl T2
mem_rdy
WAIT WAIT ON ON
'
clock clock
<=
'
UNTIL
UNTIL
AFTER
1'
mem_rdy
END END
(w_states
period);
wait
IF;
PROCESS
handshake;
END
BLOCK
cpu_mem_time_unit ;
DATA
BEGIN
BUS
:
data_bus_res
BLOCK
resjunc
PROCESS
(mem_data_out,
: :
cpu_data_out)
VARIABLE
l,r dumbin
qsim_state;
qsim_state_vector
(15
DOWNTO
0)
IN
mem_data_out'
RANGE
LOOP
data_bus (i)
<=
wired_or
(mem_data_out (i)
cpu_data_out
(i) )
LOOP;
resjunc;
PROCESS
BLOCK
data
bus
res;
MEMORY
memory
BLOCK
BEGIN PROCESS
memjnit
(run)
AND
BEGIN
IF
((run'
EVENT)
(run
'1'))
THEN
Interrupt
mem_bankl
vectors
<= <=
<= <= <= <=
(0)
(1)
mem_bank2(0)
mem_bankl
2; 0; 2;
32
"0200"
reset
"0220"
mem_bank2(l)
mem_bankl
external
"0240"
interrupt
(2)
2;
64
mem_bank2(2)
mem_bankl
opcode
error
mem
(3) bank2(3)
memory IN 5 TO
<=
<=
2;
96
address
misalignment
Zero FOR
locations
for
I/O
and
stack
255
LOOP
<= <=
mem_bankl mem_bank2
(i) (i)
0; 0;
END
LOOP;
for
RESET
<= <=
Code
mem_bankl
(256)
mem_bank2(256)
mem_bankl(257)
mem_bank2
mem_bankl
105; 0;
161;
"6900"
STPSW
Rl
"A18F"
AND
Rl, 01111b
Rl
Rl,03h
(257) (258)
(259)
143; 73;
LDPSW
mem_bank2(258)
mem_bankl
0;
145;
"9103"
<= <=
<= <=
mem_bank2(259)
3;
177;
"B100"
Rl, OOh
<= <=
mem
bank2 (261)
0; 121; 0;
"7900"
ALW,R1
Code
mem
for
external
interrupt
"C900'
bankl (272)
<=
201;
PUSH
Rl
-B23-
mem
mem mem mem
mem mem
mem
mem
mem
bank2 (272) "bankl (273) "bank2 (273) bankl (274) "bank2 (274) bankl (275) "bank2 (275) (276) (276) bankl
<=
<=
0;
105;-"6900"
STPSW
Rl
0;
193;-"C187"
OR
Rl, 00111b
Rl
135; 73; 0;
233;-
-"4900"
LDPSW
-"E900"
POP
Rl
(277) (277)
0; 232; 0;
168; 0;
-"E800"
POP
PSW
00"
-"A8
RET
<=
Program
mem_bankl
(384) mem_bank2 (384) mem_bankl (385) mem_bank2 (385) mem_bankl (386) mem_bank2 (386) mem_bankl (387) mem_bank2 (387) mem bankl (388) mem_bank2 (388) mem bankl (389) mem bank2 (389) mem_bankl (390) mem_bank2 (390) mem_bankl (391) mem_bank2 (391) mem_bankl (392) mem_bank2 (392) mem_bankl (393) mem_bank2 (393) mem_bankl (394) mem bank2 (394)
Subroutine
mem_bankl
<=
<= <=
149;-
-"9506"
LDHI
R5,06h
6;
181;-"B520"
LDLOR5,20h LDSP
LDHI
32;
189;-"BD00"
R5
0;
148;-"9400"
R4,00h
0;
180;-
<=
LDLO R4 ADC
FFh
-"0520"
R5,R4,R0
R6,R4,R4
624"
-
-"0
ADC
LDHI
145;-
Rl,03h
3;
177;"B120"
LDLO CALL
HLT
Rl,20h
32;
137;-
Rl
0; 4 0; 0;
146;-
LDHI
"B2B0"
R2,04h
4;
178;-
LDLO
R2,B0h
176;
mem_bankl
(4 02)
6;
131;
ADC
"CE00"
R6,011B
206;-
PUSH
R6 R4 R3
mem_bank2
0;
236;"EC00"
<= <=
<=
POP
mem
0;
219;"DB00"
STSP
0;
59;
6; 26; 6; 18; 130; 50; 131; 98; 152; 67; 24; 19; 136; 168; 0;
"3B06"
STW
LDW
bank2(406)
"1A06"
SHLLR2,0010B
bank2(408)
bankl
(409)
SHRLR2,0011B
bank2(409)
"6298"
mem_bankl(410)
STB
R2, [R3+R0]
,h
mem_bank2(410)
mem_bankl
"4318"
(411)
LDB
R3, [R3+R0]
,1
mem_bank2(411)
<=
<=
"1988"
SHLLR3,1000B
mem_bankl(412) mem_bank2(412)
mem
<= <=
<=
"A800"
bankl
(413)
RET
mem_bank2(413)
END
IF;
-B24-
END
PROCESS memjnit;
:
bankl_access
PROCESS
(oejbar,
: : : :
cs_bar, wrl_bar)
VARIABLE VARIABLE
mem_val
dum_int,j
dum_bin interm dat
integer; integer;
qsim_state_vector (7
qsim
_
DOWNTO
0)
state
_
vector(7
DOWNTO 0)
=
(oejbar'
EVENT)
:= :=
AND
(oejbar
'0')
AND
;
(csjbar
dumjnt
mem_val
'0'))
THEN
qsim_to_int
mem_bankl
:=
(address_bus)
dum_bin(7
FOR i
DOWNTO 0) IN 15 DOWNTO 8
:=
LOOP
<=
j
END
ELSIF
i-8;
'"
mem_data_out
(i)
dum_bin(j)
=
AFTER t
_
o;
LOOP;
(wrl_bar'
interm_dat
mem_val
:=
:=
EVENT)
AND
(cs bar
'0'))
THEN
:=
dumjnt
ELSIF
qsim_to_int
<=
mem_bankl
(mem_val)
EVENT)
15 DOWNTO
(oe_bar'
AND
THEN
FOR i END
ELSE END END
IN
LOOP
<=
' Z'
mem_data_out
(i)
AFTER totd;
LOOP;
NULL; IF;
PROCESS
bankl_access;
:
bank2_access
PROCESS
wr2_bar)
dum_bin
qsim_state_vector
:
(7
DOWNTO
(7
0)
interm_dat
qsim_state_vector
DOWNTO
=
0)
BEGIN
IF
(oejbar'
EVENT)
:= :=
AND
(oe_bar
dum_int
mem_val
qsim_to_int
mem_bank2
DOWNTO
0)
0
:=
'0'))
THEN
IN
DOWNTO
LOOP
<=
mem_dat a_out
(i)
dum_bin(i)
=
AFTER
t_o;
(cs_bar
=
LOOP;
(wr2_bar'
EVENT)
interm_dat
mem val
:=
:=
'0')
; ;
AND
'0'))
THEN
0) )
qsim_to_int qsim_to_int
<=
(addressjbus)
(interm_dat
;
int
ELSIF
:=
mem_bank2
(mem_val)
EVENT)
DOWNTO
dumjnt;
(oe_bar
'Z'
=
(oe_bar'
AND
'1'))
totd;
THEN
IN
LOOP
<=
mem_data_out
(i)
AFTER
LOOP;
END
behave ;
-B25-
APPENDIX
SIMULATION OF
PROGRAM EXECUTION
(1)
Results
of
Program Execution
(buses,
MDR,
MAR,
SP,
PC,
&
PSW,
processor's
state,
instructions,
0 RESET
XXXX
<'
fetch
xxxx
execution
cycles)
-2 -2
XXXX
1'
XXXX
more
xxxx
xxxx
XXXX
error
xxxxx
for
than xxxx
xxxx xxxx
clock
cycles
error error error error
XXXX XXXX
XXXX
XXXX
XXXX XXXX
1 1 1 1 1
1
1 1 1 1 1 1 1 1
xxxx
XXXX XXXX
xxxx xxxx
000
inte rrupt
000 0200 xxxx xxxx is f e tched from memory XXXX 0200 0200 xxxx XXXX xxxx 0200 xxxx xxxx xxxx 0200 xxxx xxxx xxxx 0200 xxxx xxxx 100 0200 xxxx 100 6900 0200 xxxx xxxx 6900 6900 xxxx xxxx xxxx xxxx 6900
routine
1 1 2
2 2 2 3 3
1 1
1 1
1'
starts
executed
xxxx
xxxx
xxxx
xxxx xxxx
xxxx
xxxx xxxx xxxx
A18F
101
101
xxxx
xxxx
xxxx xxxx
xxxx
stpsw
stpsw stpsw
stpsw
exec
3
1
xxxx
xxxx xxxx
fete
stpsw stpsw
stpsw
A18F xxxx
xxxx xxxx
xxxx
xxxx
0202 0202
0202 0202 0202 0204 0204 0204 0204 0204
0204 0204
stpsw
xxxx xxxx
xxxx
andd
andd andd
2 2 2 2 3
1 2 2 2
2 2 2 2 1 2
10000
xxxx
xxxx xxxx
exec exec
xxxx xxxx
andd
andd
3 3 3
1 2
2200 2250
2360 2400
2405
xxxx
xxxx
102 102
xxxx
xxxx
4900 4900
XXXX XXXX xxxx xxxx
0204 0204
xxxx
xxxx
xxxx
2450 2500
0206
0206 0206
the
fete fete xxxx andd fete xxxx andd fete xxxx andd fete xxxx ldpsw fete
andd
2 2 2 3 3 3
1 2 2 2
3 3 3 3 3 3
1 2
xxxx
exec exec
10100 ooooo
2550
clear
0204
xxxx xxxx
xxxx
xxxx xxxx
Interrupt
Flag
4900 4900 4900
0206
0206
0206 0206
0206
2 2 2 2 2 2 1 2 2 2
103 103
xxxx
0206
0206 0206
9103
9103
XXXX
xxxx xxxx xxxx xxxx xxxx B100 B100 xxxx xxxx xxxx
ldpsw
ldpsw ldpsw
2805 2850
2900 2950 3000 3050 3160
xxxx
xxxx xxxx xxxx xxxx
9103 9103
9103 9103 9103 9103 9103 9103
B100 B100
B100
0208
0208
xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx
fete fete
exec exec
0208
0208 0208
fete
104
104
xxxx xxxx
0208 0208
0208
3 3 3 1 2 2 2 2 3 3
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
APSW
eye
2 2 2
2 1
xxxx xxxx
ldlo
0208
AMAR
B100
xxxx
ldlo
VPC
~address_busAMDR
'SP
^instruction
Af_cyc
Aex
Adata
bus
Aproc
state
-Cl-
0208
xxxx xxxx
XXXX xxxx
B100
XXXX
XXXX
XXXX
105 105
XXXX XXXX XXXX XXXX
xxxx
7900 7900
XXXX XXXX
XXXX XXXX xxxx
XXXX
XXXX
7900
7900 7900 7900 7900 7900 7900
XXXX
xxxx xxxx
ldlo exec ldlo fete ldlo fete ldlo fete ldlo fete ldlo fete
3 1 2
2
2 2 2 2
2 2 3 3 3 3 1 2
2
xxxx
xxxx
0300
xxxx
xxxx
xxxx
0300 0300
to
180
180
xxxx
xxxx
code
9506 9506
XXXX XXXX XXXX XXXX XXXX xxxx B520 B520 XXXX
XXXX XXXX
fete
exec exec
exec
2 2 2 1
2
3 3
3 3 3 3
3 1 2
2 2 2 2 2 2 1 2
2 2 3 3 3
1 2 2 2
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo OoCOO ooooo ooooo ooooo ooooo ooooo ooooo ooooo
jump
4100 4150 4200 4250 4300 4410 4450 4455 4500 4550 4600 4650 4700 4810 4850 4855
4900
program'
addre ss
0300
0300 0300
0302 0302 0302 0302 0302 0302 0302 0302
181 181
xxxx
exec
xxxx
xxxx
2 3 3 3 1 2
2
xxxx
XXXX
xxxx xxxx
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx
182 182
XXXX xxxx xxxx
BD00 BD00
XXXX XXXX xxxx xxxx xxxx xxxx xxxx
4950 5000 5050 load 5100 5150 5260 5300 5305 5350
5400
0304 0304
0304 0304
BD00
BD00
xxxx
xxxx xxxx
BD00
BD00 BD00 BD00 BD00
2 2
2 2 2 2 1 2
2 2 3 3 3 3 1 2 2 2
2
exec exec
Pointer
0306 0306
xxxx
183 183
XXXX
9400 9400
XXXX
xxxx xxxx xxxx xxxx xxxx
B4FF
3 3
3 3 3 3 3 3
1 2 2 2
184 184
XXXX XXXX xxxx xxxx
xxxx
3
1 2
B4FF
XXXX
XXXX XXXX XXXX XXXX
0620 0620
0620 6000ns ) 0620 0620 0620 0620 0620 0620 0620
030A
of
xxxx
B4FF
fete fete ldhi fete ldhi fete ldhi fete ldlo fete ldlo exec ldlo exec ldlo fete ldlo fete ldlo fete ldlo fete ldlo fete adc fete
adc adc adc adc
exec
2 2
2
2 2
2
3 3 3 1
2
2
1
2 2 2
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
issuina
external
interrupt xxxx
(at
B4FF B4FF
185 185
xxxx
xxxx xxxx xxxx xxxx xxxx
6060
6100 6105
0520 0520
XXXX XXXX XXXX xxxx xxxx
0520
2 2 2
0520
0520 0520 0520
0520
exec exec
6350
.
030C 030C
i t i on
0620 0620
the
0620
of
xxxx t he
xxxx
0520
(after
inte
of
3 3 3 3 1
the
2 2 2 2
1
3
1
-reind an
int e rrupt
execution
inst ructio
TIME
"PC
"MAR
"address_bus"MDR
'SP
Adata bus
-C2-
6400 6450 6600 6650 6700 6850 6900 7050 7100 7150 7260
7300
030C 030C
0620 0620
0620 061E 061E
XXXX
xxxx
310
XXXX
030C
xxxx xxxx
030C 030C 030C 030C 030C 030C 030C 030C 030C 030C
XXXX
30F
XXXX
0000
xxxx
30F
XXXX XXXX
0000
xxxx
xxxx
1 1
1
1 1
1 1
1
1 1
001 001
XXXX XXXX xxxx
xxxx
xxxx
0002
0220 0220
xxxx xxxx xxxx xxxx
7305 7500 7550 7600 7710 7750 7755 7800 7850 7900
7950
030C
0220
0002 0220 0220 0220 0220 0220 0220 0220 0220 0220 061C 061C 061C 0222 0222 0222 0222
0222 0222 0222 0222 0224 0224 0224 0224
0224
110 110
xxxx xxxx xxxx
xxxx xxxx xxxx
C900 C900
xxxx
xxxx
0000 0000 0000 0000 0220 0220 0220 0220 0220 0220 C900 C900 C900
C900
xxxx
xxxx xxxx
8000 8150 8200 8250 8360 8400 8405 8450 8500 8550 8600 8650
8760
30E
xxxx xxxx
0300
xxxx xxxx xxxx
111
111
xxxx
6900 6900
xxxx xxxx xxxx xxxx
xxxx xxxx
061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C 061C
061A 061A 061A 061A 061A
0 61A
adc adc
adc adc
inte inte inte inte inte inte inte inte inte inte fete fete fete fete fete fete
exec exec exec exec exec
1 1 1
1 1 1 1
1 1
1 1 1 1
1
1
1
1
1 1 1 1 1 1
1
1 2
2
2
2
3 3
3 3 3 3
1
2 3 4 4 4
4
xxxx xxxx
xxxx
xxxx xxxx
2 2 2 2
4 4 4 4 1 2 2 2 2 2 2
10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
10000
3 3 3
1 2
fete
112 112
xxxx xxxx xxxx xxxx
6900 6900
C187 C187 C187
C187 C187 C187
stpsw
stpsw
stpsw
C187 C187
xxxx
0224
0224 0224 0224
xxxx
xxxx xxxx
2 2 2 3 3 3 3 1 2 2 2 2
2
1 2
xxxx xxxx
xxxx
orr
orr orr
xxxx
xxxx xxxx
exec
0226 0226
0226
C187 C187
C187
113 113
xxxx
xxxx xxxx xxxx xxxx xxxx
4900
0226 0226
0226
4900
xxxx
xxxx xxxx xxxx
4900 4900
4900 4900 4900 4900
0228
0228
fete orr fete 0 61A orr fete 0 61A 061A orr fete orr fete 061A 061A ldpsw fete
061A
061A 061A
0226
0226
exec
exec
0228
0228
3 3 3
1
3 3 3 3 3 3 3
1 2
9450 9500
9610 9650 9655 9700 9750
9800 9850 9960
10000 10005
10050
0228
xxxx
xxxx
fete
2 2 2 2 2 2 1 2
10111
0228
0228
0228 0228
0228
114 114
xxxx xxxx xxxx xxxx xxxx
4900
4900
E900
E900
061A
061A
061A
E900 E900
XXXX xxxx
0228
0228
022A
0228 0228 0228 061C 061C 061C 061C 061C 061C 061C "MAR
061A 061A 061C 061C 061C 061C 061C 061C 061C 061C "SP
ldpsw pop
E900
E900 E900 E900 E900
2 2 2 2 3 3 3 3 3
10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111
xxxx xxxx
xxxx
30E 30E
xxxx xxxx xxxx xxxx
0300 0300
xxxx
022A 022A
022A 022A
xxxx xxxx
10100
3
3
exec exec
3 3 3 3
3 4
TIME
"PC
"address_bus"MDR
"instruction
"data
bus
-C3-
022A 022A 022A 022A 022A 022A 022C 022C 022C 022C 022C 022C 022C 022C 022C
061C
022A 022A
XXXX XXXX
XXXX
xxxx
115
xxxx
022A 022A 022A 022A 022A 061E 061E 061E 061E 061E 061E 061E 061E
115
XXXX
E800
E800 XXXX XXXX xxxx
30F
xxxx xxxx
30F
XXXX XXXX XXXX xxxx xxxx
xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx
022C 022C
116 116
XXXX xxxx xxxx xxxx xxxx
xxxx
022E xxxx 11650 022E 0620 xxxx xxxx 11700 030C 0620 return from interrupt 11750 11800 11910 11950 11955 12000 12050 12100 12150
12200 12250
12360
022C 022C 022C 022C 022C 0620 0620 0620 0620 0620 0620 0620
A800 A800
xxxx
061C 061C 061C 061C 061C 061C 061C 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 0620 0620 0620
pop pop Pop pop pop pop pop pop pop Pop pop pop pop pop pop pop pop pop pop pop pop
ret ret
ret
exec
3 1
2
6 6 6 6 6 6 6
1
2
2 2
3 3 3 3 3 3 3 3 3
1
3 3 3 3
4
5
6
10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111 10111
xxxx
xxxx xxxx xxxx
6 6 6
6
2 2
2
2 3
6 6 1 2 3 3 3 3
4
310 310
XXXX xxxx xxxx
ret
ret ret ret ret ret ret ret
exec exec
exec exec exec exec exec exec
030C
030E 030E
030E 030E
030C 030C 030C 030C 030C 030C 030C 030C 030C 030E 030E
030E 030E 030E
xxxx
186 186
XXXX xxxx xxxx xxxx xxxx xxxx xxxx 187
030E
030E
187
XXXX
XXXX
030E 030E
030E
0620 030C 0620 xxxx 030C 0620 xxxx 030C 0620 xxxx 030C 0620 xxxx 030C 0620 xxxx 030C 0620 service rout ine XXXX 030C 0620 xxxx 030C 0620 0624 030C 0620 0624 0624 0620 XXXX 0624 0620 0624 XXXX 0620 0624 XXXX 0620 xxxx 0624 0620 0624 xxxx 0620 0624 0620 xxxx xxxx 0624 0620 0624 0620 9103 0620 9103 9103 0620 XXXX 9103 0620 9103 xxxx
xxxx xxxx xxxx xxxx B120 B120
xxxx XXXX xxxx xxxx xxxx xxxx
030C 030C
3 3 3 3 3 3 3 3 3 3
1 2
5 6 7
7
7 7 7
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
ret
ret ret
ret
ret adc
2 2 2 3 3 3 3 1 2
2
7
7
adc adc
adc
2 3 3 3
fete
2 2
3 3
3 1 2 2 2 2
3 3 3 3
1 2 2 2 2
0310 0310
0310
12650
12760
0310 0310
0310
188 188
xxxx XXXX
XXXX xxxx xxxx xxxx
12800
12805 12850
12900 12950
0310 0310
0310 0310 0310 0312
0310 0312
0312
0312 0312
13000 13050
13160
0312 0312
0312
189 189
XXXX XXXX
0620
0620 0620
13200 13205
13250
8900 8900
XXXX
8900
0312 0314
8900
8900
0620 0620
2
2 2 1 2 2
3 3 3 1 2 2
2
2 2 2
XXXX
XXXX
fete fete
2 2
TIME
"PC
"MAR
~address_bus"MDR
'SP
"instruction
"data bus
-C4-
0314 0314 0314 0314 0320 0320 0320 0320 0320 0320 0322 0322 0322 0322 0322 0322 0322 0322 0324 0324 0324
0324 0324 0324 0324 0324
XXXX
xxxx xxxx
XXXX
310
XXXX XXXX XXXX
0314
XXXX xxxx
0620 0320 0320 0320 0320 0320 0320 0320 0320 0322 0322 0322 0322 0322 0322 0322 0322 0324 0324 0324 0324 0324 0324 0324 0324 0324 0326 0326 0326 0326 0326 0326 0326 0326 061E 061E 061E
0328 0328 0328 0328 0328 0328 0328 061E 061E 061E
061E 061E 061E
xxxx
xxxx
190 190
XXXX XXXX
8900 0314 0314 0314 0314 0314 0314 0314 9204 9204 9204 9204 9204 9204 9204 9204
B2B0 B2B0 B2B0 B2B0 B2B0 B2B0 B2B0
B2B0
9204 9204
XXXX XXXX XXXX XXXX xxxx
191
XXXX xxxx
xxxx
xxxx
xxxx xxxx
0620 0620 0620 0620 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E
061E 061E 061E
call call
call
call call
call
call
call call call
XXXX
xxxx
192 192
XXXX XXXX xxxx
xxxx xxxx
0683 0683
XXXX XXXX XXXX
XXXX
0326 0326 0326 0326 0326 0326 0326 0326 0326 0328 0328 0328 0328 0328 0328 0328 0328 0328 0328 0328
032A 032A 032A
xxxx
xxxx
xxxx xxxx
xxxx
193 193
XXXX xxxx xxxx xxxx xxxx xxxx
CE00 CE00
xxxx xxxx xxxx xxxx xxxx
061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E
061E
ldhi ldhi ldhi ldhi ldhi ldhi ldhi ldhi ldlo ldlo ldlo ldlo ldlo ldlo ldlo ldlo
adc adc
3 3 3 3 1 2 2
2 2
3 3
4 4 4
4 4
4
3 3 3 1 2
2 2 2
4
1 2
2 2 2
2
2 2 1
2 2 2
3 3 1
2 2
2
2
2 2 3 3 3 3
1 2 2
2 2
1 2
adc
adc
exec
exec
3 3 3 3 3 3 3
1
adc
adc adc adc adc
push push
push
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
ooooo
2 2 3
061E 061C
push
push
30F
xxxx xxxx
0201
xxxx xxxx xxxx
0201
0201
194 194
XXXX
xxxx xxxx
EC00 EC00
xxxx xxxx xxxx xxxx
0201
EC00 EC00 EC00
push push
push
3 3 3 3 3
1 2 2
3
4 4 4
4
push push
push
xxxx xxxx
EC00
EC00 EC00 EC00 0201 0201
032A 032A
032A 032A 032A 032A
032A 032A 032A
30F
xxxx
30F
XXXX XXXX XXXX xxxx
xxxx
0201 0201
xxxx xxxx xxxx xxxx xxxx xxxx DB00
0201
0201
061E
061E 032A 032A 032A 032A
16250
16300
16350
xxxx
195
16460
16500
032A 032A
195
XXXX
XXXX
DB00
XXXX xxxx xxxx
16505
16550 16600 16650
032A 032A
xxxx
fete fete fete fete fete stsp fete stsp exec stsp exec
pop pop pop pop pop pop pop pop pop pop pop pop pop pop pop
4 4 4
2 2 3
exec
exec exec exec exec
exec
exec exec
3 3 3 3 3 3 3 3 3 1
2
4 1 2 3 3 3 3
4
5 6 6
6
2 2 2 3
6 6
3 3
6 6 1 2
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
ooooo ooooo
TIME
"PC
"address_bus"MDR
'SP
"data
bus
-C5-
032C 032C 032C 032C 032C 032C 032C 032C 0201 0201 0201
xxxx
XXXX
XXXX
DB00
061E
196 196
xxxx XXXX XXXX XXXX
DB00
DB00
3B06 3B06
XXXX XXXX XXXX XXXX
032E
032E
xxxx
xxxx
061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E
fete
1 2
2 2 2 2 2 2
1
2 2 2
exec exec
stw StW
StW
3 3 3 3 3 3 3 3 1
2
2 3 4
XXXX
XXXX
032E 032E
xxxx xxxx
xxxx
0201
17655 17700 17750 17800 17850 17900 18010 18050 18055 18100 18150 18200
18250 18300 18410 18450 18455 18500
18550
100 xxxx
xxxx 197 197
XXXX xxxx
061E
XXXX
xxxx xxxx
5 6 6
6 6 6 6 6 6
1
061E
061E 061E
061E 061E
061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E
061E 061E 061E
exec
061E 1A06 1A06 1A0 6 1A06 1A0 6 1A0 6 1A0 6 1A0 6 061E 061E 061E 061E
061E 061E
xxxx
xxxx
fete stw fete StW fete stw fete stw fete ldw fete
ldw
exec
2 2
2
3 3 3 3 3
0330 0330 0330 0330 0330 0330 0330 0330 0330 0330 0330
0330 0330 0330 0332 0332 0332 0332 0332 0332
0332
032E 0201 0201 0201 0201 0201 0201 0201 0201 0330 0330 0330 0330 0330 0330 0330 0330 0330
0332
xxxx xxxx
100 100
xxxx xxxx
xxxx
ldw exec ldw exec ldw exec ldw ldw ldw ldw ldw ldw
ldw
exec exec exec
exec
3
4 4 4 4
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
061E
061E
XXXX XXXX
XXXX xxxx xxxx xxxx
exec
exec
3 3 3 3 3
3
1
5 6
7.
198 198
xxxx xxxx xxxx xxxx xxxx xxxx xxxx
1282
061E 061E
1282 1282 1282 1282 1282 1282 1282 1282 1282
1282
XXXX xxxx
xxxx
fete ldw fete ldw fete ldw fete ldw fete shll fete
shll shll shll
shll
2 2
7
7
2 2 3 3 3 3
1
7
7
7 1 2
061E 061E
061E
exec exec
exec
3 3 3 3 3 3 3
1 2
199
199
XXXX xxxx xxxx xxxx
0332 0332
0334 0334
3283 3283
XXXX
XXXX XXXX XXXX XXXX xxxx xxxx
shll
shll
2 2 2 2 3
3283
shll
shll shrl
18905
18950 19000
19050
19100
0334
0334
xxxx
xxxx xxxx
19150
19200 19310
0334 0334
0334 0334 0334
19A 19A
xxxx xxxx xxxx
xxxx
fete fete
exec
exec exec
shrl shrl
shrl
3 3 3 1 2
2
shrl
shrl
6298
shrl shrl
shrl
19350
19355 19400
6298
XXXX
061E
061E
XXXX XXXX
XXXX XXXX xxxx xxxx
2 2 3
3 3 3 3 3 3
1 2
19450
19500 19550
19600 19650
19700
061E
xxxx
xxxx
6298 6298
6298 030F
030F
061E
061E 061E
061E 061E
061E
061E 061E 061E 061E
3 3 3 3 3 3 3
1
3
4
xxxx xxxx
30F
xxxx xxxx
030F
XXXX XXXX xxxx
030F
030F 030F 030F
061E
061E 061E 061E 061E
stb
stb
19B 19B
XXXX
4318 4318
stb stb
0336
"MAR
4318
2 2
5 6 6 6 6 6 6
TIME
"address_bus"MDR
SSP
"data
bus
-C6-
XXXX
XXXX
XXXX xxxx
4318 4318
061E 061E
stb
xxxx xxxx
xxxx
30F 30F
XXXX XXXX xxxx xxxx xxxx xxxx
xxxx
0301
0301
xxxx
xxxx
xxxx xxxx xxxx
xxxx
4318 4318 4318 4318 4318 0301 0301 0301 0301 0301 0301 0301 0301 1388 1388
061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E 061E
061E
fete fete
exec
exec exec
6 6
1 2
exec exec
exec exec
exec
exec exec
19C 19C
xxxx xxxx xxxx
xxxx
1388
1388
xxxx xxxx xxxx xxxx xxxx xxxx xxxx A800 A800
xxxx xxxx xxxx xxxx
3 3 3 3 3 3 3 3 3 3 3
1
3 4
4
4 4
5 6
7
7
21100 21150 21200 21310 21350 21355 21400 21450 21500 21550 21660 21700 21705 21750 21800 21850
21900 21950
22000 22110
033A 033A
033A
xxxx xxxx
xxxx
ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo
2 2
2
7 7 7 7
7
2 3 3 3 3 1 2 2
2 2
2 3 3 3 3 3 3 3 1 2
shll
shll shll
19D
19D
XXXX xxxx xxxx xxxx xxxx
1388
A800
shll
shll ret ret ret ret ret ret
ret ret ret
033A 033C
3 3
033A
310
310
xxxx
xxxx
0314
0314
XXXX
xxxx xxxx
xxxx
xxxx xxxx
0314 0314
0314 0314 0314
0314
0620
0620
exec
exec
0620 0620
0314
xxxx
xxxx xxxx
xxxx
xxxx xxxx xxxx
ret ret
ret
3 3 3 3 3 3 3 3
3 1 2 2 2 2
3 3 3 3
4
5 6
7
exec
011 4
Oil 4
18A 18A
xxxx
ret
ret
2800
0314
7
7 7 7 7 7
0314
2800
xxxx xxxx
xxxx
xxxx
xxxx
xxxx
ret ret
0620 0620
0620 "SP
hit hit
3 3
"f
1
eye
"address
"data
bu s"MDR bus
"instruction
"proc
state
"ex
-C7-
APPENDIX
SIMULATION
OF
PROGRAM EXECUTION
(2)
Results
of
Program Execution
of
(registers
0 850 900 950 1060 1100 1105 1300 1350
1400
-2147
-2147
register
file)
-2147
-2147
-2147
-2147
-2147
-2147
0 0 0 0 0 0
0
0 0
0 0
0 0 0
0 0 0 0 0 0 0 0 0
0
0 0
0 0
0 0 0 0 0 0 0
0 0 0 0
0
0
0 0 0 0
0
0 0 0
0 0
0 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0 0
0
0 0
0 0
0 0 0 0 0 0
'
0 0 0 0 0 0 16
16 16 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0
0 0 0
0 0 0
0
0 0
0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0
0 0 0 0 0 0 0
0
1750
1800 1910
0 0 0
0
0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0
0
1950
1955
16 16 16 16 16 0 0 0 0 0 0 0
0
2000
2050 2100
0 0 0 0 0
0 0 0
0 0
0 0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 0
0
0 0 0 0
0
2400
2405 2450
0 0
0
0 0 0 0 0 0
0
0 0
2500
2550
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
0 0 0 0
0 0 0 0 0 0 0 0
2600 2650
2760
0 0
0
2800
2805 2850
2900 2950
3000 3050 3160 3200 3205
3250
0 0 0
0 0
0 0 0 0 0
0 768 768 768 768 768 768 768 768 768 768
0 0
0 0
0 0 0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0
0 0
0 0 0 0 0 0 0 0
0
0 0
3300 3350
0 0 0
0 0
0
3400 3450
768
0 0
TIME
"registers
(6)
"registers (6)
registers
(3)
"registers (5)
(7)
"
-Dl-
0
0
768 768
768
0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0
0
0
0 0 0 0 0 0 0 0 0
0 0
0
768 768
0 0 0 0 0 0
768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768
768
4055 4100 4150 4200 4250 4300 4410 4450 4455 4500
4550 4600 4650 4700
0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
0
0 0 0
0
0 0 0 0 0 0 0
0 0
0 0 0 0 0
0
0
0
0 0 0 0 0
0 0 0 0 0 0 0
0
0 0 0
0 0
0 0 0 0 0
0 0
4810 4850 4855 4900 4950 5000 5050 5100 5150 5260 5300
5305
768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768
0 0 0
0
0 0 0 0
0 0 0 0
0 0 0
0
0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0
0
0
0
0
0
0 0 0 0 0 0 0
0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
0
0 0 0 0 0 0 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
5705 5750
5800 5850 5900 5950 6060 6100
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0
1536 1536 1536 1536 1536 1536 1536 1536 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 1568 255 255 255 255 255 255
0 0 0 0 0 0 0 0
0
0 0
0 0 0
0 0 0 0
0 0
0 0 0 0 0 0 0
0 0
0 0
0 0
0
0 0 0
0 0 0 0 0 0
0 0 0 0
0 0
0 0 0 0 0
0 0
0 0 0
0 0 0 0 0 0 0 0 0
0 0 0
0 0
0
0 0
0 0 0 0 0 0 0 0 0
6105 6150 6200 6250 6300 6350 6400 6450 6600 6650 6700
0
0
0 0 0 0 0 0 0
0
0
0 0
0 0
0 0 0 0
0
0 0
0
0 0
255
255
TIME
"registers (6) "registers (6) "registers (3) "registers (0) "registers (5) "registers (3) "registers (1)
registers
(7)
"
-D2-
6850 6900 7050 7100 7150 7260 7300 7305 7500 7550 7600 7710 7750 7755 7800 7850 7900 7950 8000 8150 8200 8250 8360 8400 8405 8450
8500 8550 8600 8650
0 0
768
768 768
0 0 0
0 0
0 0 0 0 0 0 0 0 0 0 0
0
768 768 768 768 768 768 768 768 768 768
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0
0
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
255
255 255
0 0
0 0
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 Z55 255 zn 255 255 255 255 255 255 255 255 255 255 255 255
..:>,
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u 0 0 v 0 0 0 0 Q o Q 0 0 0 0
U
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
16 16 16 16
16 16 16
8760
8800
23
23
0 0 0 0
0
23 23 23
0 0 0 0 0 0 0 0 0 0 0 0 u 0 0 0
u
9350
9400 9450
9500
0 0 0 0 0
0
0 "
23 23 23 23 23 23 23 23
23 23
9Zr? 9750
QRnn
!=n
H 23
0 n 0 n 0
n 0 0 0
23
23
0 0 0 0 0 0 0 0 0 0 0 0 n 0 0 0 0 0
0 0
255 255 255 255 255 255 255 255 255 255
Zbb 255
23
23 23
23 23
ill 768
0
n 0 n 0 n 0 n 0
768 768
ill 768
0 0 0 u 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u 0 0
255
2bb 255
0 0
0 Q Q Q 0 0 0
0
768
"registers
(0)
"registers
(3)
"registers
(6)
"registers
(6)
"
"reqisters(l)
"registers
(3)
"registers (5)
registers
(7)
-D3-
0 0 0 0
768 768
0 0
0 0 0 0 0 0
0 0 0
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
11955
12000
12050 12100 12150 12200 12250 12360 12400 12405 12450 12500 12550
12600
768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 '768 7 68 768 768 768 768 768 768 768
768
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0
u 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
255 255 255 255 255 255 255 255 255 255 255 -o 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
0
0 0
HI
255
12650 12760
12800 12805 12850
12900 12950
13000
13050
13160 13200 13205
13250 13300 13350 13400
0 0 0 0 0 0
0 0 0 0
768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 800 800 800 800 800 800 800 800 800 800 800 800
0 0 0 0 0
0
0
0 0
0 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0
0
13550
13600
0 0 0 0 0 0 0 0 0
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
255 255 255 255 255 255 255 w, 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
0 0 0 0 0
0 0
n 0 n 0
HI HI
0
0 0 0 0 0 0 0 0
0
n 0
0
0
0 0 0 0 0 0
0
0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 510
0 0 0 0 0 0 0 0 0 0 0 0
510 510 510 510 510 510 510 510 510 510 510 510 510 510 510
0 0 0 0 0 0 0
0 0
0 0 0 0 0
510 510 510 510 510 510 510 510 510 510 510 510
0 0 0 0
0 0
0 0
TIME
"registers (3) "registers (6) "registers (0) "registers "registers (3) "registers (1) "registers (5)
registers
(6)
"
(7)
-d4-
13650 13700 13810 13850 13855 13900 13950 14000 14050 14100
0 0
0
800 800
0 0
0
0 0 0 0 0
0
0 0 0 0 0 0 0
800 800
0 0 0
0 1024 1024 1024 1024 1024 1024 1024 1024 1200 1200 1200 1200
0 0 0 0 0
0
255 255 255 255 255 255 255 255 255 255
0 0 0
0 0
0 0 0 0 0
0 0 0
0 0 0 0 0 0
0
14400
0 0 0 0
0
0 0
0
800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800
800 800 800 800
0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0
1200
1200 1200 1200 1200 1200 1200
255 255 255 255 255 255 255 255 255 255 255 255
255
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
255 255 255
510 510 510 510 510 510 510 510 510 510 510 510 510 510
510
0 0
0
0 0
0 0 0
0
0 0 0 0 0 0 0 0
0 0 0
1200 1200
1200 1200 1200 1200 1200
15550
15600 15710 15750
800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800
800 800
0 0 0 0
15755
15800
1200 1200
1200
15850
15900 15950 16060
16100
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
0
1200 1200
1200
0 0 0 0 0 0 0 0 0
16105 16150
16200
1200 1200
1200 1200 1200 1200 1200 1200 1200
16250
16300
16350 16460
16500
0
0
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 513 513 513 513
16505
16550
0 0
0 0 0 0 0
1200
1200 1200
1200 1200 1200
16600
16650 16700
16750 16860
1200
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
510 510 510 510 510 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
0 0 0 0 0
0
0 0 0 0
0 0 0 0 0
0
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
0
0 0 0 0
TIME
'registers
(0)
"registers
(3)
"registers
(6)
"registers
(6)
"
"registers
(1)
"registers (3)
"registers (5)
registers
(7)
-D5-
0 0 0 0
0
0 0
0
0 0 0 0
0 0
17700 17750
17800 17850 17900
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
800 800 800 800 800 800 800 800 800 800 800
800 800
1566 1566
800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800
800
1200 1200 1200 1200 1200 1200 1566 1566 1566 1566 1566 1566 1566 1566
1566 6264 6264 6264 6264
6264 6264
1566 1566 1566 1566 1566 1566 1566 1566 1566 1566 1566 1566 1566 1566
1566
513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
513
255
255 255 255 255 255 255 255 255 255 255
1566 1566
1566 1566 1566
18950 19000
19050
0 0 0 0
6264
6264 6264
19100
19150
0 0
0 0 0 0 0 0 0 0 0 0
19200 19310
19350
783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783
1566 1566
1566 1566 1566 1566 1566 1566 1566 1566
1566
19355
19400
19450
19500 19550
19600 19650
800 800
800
800
513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
255
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
513
0 0 0 0 0
0 0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0
0 0
0
0
0
0 0 0
0 0
0
513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
0
19700
19850
0 0
0 0 0 0 0
20105
0 0 0
0
0 0
0
TIME
"registers "registers (6) "registers (3) "registers (0) "registers (3) "registers (5) "registers (1)
registers
(6)
"
(7)
-D6-
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800
21050 21100 21150 21200 21310 21350 21355 21400 21450 21500 21550 21660 21700 21705 21750 21800 21850
21900 21950 22000
22110 22150
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0
783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783 783
783 783
3 3 3 3 3 3 3 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768 768
768
513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
513 513 513 513 513 513 513
255 255 255 255 255 255 255 255 255 255 255 255 255
255
513 513 513 513 513 513 513 513 513 513 513 513 513 513
513 513 513 513 513 513 513 513
513
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22250
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768 768
255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513 513
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(0)
"registers
(3)
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registers
-D7-