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LDPC Decoder Using Pattern-Dependent Modied LLR for the Bit Patterned Media Storage With Written-In Errors
Pornchai Supnithi, Warangrat Wiriya, Watid Phakphisut, and Nattakan Puttarak
Faculty of Engineering, King Mongkuts Institute of Technology Ladkrabang, Bangkok 10520, Thailand
The written-in errors in bit patterned media recording (BPMR) system cause the erroneous bits during the writing process leading to the performance degradation. In this work, we propose the pattern-dependent modied log-likelihood ratio (LLR) usage in low-density parity check (LDPC) decoder to reduce the written-in errors and also improve the write margin. Unlike the existing works, LLR computed based on the input data patterns is used at the LDPC decoder for the cascaded written-in error channel (WEC) with the additive white Gaussian noise (AWGN) channel. The proposed LDPC decoder outperforms the one with conventional LLR in terms of both the . write margin, when the SNR is xed at 5.5 dB, and the performance of LDPC decoder. The SNR gain is about 0.2 dB at the BER of Index TermsBit patterned media recording, log-likelihood ratio, low-density parity-check codes, written-in errors.

I. INTRODUCTION IT PATTERNED media recording (BPMR) is a promising technology to overcome the super-paramagnetic limit and extends the areal density of magnetic recording systems towards 4 Tb/in [1]. The bit patterned media (BPM) is envisioned to further improve the recording density to 10 Tb/in when using with the heat-assisted recording technology [2], [3]. However, this technology still has many challenges that need to be tackled; one is in the writing process known as written-in errors [4]. Due to the head eld gradient, the inherent uctuation such as the media switching eld distribution (SFD) of each individual island, the demagnetization elds from adjacent islands, the random island position jitter, and the write head offset, the errors may occur on the previously written island and the target island. To overcome this problem, recently, some works have proposed the use of the binary and non-binary LDPC codes to correct these errors and improve the write margin in WEC. The results show that LDPC codes can alleviate the written-in errors [4], [5]. In addition, in [6], the improvement of LDPC decoder for the cascaded binary systematic channel (BSC) with AWGN channel or cascaded BSC-AWGN channel has been proposed. The LLR is modied at the LDPC decoder by including the crossover probability of BSC. In practice, the WEC, when modeled as a BSC, does not include the data-dependent nature. Therefore, in this work, we propose to modify the LLR using the written-in error probability at the LDPC decoder based on the input data patterns to reduce the written-in errors and improve the write margin on the cascaded WEC-AWGN channel. The remainder of this paper is organized as follows. We describe the modeling of written-in errors in Section II, and then in Section III, the data patterns that cause the different values are analyzed. Section IV explains the proposed patterndependent LLR modication in the LDPC decoder. The simulation results of the performance improvement of LDPC decoder

using the pattern-dependent modied LLR are shown and discussed in Section V. Finally, in Section VI, the conclusions are given. II. MODELING OF WRITTEN-IN ERRORS The writing process in the BPMR requires that the head eld be large enough to saturate the target island and, simultaneously, does not change the polarity of the previously written island [7]. Due to the head eld gradient, the inherent uctuation such as the media switching eld distribution (SFD) of each individual island, the demagnetization elds from adjacent islands, the random island position jitter, as well as the write head offset [4], [5], two conditions of the written-in errors can occur while attempting to write the bit as shown in Fig. 1. The rst condition is the error on the previously written bit when the polarity of the previous bit is switched to the same direction as the head eld when the write head shifts close to the previous bit (left shift) is shown in Fig. 1(a). Normally, the main pole of the write head is located above the bits and its trailing edge is at the center of the target bit . However, the write head offset and the island position deviation cause the strong effect of head eld gradient to the island . In addition, the other reason that is considered for the probability of occurrence of written-in error on is the magnetization of two neighboring bits . When the polarity of and are opposite to , the demagnetization elds of these bits add up with the head eld gradient. If the head eld gradient, that is disturbed by the demagnetization eld, is more than the media coercivity of , the condition of written-in error on is [4]

(1) where is the applied head eld. is island pitch, is the island position of dened by the island position deviation normalized by . is the head eld and gradient. and are the demagnetization eld of ; herein, the sign of and depends on the polarity of . When and have the opposite polarity, is positive; in contrast, when and have the same pois larity, is negative. is the media coercivity and

Manuscript received March 02, 2012; accepted April 04, 2012. Date of current version October 19, 2012. Corresponding author: P. Supnithi (e-mail: ksupornc@kmitl.ac.th). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TMAG.2012.2194991

0018-9464/$31.00 2012 IEEE

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TABLE I (WRITE HEAD OFFSET, WRITTEN-IN ERROR PATTERNS AND NM) FOR BOTH CONDITIONS OF WRITTEN-IN ERRORS

Fig. 1. Two types of write error conditions: (a) the written-in error in previously written dot and (b) the written-in error in target dot.

Fig. 2. Cascaded WEC-AWGN channel.

the standard deviation of of . Here, the standard deviation of and are normalized by [4], [5]. The second condition is due to the right shift of the head shown in Fig. 1(b); the error on the target bit being written may occur when the write head shifts far from the target bit and the head eld is not large enough to write the target bit. The worst situation that causes a high probability of occurrence of the written-in error takes place when the magnetizations of two neighboring bits are in parallel with the head eld so that the demagnetization eld reduces the head eld. The condition of written-in error of is expressed as

(2) where is the dot position of and are the demagnetization eld of and , and is the deviation of of [4], [5]. Consider a BPM read/write channel as a cascaded WECAWGN channel in Fig. 2, where is the codeword that is transmitted into the channel and is the sampled readback sequence, where and is an AWGN sequence with a zero mean and variance of . Given certain writing conditions, i.e., head eld gradient, demagnetization eld, island uctuation, and head offset values, the output can be generated using the writing condition (1) and (2). III. WRITTEN-IN ERROR PATTERNS AND PROBABILITY OF WRITTEN-IN ERRORS From Section II, the two main causes of written-in errors are the write head offset and the demagnetization eld from adjacent islands. The direction of the write head shift causes the

written-in errors either on the previous bit or the target bit, while the demagnetization eld from adjacent bits causes the various written-in error patterns. For the rst condition with the write head shifted to the left, the probability of written-in error on depends mostly on the polarity of the adjacent bits and , so we consider the pattern as shown in Table I. The value of is increased when and are opposite to . For example, of in the pattern 010 is higher than that in the pattern 001. Out of eight possible patterns 000, 001, 010, 011, 100, 101, 110, and 111, we can divide them into 3 groups, each with different . The left side of the table shows the written-in errors of the rst condition. The polarity of is switched to the same direction as , so only four patterns have . For the second condition with the write head shifted to the right, the bits are considered. In this case, the written-in error may occur on , the bit still keeps the previous polarity after it is written since the head eld is smaller than the media coercivity of the bit. For example, in the pattern 000, we try to write the 0 at ; however, when the written-in error occurs, the 0 cannot be recorded at . Therefore, the bit still keeps the previous polarity that is 1. The value of the each pattern is shown on the right side of the table. The values are divided into 3 groups as well. Here, and the average are obtained from the erroneous recorded bits of each pattern and all patterns, respectively. Note that the write head offset in Table I is 1.3 nm. IV. PATTERN-DEPENDENT LLR MODIFICATION IN LDPC DECODER LDPC codes have recently been applied to the BPMR system with write errors [4], [5]. It has been found that soft iterative decoding of LDPC codes provides a signicant coding gain in conventional magnetic recording system [8]. However, when applying LDPC codes to BPMR system that has the probability of written-in error, this code is unable to keep a good performance due to the high probability of the erroneous bits. We take into account the data-dependent nature of the probability of written-in error as follows. Firstly, the received sequence is converted into bits using the hard decision. Secondly, each three-bit pattern is considered whereby the probability of the middle bit is from Table I (given the spec-

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ied writing parameters), depending on the left or right shift conditions. If only the range of shifts is known, for instance, nm, then for each pattern, of the middle bit can be obtained from the averaged of both sides. Finally, the probability density function (pdf) of is modied by weighing with , depending on the hard decision. Therefore, we have

(3) can be similarly obtained. The logThe term likelihood ratio (LLR) is dened as (4) Using Bayes rule, we obtain
Fig. 3. Written-in error probability of each pattern.

(5) The pattern-dependent modied LLR density is used for LDPC decoding. Note that the conventional LLR is calculated by setting . V. SIMULATION RESULTS AND DISCUSSIONS In this work, we start to explain the written-in error probability for each pattern that is simulated from (1) and (2) in Section II. For this simulation, we assume that the island arrangement is a 1 row per track (1RPT) array and the areal recording density is 2 Tbits/in with the bit density of 2000 kBPI and the track density of 1100 kBPI. The island diameter, the island pitch, and the track pitch are xed to 8, 13, and 23 nm, respectively. We also assume that magnetic eld at the target track is not oscillated by the magnetization on the neighboring tracks because the read head has the side shield, and the cross-track width of read head is equal to the track pitch [4], [5]. Secondly, the performance of LDPC decoder using the pattern-dependent modied LLR are presented. In this part, the simulation system consists of high-rate LDPC codes and the cascaded WEC-AWGN channel. This LDPC code is constructed using the progressive-edge-growth (PEG) algorithm [9]. The Tanner graph has the column weight of 3, while the row weight varies from 2629. The codeword block size is 4608 and the code rate is 8/9. For the LDPC decoder, we use the belief propagation (BP) algorithm. A. Written-In Error Probability of Each Pattern Fig. 3 shows the written-in error probability of each pattern. The vertical axis shows and the horizontal axis shows the write head offset between the transition timing of the write current at the trailing edge of write head and the center position of the writing target bit. In this simulation, the parameters are set as kOe, kOe,

Oe/nm, [1]. The left-hand side of the graph shows of the rst condition while the right-hand side shows of the second condition. The legends show the patterns before the written-in errors occur. If we focus our attention on nm, of each data pattern is the same as is shown in Table I and is at the minimum at nm. B. Performance Improvement of LDPC Decoder Using the Pattern-Dependent Modied LLR The performance of LDPC decoder with the pattern-dependent modied LLR for the write-error channels is investigated. For this simulation, the user data sequences are encoded and decoded with LDPC codes. The signal-to-noise ratio (SNR) can be expressed in terms of , where is the bit energy, is a one-sided power spectral density of AWGN, is the variance of AWGN, and is the code rate. For each SNR, the simulation is run until about 1000 erroneous bits are obtained. Also, for all the curves, the number of decoding iterations is 20. Fig. 4 shows the performance of LDPC decoder with the conventional LLR LLR , the modied LLR with the average and the pattern-dependent modied LLR of three types. Type 1 and 2 represent the systems with the left and right shift of the read head only. Type 3 represents the situation when the range of shifts is known. Therefore, of each pattern is obtained from the left sides or the right sides in Table I only. Although in practice, a BPMR system will not experience only one direction of the offset, these two cases are used to illustrate the improvement using the proposed pattern-dependent modied LLRs. The results show that the proposed methods give the SNR gains of about 0.1 dB and 0.6 dB, respectively. The conventional LLR approach obviously performs the worst. Next, we consider a system with the head offset nm, denoted as , so on the read side, the conventional LLR, the average , and the pattern-dependent methods are compared. For the average , we use .

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set as in the simulation in part A, except that the SNR is xed at 5.5 dB. The results show that LDPC decoder using the modied LLR with the average and the pattern-dependent modied LLR can keep error-free over nm and nm, respectively. VI. CONCLUSION In this work, we have proposed the performance improvement of LDPC codes using the pattern-dependent modied LLR in the cascaded WEC-AWGN channel. The results show that the proposed method yields the nest performance when compared with the conventional LLR and the modied LLR with the average . In addition, when we evaluate the performance of the proposed method in terms of the write margin, the results show that the write margin of pattern-dependent modied LLR is the widest. ACKNOWLEDGMENT This work was supported by the Thailand Research Fund through the Royal Golden Jubilee Ph.D. Program (Grant No. PHD/0002/2554). The authors would like to thank Prof. Y. Okamoto and Prof. Y. Nakamura for the introduction of the written-in error issue. REFERENCES
[1] H. J. Richter et al., Recording on bit-patterned media at densities of 1 Tb/in and beyond, IEEE Trans. Magn., vol. 42, no. 10, pp. 22552260, Oct. 2006. [2] B. Xu, J. Yang, H. Yuan, J. Zhang, Q. Zhang, and T. C. Chong, Thermal effects in heat assisted bit patterned media recording, IEEE Trans. Magn., vol. 45, no. 5, pp. 22922295, May 2009. [3] H. Muraoka and S. J. Greaves, Statistical modeling of write error rates in bit patterned media for 10 Tb/in recording, IEEE Trans. Magn., vol. 47, no. 1, pp. 2634, Jan. 2011. [4] Y. Nakamura et al., A study of LDPC coding and iterative decoding system in magnetic recording system using bit-paterned medium with write error, IEEE Trans. Magn., vol. 45, no. 10, pp. 37533756, Oct. 2009. [5] Y. Nakamura et al., A study on non-binary LDPC coding and iterative decoding system in BPM R/W channel, IEEE Trans. Magn., vol. 47, no. 10, pp. 35663569, Oct. 2011. [6] A. R. Iyengar, P. H. Siegel, and J. K. Wolf, LDPC codes for the cascaded BSC-BAWGN channel, in Proc. 47th Annu. Allerton Conf. Communication, Control and Computing, Sep. 2009, pp. 620627. [7] H. Muraoka, S. J. Greaves, and Y. Kanai, Modeling and simulation of the writing process on bit-patterned perpendicular media, IEEE Trans. Magn., vol. 44, no. 11, pp. 34233429, Nov. 2008. [8] E. M. Kurtas, A. V. Kuznetsov, and I. Djurdjevic, System perspective for the application of structured LDPC codes to data storage devices, IEEE Trans. Magn., vol. 42, no. 2, pp. 200207, Feb. 2006. [9] X. Y. Hu et al., Regular and irregular progressive edge-growth tanner graph, IEEE Trans. Inf. Theory, vol. 51, no. 1, pp. 386398, Jan. 2005.

Fig. 4. Performance comparison of the LDPC decoder with the conventional , and the pattern-dependent modiLLR, the modied LLR with average ed LLR.

Fig. 5. Comparison of the write margins in the LDPC decoders with the con, and the pattern-depenventional LLR, the modied LLR with average dent modied LLR.

For the pattern-dependent method, of each bit is an average of both the left and right shift scenarios from Table I. It is evident that the pattern-dependent method offers a gain of about 0.2 dB at BER . To further explore the effect of the patterned-dependent modied LLR for LDPC decoding, in Fig. 5, we evaluate the performance of the pattern-dependent modied LLR in terms of the write margin. The parameters are