o Curriculum Vitae Samuel Freitas Anta

Personal Information

Samuel Freitas Ant ao INESC-ID, Room 201 Rua Alves Redol, 9 1000-029 Lisbon Portugal tel: +351 964 932 941 fax: +351 213 145 843 sfan@sips.inesc-id.pt sips.inesc-id.pt/~ sfan http://pt.linkedin.com/in/samuelfantao

29th October, 2012 I was born in Lisbon, Portugal, in 1985. I graduated from Electrical and Computer Engineering from the Instituto Superior T ecnico (IST) of the Technical University of Lisbon, and obtained my MSc degree from the same University. My MSc research project was conducted under the supervision of professor Leonel Sousa resulting in the thesis entitled Portable Embedded Systems: Ecient Units for Data Processing and Cryptography. I am now working towards my PhD as a researcher at the Signal Processing Group (SiPS) integrated at INESC-ID, in the elds of cryptography, embedded systems and digital electronic design. My research interests include computer arithmetic, residue number systems, computer arithmetic and computer architecture.
Education

PhD student in Electrical and Computer Engineering (2008-present). Department of Electrical and Computer Engineering, Instituto Superior T ecnico, Technical University of Lisbon in collaboration with Laboratoire dInformatique de Paris 6, Universit e Pierre et Marie Curie. Thesis subject: Embedded Systems, Elliptic Curve Cryptography, Digital Electronic Design, Parallel Processing, Highly Parallel Platforms and Arithmetic/Algorithms. Thesis advisor: Prof. Leonel Sousa. Expected completion by December, 2012. MSc degree in Electrical and Computer Engineering (2006-2008). Department of Electrical and Computer Engineering, Instituto Superior T ecnico, Technical University of Lisbon. Thesis title: Portable Embedded Systems: Ecient Units for Data Processing and Cryptography. Thesis advisor: Prof. Leonel Sousa. Final Grade: 18 of 20. BSc degree in Electrical and Computer Engineering (2003-2007). Department of Electrical and Computer Engineering, Instituto Superior T ecnico, Technical University of Lisbon. Final Grade: 17 of 20.

Professional Experience

2007 present Researcher at Signal Processing Systems Group - INESC-ID, developing research on several subjects including: cryptography, residue number systems, computer arithmetic, parallelization of algorithms, com-

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puter architectures, embedded systems, FPGA design, ASIC design, GPU programming, and image processing. 2012 present System administrator at Quality, Test and Co-Design of HW/SW Systems Group - INESC-ID; 2008 present Singer (tenor) at the Calouste Gulbenkian Foundation Professional Choir; 2002 present Management and technical assistant at Casal Freitas winery. Fernando-P o, Palmela, Portugal; 2007 2008 High School Student Tutoring, supporting the preparation of high school students in the eld of physics for admission in graduation programs. Summer 2005 Research Intern at Signal Processing Systems Group - INESCID.
Publications Book chapters

Ant ao, S., & Sousa, L. (2012). Recongurable Architecture for Cryptography over Binary Finite Fields. Embedded systems: Hardware Design and Implementations, John Wiley & Sons (to appear).

Refereed Scientific Journals

Ant ao S., & Sousa, L. (2012). The CRNS Framework and its Application to Programmable and Recongurable Cryptography. ACM Transactions on Architecture and Code Optimization (to appear). ACM. Sousa, L., Ant ao, S., & Germano, J. (2012). A lab project on the design and implementation of programmable and congurable embedded systems. IEEE Transactions on Education (to appear). IEEE. Sousa, L., Ant ao S., & Chaves R. (2012). On the design of RNS reverse converters for the four-moduli set {2n + 1, 2n 1, 2n , 2n+1 + 1}. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (to appear). IEEE. Sousa, L., & Ant ao, S. (2012). MRC-based RNS reverse converters for the fourmoduli sets {2n + 1, 2n 1, 2n , 22n+1 1} and {2n + 1, 2n 1, 22n , 22n+1 1}. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(4), 244 -248. IEEE. Ant ao, S., Bajard, J.-C., & Sousa, L. (2011). RNS based Elliptic Curve Point Multiplication for Massive Parallel Architectures. The Computer Journal 2011 - Oxford Journals, 55(5), 624-647. Oxford University Press.

Refereed Conference Proceedings

Sousa, L., & Ant ao, S. (2012). VLSI Reverse Converter for RNS based on the Moduli Set {2n + 1, 2n 1, 22n+1 3, 22n 2}. Euromicro Symposium on Digital System Design - DSD (to appear). C e sme - Izmir: IEEE;

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Ant ao, S., & Sousa, L. (2010). Exploiting SIMD extensions for linear image processing with OpenCL. IEEE International Conference on Computer Design - ICCD (pp. 425-430). Amsterdam: IEEE; Ant ao, S., Bajard, J.-C., & Sousa, L. (2010). Elliptic Curve point multiplication on GPUs. IEEE International Conference on Application-specic Systems Architectures and Processors - ASAP (pp. 192-199). Rennes: IEEE; Ant ao, S., Chaves, R., & Sousa, L. (2009). Compact and Flexible Microcoded Elliptic Curve Processor for Recongurable Devices. IEEE Symposium on Field Programmable Custom Computing Machines - FCCM (pp. 193-200). Napa CA: IEEE; Tulabandhula, T., Ant ao, S., & Sousa, L. (2009). A Class of Software-Hardware Processors for Fingerprint Matching on the Fourier Domain. 3rd HiPEAC Workshop on Recongurable Computing. Paphos: HiPEAC; Ant ao, S., Chaves, R., & Sousa, L. (2008). Ecient FPGA Elliptic Curve Cryptographic Processor over GF (2m ). International Conference on FieldProgrammable Technology - ICFPT (pp. 357-360). Taipei: IEEE.

Invited Publications

Ant ao, S., Chaves, R., & Sousa, L. (2009). AES and ECC Cryptography Processor with Runtime Conguration. International Conference on Advanced Computing and Comunications - ADCOM. Bangalore: IEEE.

Thesis

Ant ao, S. (2008). Portable Embedded Systems: Ecient Units for Data Processing and Cryptography. Instituto Superior T ecnico - TU-Lisbon.

Other Publications

Ant ao, S., Chaves, R., & Sousa, L. (2009). Ecient Elliptic Curve Cryptography with Collapsed Representation. Advanced Computer Architecture and compilation for Embedded Systems (pp. 125-128). Terrassa: High Performance Embedded Architecture and Compilation (HiPEAC) Network of Excelence.
Tutorials for Education

Optimizing code for given architectures with the SIMD instructions. Tutorial for the practical classes of the course of Advanced Computer Architectures of the MSc degree in Electrical and Computer Engineering at Instituto Superior T ecnico - Technical University of Lisbon, 2012. Accelerating Image Processing Algorithms with Microblaze Softcore and Digilent S3 FPGA Demonstration Board. Tutorial for the practical classes of the course of Computer Electronics of the MSc degree in Electrical and Computer Engineering at Instituto Superior T ecnico - Technical University of Lisbon, 2011.

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Microblaze Softcore and Digilent S3 FPGA Demonstration Board. Tutorial for the practical classes of the course of Computer Electronics of the MSc degree in Electrical and Computer Engineering at Instituto Superior T ecnico - Technical University of Lisbon, 2011.
Referee Experience Scientific Journals

TCAS-I: IEEE Transactions on Circuits and Systems I, IEEE; TVLSI: IEEE Transactions on Very Large Scale Integration Systems, IEEE; TECS: ACM Transactions on Embedded Computing Systems, ACM; IET-CDT: IET Computers & Digital Techniques, IET; IET-CDS: IET Circuits, Devices & Systems, IET; MICPRO: Microprocessors and Microsystems, Elsevier; Integration, the VLSI Journal, Elsevier.

Conference Proceedings

MSEPT: International Conference on Multicore Software Engineering, Performance, and Tools - 2012; ARITH: IEEE Symposium on Computer Arithmetic - 2011; CF: ACM International Conference on Computing Frontiers - 2011; PDPS: International Conference on Parallel and Distributed Computing and Systems - 2011; ARCS: Architecture of Computing Systems - 2010, 2012; DSD: Euromicro Conference on Digital System Design - 2010, 2011, 2012; ICCD: IEEE International Conference on Computer Design - 2010, 2011; IPDPS: IEEE International Parallel & Distributed Processing Symposium 2010, 2012; ISCA: ACM/IEEE International Symposium on Computer Architecture - 2010; ISPDC: International Symposium on Parallel and Distributed Computing 2010; RAW: Recongurable Architectures Workshop - 2010; SDR/WInnComm: Software Dened Radio Forum / Wireless Innovation Forum - 2010; VLSI-SoC: IFIP/IEEE International Conference on Very Large Scale Integration - 2010; EUSIPCO: European Signal Processing Conference - 2009; SAMOS: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation - 2009, 2010, 2011; SiPS: IEEE Workshop on Signal Processing Systems - 2009;

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PDCAT: International Conference on Parallel and Distributed Computing, Applications and Technologies - 2008; ReCong: International Conference on ReConFigurable Computing and FPGAs - 2008.
Projects and Scholarships

2008 2012 PhD Student Scholarship by the Portuguese Foundation for Science and Technology (FCT) for the realization of the PhD thesis at Instituto Superior T ecnico - TU Lisbon. 2009 2010 Systems for Cryptography based on Modular Arithmetic (SCryBAM) project in the scope of the PHC PESSOA program between Portugal and France. This project aimed the development of collaborative work with the teams ARITH at the Laboratoire dinformatique de Robotique et de Micro electronique de Montpelier (LIRMM) and Performance and Quality of Numerical Algorithms (PeQuAN) at Laboratoire dInformatique de Paris 6 - Universit e Pierre et Marie Curie. The project allowed close collaboration with Prof. Jean-Claude Bajard, Prof. Laurent-St ephane Dider and Prof. Thibault Hilaire in the eld of modular arithmetic and residue number systems. 2007 2008 Scholarship for Introduction to the Scientic Research by the Portuguese Foundation for Science and Technology (FCT) for the development of prototypes to accelerate elliptic curve cryptography at INESC-ID.

Honors and Awards

HiPEAC Paper Award for the paper entitled Compact and Flexible Microcoded Elliptic Curve Processor for Recongurable Devices, by Samuel Ant ao, Ricardo Chaves and Leonel Sousa, presented at the IEEE Symposium on Field Programmable Custom Computing Machines - FCCM, March 2009. Awarded by: European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC); Prize Professor Lu s Vidigal 2007/2008, for the best quality and innovative MSc Thesis in the eld of Electrical and Computer Engineering, and Computer Science between any of the courses lectured at Instituto Superior T ecnico - TULisbon. Awarded by: Electrical and Computer Engineering Department - Instituto Superior T ecnico - TU-Lisbon, INESC-ID; Merit Diploma for the 3rd best scholar performance for the 1st year of the MSc degree in Electrical and Computer Engineering. Awarded by: Electrical and Computer Engineering Department - Instituto Superior T ecnico - TU-Lisbon; Best Project of Mobile Computing 2006/2007 (Spring semester) Award, with the work entitled: Intrusion Detection based on a Sensor Network. Awarded by: Electrical and Computer Engineering Department - Instituto Superior T ecnico - TU-Lisbon, UbiSec&Sens, INOV.

Talks

Elliptic Curve Point Multiplication on GPUs, Laboratoire dInformatique de Paris 6 - Universit e Pierre et Marie Curie, July, 2010, Paris, France.

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Training Initiatives

Attendee at the 5th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, Terrassa, Spain, July, 2009. Organized by: European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).

Tool skills Operating Systems

Windows; Linux (OpenSuse, Ubuntu, CentOS) and other Unix based systems, including Mac OS X; TinyOS 2.0 (applied to sensor network motes).

Programming, Hardware Description and Scripting languages

C, C++: development of programs for verication, compilers, simulators, embedded processors programming (e.g. Xilinx MicroBlaze, Microchip PIC Microcontrollers, Atmel Microcontrollers); NesC: development of programs to control the motes in sensor network; Assembly: optimization of programs for several platforms, including x86 CPUs and several embedded processors (e.g. Xilinx MicroBlaze, Microchip PIC Microcontrollers); Intel SIMD intrinsics: optimization of programs exploiting the CPU SIMD capabilities; VHDL, Verilog: description of FPGA and ASIC accelerators for several applications, including general purpose processing and cryptography; bash, DOS batch, Perl: automation of design procedures, setup and administration of an Apache Subversion server; MATLAB: simulation and results analysis using dierent toolboxes (e.g. Simulink, Statistics toolbox); CUDA: GPU general purpose programming for NVIDIA GPUs, parallelization of algorithms; OpenCL: parallel programming targeting NVIDIA and ATI GPUs, AMD and Intel CPUs, employing the OpenCL implementation by NVIDIA, Apple, and AMD (AMD Accelerated Parallel Processing).

Hardware Development and Verification

Modelsim (Mentor Graphics, Inc.): verication and evaluation of digital hardware implementations; Synplify (Synopsys Inc.): synthesis for FPGA platforms; Design Vision (Synopsys Inc.): synthesis for ASIC standard cell based implementations;

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RTL Compiler (Cadence Design Systems, Inc.): synthesis for ASIC standard cell based implementations; Encounter (Cadence Design Systems, Inc.): digital ASIC design, cell placement and routing; Xilinx FPGA design tools: synthesis, place and routing, evaluation (ISE tools), MicroBlaze and Power PC embedded processors integration (Xilinx Platform Studio); Altera FPGA design tools: synthesis, place and routing, evaluation (QuartusII tools), IP cores development and management (Qsys, SOPC Builder).

Other Software Tools and Libraries

Microsoft Visual Studio .NET: managing and development of software projects; GNU Multiple Precision Arithmetic Library (GMP): software implementation of arithmetic for big integers in the development of compilers and verication programs; Crypto++: software implementation of protocols based requiring cryptographic routines and verication programs; Multiprecision Integer and Rational Arithmetic C/C++ Library (MIRACL): implementation of nite eld arithmetic, both for prime and binary extension elds; Flex, The Fast Lexical Analyzer: implementation of the scanner procedures for compilers; Bison, GNU parser generator: implementation of the parser procedures for compilers; LLVM Compiler Infrastructure : implementation of an high-level synthesis and parallel programming framework; Latex2 : writing and production of documents; Apache2: setup and management of Linux based Web and Subversion servers.
Other activities

2006 present Member at the early music ensemble Camerata da Cotovia as tenor voice, and Baroque and Renaissance ute (traverso) player; 2007 Participant in the movie Esbo co para um Filme (Sketch for a Movie) directed by Pedro Sabino: dubbing on an original movie recorded in the Portuguese Colonial War years; 1998 2005 Flute, Musical Sight-Reading, and Ensemble Music Course. Adriana de Vecchi Music School, Music School of the National Conservatory of Lisbon, Portugal;

Language skills

Portuguese: Native; English: Fluent; French: Basic; Spanish: Conversational.

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