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KL25P80M48SF0
Supports the following: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4, MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4, MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4
Features Operating Characteristics Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V Temperature range (ambient): -40 to 105C Performance Up to 48 MHz ARM Cortex-M0+ core Memories and memory interfaces Up to 128 KB program flash memory Up to 16 KB RAM Clocks 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator Multi-purpose clock source System peripherals Nine low-power modes to provide power optimization based on application requirements 4-channel DMA controller, supporting up to 63 request sources COP Software watchdog Low-leakage wakeup unit SWD interface and Micro Trace buffer Bit Manipulation Engine (BME) Security and integrity modules 80-bit unique identification (ID) number per chip Human-machine interface Low-power hardware touch sensor interface (TSI) General-purpose input/output Analog modules 16-bit SAR ADC 12-bit DAC Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers Six channel Timer/PWM (TPM) Two 2-channel Timer/PWM (TPM) Periodic interrupt timers 16-bit low-power timer (LPTMR) Real-time clock Communication interfaces USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator Two 8-bit SPI modules Two I2C modules One low power UART module Two UART modules
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2012 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 2 Part identification......................................................................3 2.1 Description.........................................................................3 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 2.4 Example............................................................................4 3 Terminology and guidelines......................................................4 3.1 Definition: Operating requirement......................................4 3.2 Definition: Operating behavior...........................................4 3.3 Definition: Attribute............................................................5 3.4 Definition: Rating...............................................................5 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 3.7 Guidelines for ratings and operating requirements............7 3.8 Definition: Typical value.....................................................7 3.9 Typical Value Conditions...................................................8 4 Ratings......................................................................................8 4.1 Thermal handling ratings...................................................8 4.2 Moisture handling ratings..................................................9 4.3 ESD handling ratings.........................................................9 4.4 Voltage and current operating ratings...............................9 5 General.....................................................................................9 5.1 AC electrical characteristics..............................................10 5.2 Nonswitching electrical specifications...............................10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and current operating requirements.........10 LVD and POR operating requirements.................11 Voltage and current operating behaviors..............12 Power mode transition operating behaviors..........13 Power consumption operating behaviors..............13 EMC radiated emissions operating behaviors.......20 Designing with radiated emissions in mind...........21 Capacitance attributes..........................................21 5.3.1 5.3.2 Device clock specifications...................................21 General Switching Specifications..........................22 5.4 Thermal specifications.......................................................22 5.4.1 5.4.2 Thermal operating requirements...........................22 Thermal attributes.................................................22
6 Peripheral operating requirements and behaviors....................23 6.1 Core modules....................................................................23 6.1.1 SWD Electricals ...................................................23
6.2 System modules................................................................25 6.3 Clock modules...................................................................25 6.3.1 6.3.2 MCG specifications...............................................25 Oscillator electrical specifications.........................27
6.5 Security and integrity modules..........................................30 6.6 Analog...............................................................................31 6.6.1 6.6.2 6.6.3 ADC electrical specifications.................................31 CMP and 6-bit DAC electrical specifications.........35 12-bit DAC electrical characteristics.....................36
6.7 Timers................................................................................39 6.8 Communication interfaces.................................................39 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 USB electrical specifications.................................39 USB VREG electrical specifications......................39 SPI switching specifications..................................40 I2C.........................................................................44 UART....................................................................44
7 Dimensions...............................................................................45 7.1 Obtaining package dimensions.........................................45 8 Pinout........................................................................................45 8.1 KL25 Signal Multiplexing and Pin Assignments................45 8.2 KL25 Pinouts.....................................................................48 9 Revision History........................................................................52
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PKL25 and MKL25
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q KL## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field Q KL## A FFF Qualification status Kinetis family Key attribute Program flash memory size Description Values M = Fully qualified, general market flow P = Prequalification KL25 Z = Cortex-M0+ 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB
Terminology and guidelines Field R T PP Silicon revision Temperature range (C) Package identifier Description Values (Blank) = Main A = Revision after main V = 40 to 105 FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm)
CC N
2.4 Example
This is an example part number: MKL25Z64VLK4
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed:
Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements:
Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. A Unit
3.3.1 Example
This is an example of an attribute:
Symbol CIN_D Description Input capacitance: digital pins Min. 7 Max. pF Unit
3.4.1 Example
This is an example of an operating rating:
Symbol VDD Description 1.0 V core supply voltage 0.3 Min. 1.2 Max. V Unit
20
The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
10
ra pe
ra pe
ra pe
ra pe
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
n Ha
dli
ng
ng ati
(m
(m
Ha
nd
Fatal range
Expected permanent failure
Handling range
No permanent failure
Fatal range
Expected permanent failure
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. A Unit
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions:
Ratings
5000 4500 4000 3500 IDD_STOP (A) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 C 105 C 25 C 40 C
4 Ratings
4.1 Thermal handling ratings
Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Min. 55 Max. 150 260 Unit C C Notes 1 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
General
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc. 9
General
All digital I/O switching characteristics, unless otherwise specified, assumes: 1. output pins have CL=30pF loads, are slew rate disabled, and are normal drive strength
VDD VDDA VDD-to-VDDA differential voltage VSS VSSA VSS-to-VSSA differential voltage VIH Input high voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V VIL Input low voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V
V V
General
-25 1.2
+25
mA
1. All digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
General
General
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. Measured at VDD supply voltage = VDD min and Vinput = VDD
General
IDD_RUNCO_ Run mode current in compute operation - 48 MHz core / 24 MHz flash/ bus disabled, LPTMR CM running using 4MHz internal reference clock, CoreMark benchmark code executing from flash at 3.0 V IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 V at 25 C at 125 C IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V
6.4 6.8
7.8 8.3
mA mA 3
3.7
5.0
mA
IDD_WAIT
3 2.9 4.2 mA
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus at 3.0 V IDD_VLPRCO Very low power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 V IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 V
3 2.5 3.7 mA
5 188 570 A
5 224 613 A
General
IDD_VLPW
135
496
IDD_STOP
General
IIREFSTEN32KHz
52
52
52
52
52
52
IEREFSTEN4MHz
206
228
237
245
251
258
uA
General
IRTC
432
357
388
475
532
810
nA
IUART
General
5.2.5.1
The following data was measured under these conditions: MCG in FBE for run mode, and BLPE for VLPR mode USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
7.00E-03
6.00E-03
5.00E-03
4.00E-03
All Off
All On
3.00E-03
2.00E-03
1.00E-03
General
400.00E-06
350.00E-06
300.00E-06
250.00E-06
150.00E-06
100.00E-06
50.00E-06
000.00E+00
'1-1 '1-2 '1-2 '1-4
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range.
General 2. VDD = 3.3 V, TA = 25 C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method
General Symbol
K
Description
Min.
Max. 16 16 8 8
Notes
fLPTMR_ERCL LPTMR external reference clock fosc_hi_2 fTPM fUART0 Oscillator crystal or resonator frequency high frequency mode (high range) (MCG_C2[RANGE]=1x) TPM asynchronous clock UART0 asynchronous clock
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module.
Four-layer (2s2p)
RJA
53
52
28
33
C/W
Single-layer (1S)
RJMA
59
69
75
C/W
Four-layer (2s2p)
RJMA
46
22
27
C/W
RJB RJC JT
34 15 0.6
34 20 5
10 2.0 5.0
12 1.8 8
2 3 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental ConditionsForced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air).
J2 J3 J3
SWD_CLK (input)
J4
J4
SWD_CLK
J9 J10
SWD_DIO
J11
SWD_DIO
J12
SWD_DIO
J11
SWD_DIO
fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature using SCTRIM and SCFTRIM fdco_t fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0 - 70 C Internal reference frequency (fast clock) factory trimmed at nominal VDD and 25 C Frequency deviation of internal reference clock (fast clock) over temperature and voltage --factory trimmed at nominal VDD and 25 C Internal reference frequency (fast clock) user trimmed at nominal VDD and 25 C Loss of external clock minimum frequency RANGE = 00 Loss of external clock minimum frequency RANGE = 01, 10, or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 640 ffll_ref Mid range (DRS = 01) 1280 ffll_ref
+0.5/-0.7 0.4
3 1.5
%fdco %fdco
1, 2 1, 2
fintf_ft fintf_ft
4 +1/-2
MHz %fintf_ft 2
20.97 41.94
39.0625 25 48
Ipll
2.0
600
4.0
A MHz
fpll_ref Jcyc_pll
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
IDDOSC
Supply current high gain mode (HGO=1) 32 kHz 4 MHz 8 MHz (RANGE=01) 16 MHz 24 MHz 32 MHz
Cx Cy RF
EXTAL load capacitance XTAL load capacitance Feedback resistor low-frequency, low-power mode (HGO=0) Feedback resistor low-frequency, high-gain mode (HGO=1) Feedback resistor high-frequency, low-power mode (HGO=0) Feedback resistor high-frequency, high-gain mode (HGO=1)
VDD
0.6
VDD
1. VDD=3.3 V, Temperature =25 C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used.. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.
6.3.2.2
Symbol fosc_lo fosc_hi_1
fosc_hi_2
32
MHz
fec_extal tdc_extal
40
50
48 60
MHz %
1, 2
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.
The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.
Table 15. NVM program/erase timing specifications
Symbol thvpgm4 thversscr thversall Description Longword Program high-voltage time Sector Erase high-voltage time Erase All high-voltage time Min. Typ. 7.5 13 52 Max. 18 113 452 Unit s ms ms 1 1 Notes
6.4.1.2
Symbol trd1sec1k tpgmchk trdrsrc tpgm4 tersscr trd1all trdonce tpgmonce tersall tvfykey
1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3
Symbol IDD_PGM IDD_ERS
6.4.1.4
Symbol
Reliability specifications
Description
tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k nnvmcycp Data retention after up to 1 K cycles Cycling endurance
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 19 and Table 20 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1
Symbol VDDA VDDA VSSA VREFH VREFL VADIN CADIN
RADIN RAS
ADC conversion clock frequency ADC conversion clock frequency ADC conversion rate
Min. 37.037
Typ.1
Max. 461.467
Unit Ksps
Notes 6
Z ADIN
SIMPLIFIED CHANNEL SELECT CIRCUIT
Z AS R AS V ADIN V AS C AS
R ADIN
R ADIN
INPUT PIN
R ADIN C ADIN
INPUT PIN
6.6.1.2
Symbol IDDA_ADC
Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description ADC asynchronous clock source Conditions1 ADLPC = 1, ADHSC = 0 ADLPC = 1, ADHSC = 1 ADLPC = 0, ADHSC = 0 ADLPC = 0, ADHSC = 1 Sample Time TUE Total unadjusted error Differential nonlinearity Min. 1.2 2.4 3.0 4.4 Typ.2 2.4 4.0 5.2 6.2 Max. 3.9 6.1 7.3 9.5 Unit MHz MHz MHz MHz LSB4 Notes tADACK = 1/ fADACK
fADACK
See Reference Manual chapter for sample times 12-bit modes <12-bit modes 12-bit modes <12-bit modes 4 1.4 0.7 0.2 1.0 0.5 -4 -1.4 -1 to 0 -5.4 -1.8 0.5 6 12.8 11.9 14.5 13.8 bits bits LSB4 LSB4 VADIN = VDDA 5 -2.7 to +1.9 -0.7 to +0.5 <12-bit modes 12-bit modes <12-bit modes LSB4 5 6.8 2.1 -1.1 to +1.9 -0.3 to 0.5 12-bit modes LSB4 5 5
DNL
INL
Integral nonlinearity
EFS
Full-scale error
EQ
Quantization error
ENOB
Effective number 16-bit differential mode of bits Avg = 32 Avg = 4 16-bit single-ended mode Avg = 32 Avg = 4
12.2 11.4
bits bits dB 7
SINAD THD
See ENOB 16-bit differential mode Avg = 32 16-bit single-ended mode Avg = 32
94 -85
dB dB 7
SFDR
Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol EIL Description Input leakage error Conditions1 Min. Typ.2 IIn RAS Max. Unit mV Notes IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage Across the full temperature range of the device 25 C 1.715 719 mV/C mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD 0.7 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64
CMP Hysteresis vs Vinn
90.00E-03
80.00E-03
70.00E-03
50.00E-03
HYSTCTR S etting
0 1
40.00E-03
2 3
30.00E-03
20.00E-03
10.00E-03
000.00E+00 0.1 0.4 0.7 1 1.3 1.6 Vinn (V) 1.9 2.2 2.5 2.8 3.1
160.00E-03
140.00E-03
120.00E-03
100.00E-03
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00 0.1 -20.00E-03 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vinn (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3.1
Symbol VDDA VDACR TA CL IL
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
6.6.3.2
Symbol
P
IDDA_DACL Supply current low-power mode IDDA_DACH Supply current high-speed mode
P
tDACLP tDACHP
Full-scale settling time (0x080 to 0xF7F) low-power mode Full-scale settling time (0x080 to 0xF7F) high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) low-power mode and high-speed mode Vdacoutl Vdacouth INL DNL DNL DAC output voltage range low high-speed mode, no load, DAC set to 0x000 DAC output voltage range high highspeed mode, no load, DAC set to 0xFFF Integral non-linearity error high speed mode Differential non-linearity error VDACR > 2 V Differential non-linearity error VDACR = VREF_OUT Gain error Power supply rejection ratio, VDDA 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Output resistance load = 3 k
1. 2. 3. 4. 5. 6.
Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR 100 mV The DNL is measured for 0 + 100 mV to VDACR 100 mV The DNL is measured for 0 + 100 mV to VDACR 100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device
6.7 Timers
See General switching specifications.
1. Typical values assume VREGIN = 5.0 V, Temp = 25 C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
Table 25. SPI master mode timing on slew rate disabled pads (continued)
Num. 2 3 4 5 6 7 8 9 10 11 Symbol tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 25 ns Min. 2 x tperiph 1/2 1/2 tperiph - 30 16 0 0 Max. 2048 x tperiph 1024 x tperiph 10 tperiph - 25 Unit ns tSPSCK tSPSCK ns ns ns ns ns ns Note 2
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph
Table 26. SPI master mode timing on slew rate enabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 36 ns Min. fperiph/2048 2 x tperiph 1/2 1/2 tperiph - 30 96 0 0 Max. fperiph/2 2048 x tperiph 1024 x tperiph 52 tperiph - 25 Unit Hz ns tSPSCK tSPSCK ns ns ns ns ns ns Note 1 2
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph
2 5 5
10
11
10
11
6 MISO (INPUT)
MOSI (OUTPUT)
MSB OUT2
BIT 6 . . . 1
1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
10
11
10
11
6 MISO (INPUT)
LSB IN
BIT 6 . . . 1
PORT DATA
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA = 1) Table 27. SPI slave mode timing on slew rate disabled pads
Num. 1 2 3 4 5 Symbol fop tSPSCK tLead tLag tWSPSCK Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Min. 0 4 x tperiph 1 1 tperiph - 30 Max. fperiph/4 Unit Hz ns tperiph tperiph ns Note 1 2
Table 27. SPI slave mode timing on slew rate disabled pads (continued)
Num. 6 7 8 9 10 11 12 13 Symbol tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 2. 3. 4. Description Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 25 ns Min. 2 7 0 Max. tperiph tperiph 22 tperiph - 25 Unit ns ns ns ns ns ns ns Note 3 4
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state
Table 28. SPI slave mode timing on slew rate enabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 2. 3. 4. Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 36 ns Min. 0 4 x tperiph 1 1 tperiph - 30 2 7 0 Max. fperiph/4 tperiph tperiph 122 tperiph - 25 Unit Hz ns tperiph tperiph ns ns ns ns ns ns ns ns Note 1 2 3 4
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state
SS (INPUT) 2 12 13 4
12
13 9
8 MISO (OUTPUT) see note 6 MOSI (INPUT) NOTE: Not defined! SLAVE MSB 7 MSB IN
10 BIT 6 . . . 1
11
11 SEE NOTE
BIT 6 . . . 1
LSB IN
4 12 13
12
13
10 MISO (OUTPUT) MOSI (INPUT) NOTE: Not defined! see note 8 SLAVE 6 MSB IN MSB OUT 7
BIT 6 . . . 1
LSB IN
6.8.4 I2C
See General switching specifications.
6.8.5 UART
See General switching specifications.
KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
44 Freescale Semiconductor, Inc.
Dimensions
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for the drawings document number:
If you want the drawing for this package 32-pin QFN 48-pin QFN 64-pin LQFP 80-pin LQFP Then use this document number 98ASA00473D 98ASA00466D 98ASS23234W 98ASS23174W
8 Pinout
Pinout
23 24 25 26 27 28 29 30 31
19 20 21 22 23 24 25 26 27
15 16 17 18 19 20 21
10 11 12 13 14
PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 UART0_RX UART0_TX I2C1_SCL I2C1_SDA USB_CLKIN
TPM0_CH4 TPM0_CH0 TPM0_CH1 TPM0_CH5 TPM2_CH0 TPM2_CH1 TPM0_CH0 TPM0_CH1 TPM0_CH2 SWD_DIO NMI_b I2C0_SCL I2C0_SDA SWD_CLK
Pinout 80 64 LQFP LQFP 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 48 QFN 22 23 24 25 26 27 28 29 30 31 32 33 34 32 QFN 15 16 17 18 19 20 21 22 Pin Name PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA19 RESET_b PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB8 PTB9 PTB10 PTB11 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 VSS VDD PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 Default DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED VDD VSS EXTAL0 XTAL0 RESET_b ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 DISABLED DISABLED DISABLED DISABLED TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 DISABLED VSS VDD DISABLED DISABLED CMP0_IN0 CMP0_IN0 VSS VDD PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 SPI0_PCS0 SPI0_SCK SPI0_MOSI UART1_TX LPTMR0_ ALT2 EXTRG_IN SPI0_MISO TPM0_CH3 CMP0_OUT TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 VDD VSS EXTAL0 XTAL0 PTA18 PTA19 PTA20 PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB8 PTB9 PTB10 PTB11 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 I2C1_SCL SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART0_RX UART0_TX TPM2_CH0 TPM2_CH1 EXTRG_IN TPM0_CH0 CMP0_OUT TPM_CLKIN0 TPM_CLKIN1 SPI1_MISO SPI1_MOSI I2C0_SCL I2C0_SDA I2C0_SCL I2C0_SDA TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 EXTRG_IN UART1_RX UART1_TX TPM_CLKIN0 TPM_CLKIN1 LPTMR0_ ALT1 ALT0 ALT1 PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO ALT2 ALT3 TPM1_CH0 TPM1_CH1 UART0_TX UART0_RX SPI0_MISO SPI0_MOSI ALT4 ALT5 ALT6 ALT7
57 58 59 60 61 62 63
45 46 47 48 49 50 51
35 36 37 38 39
23 24 25 26 27
I2C1_SDA UART1_RX
Pinout 80 64 LQFP LQFP 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 52 53 54 55 56 57 58 59 60 61 62 63 64 48 QFN 40 41 42 43 44 45 46 47 48 32 QFN 28 29 30 31 32 Pin Name PTC7 PTC8 PTC9 PTC10 PTC11 PTC12 PTC13 PTC16 PTC17 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 Default CMP0_IN1 CMP0_IN2 CMP0_IN3 DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED ADC0_SE5b DISABLED DISABLED DISABLED ADC0_SE6b ADC0_SE7b DISABLED ADC0_SE6b ADC0_SE7b ADC0_SE5b ALT0 CMP0_IN1 CMP0_IN2 CMP0_IN3 ALT1 PTC7 PTC8 PTC9 PTC10 PTC11 PTC12 PTC13 PTC16 PTC17 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART2_RX UART2_TX UART2_RX UART2_TX UART0_RX UART0_TX TPM0_CH0 TPM0_CH1 TPM0_CH2 TPM0_CH3 TPM0_CH4 TPM0_CH5 SPI1_MISO SPI1_MOSI SPI0_MISO SPI0_MOSI ALT2 SPI0_MISO I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA TPM_CLKIN0 TPM_CLKIN1 TPM0_CH4 TPM0_CH5 ALT3 ALT4 ALT5 SPI0_MOSI ALT6 ALT7
Pinout
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC12
PTC13
PTC11
PTC10
PTD2
PTD7
PTD5
PTD3
PTD1
PTC9
PTC8
PTD0
71
PTC7
PTC5/LLWU_P9 62
PTC17
79
75
72
69
80
78
76
68
70
67
66
65
64
77
74
PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 25 26 28 29 31 23 24 27 32 35 30 36 33 34 37 38 39 40
73
63
61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PTC4/LLWU_P8
PTC16
VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB11 PTB10 PTB9 PTB8 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19
PTE29
PTE30
PTE25
PTA0
PTA3
PTA5
PTE31
PTE24
PTA12
PTA15
PTA16
PTA13
PTA14
PTA17
PTA18
PTA1
PTA2
PTA4
VDD
VSS
Pinout
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTD0
PTC9
PTD7
PTC8
61
62
59
55
52
51
PTC5/LLWU_P9 50
PTC11
PTD3
PTD1
58
64
60
57
56
54
PTE0 PTE1 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 25 26 23 24 27 28 29 31 17 18 19 20 30
63
53
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PTC4/LLWU_P8
PTC10
PTD5
PTD2
PTC7
VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19
PTE30
PTE31
PTE29
PTE24
PTE25
PTA0
PTA3
PTA12
PTA13
PTA4
VSS
PTA18
PTA1
PTA2
PTA5
VDD
Pinout
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
38
48
46
45
47
44
43
42
41
40
39
37
PTC4/LLWU_P8
PTD7
PTD5
PTD3
PTD2
PTD1
PTD0
PTC7
VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 VDDA VREFH VREFL VSSA
1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 13 14 15 16 17 18 19 20 24
36 35 34 33 32 31 30 29 28 27 26 25
PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19
PTE24
PTE25
PTA1
PTA2
PTE29
PTE30
PTA0
PTA3
PTA4
VDD
PTA18
VSS
Revision History
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
26
32
31
29
30
28
27
25
PTC4/LLWU_P8
PTD7
PTD5
PTC7
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21 20 19 18 17
PTA1
PTA2
PTE30
VDD
PTA0
PTA3
9 Revision History
The following table provides a revision history for this document.
Table 30. Revision History
Rev. No. 1 2 3 Date 7/2012 9/2012 9/2012 Substantial Changes Initial NDA release. Completed all the TBDs, initial public release. Updated Signal Multiplexing and Pin Assignments table to add UART2 signals.
PTA4
VSS
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