1

2
Design Of A Wireless Sensing
Location Finding
System
ADC SENSOR MEMORY
PROCESSOR
PROCESSOR UNIT
TRANSCEIVER
Mobilizer
Sensing
Unit
Processing
Unit
Power
Generator
3
Analog to Digital (A/D) Converter
Input signal
Sampling rate
Throughput
Resolution
Range
Gain
Physical
System
Computer
A/D
Converter
Signal
Conditioning
Transducer
Sensor
Amplification
Isolation
Filtering
Linearization
Temperature
Pressure
Light
Force
Noisy Electrical
Signal
Digitized Signal 8-Bit Binary Code
4
Fundamentals of Sampled Data
Systems
Analog-to-Digital converters (ADCs) translate analog quantities, wich are
characteristic of most phenomen in the real world to digital language, used in
information processing, computing, data transmission, and control systems
Digital-to-Analog converters (DACs) are used in transforming transmitted or
stored data, or the results of digital processing, back to real world variables
for control, information display, or further analog processing
5
Digital Number
Digital number used are all basically binary : that is, each bit or unit of information
has one of two possible states.
These state are :
off, false, or 1
on, true , or 0
It is also possible to represent the two logic state by two different levels of current ;
however, this is much less popular than using voltages .
Word are groups of levels representing digital numbers; the levels may appear
simultaneously in paralel , on a bus or groups of gate inputs or outputs,
serially (or in time sequence) on a single line,
as a sequence of parallel bytes (i.e. byte serial) or nibbles (small bytes)
A unique parallel or serial grouping of digital levels, or a number, or code, is assigned
to each analog level which is quantized (i.e., represents a unique portion of the
analog range).
6
Typical Digital Code
A typical digital code would be this array :
1 0 0 1 1 1 0 1 a a a a a a a a
0 1 2 3 4 5 6 7
=
MSB
LSB
The meaning of the code, as either a number, a character, or a representation of
an analog variable is unknow until the code and the conversion relationship have
been defined
7
Unipolar
Code
Base 10
number
SCALE + 10V FS BANARY GRAY
0 1 0 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
1 0 0 0
1 0 0 1
1 0 1 1
1 0 1 0
1 1 1 0
1 1 1 1
1 1 0 1
1 1 0 0
0 1 0 0
0 1 0 1
3.125
0.000
0.625
1.250
1.875
2.500
9.375
8.750
8.125
7.500
6.875
6.250
5.625
5.000
4.375
3.750
+5
0
+1
+2
+3
+4
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
0
1LSB = +1/16 FS
+FS - 1LSB = +15/16 FS
+7/8 FS
+13/16 FS
+3/4 FS
+11/16 FS
+5/8 FS
+9/16 FS
+1/2 FS
+7/16 FS
+3/8 FS
+5/16 FS
+1/4 FS
+3/16 FS
+1/8 FS
8
Bipolar
Codes
Base 10
number
SCALE 5V FS
OFFSET
BANARY
TWOS
COMP.
0 1 0 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
1 1 0 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
1 1 1 1
1 1 1 0
-1.875
-5.000
-4.375
-3.750
-3.125
-2.500
+4.375
+3.750
+3.125
+2.500
+1.875
+1.250
+0.625
0.000
-0.625
-1.250
-3
-8
-7
-6
-5
-4
+7
+6
+5
+4
+3
+2
+1
0
-1
-2
-FS
+FS - 1LSB = +7/8 FS
+3/4 FS
+5/8 FS
+1/2 FS
+3/8 FS
+1/4 FS
+1/8 FS
0
-1/8 FS
-1/4 FS
-3/8 FS
-1/2 FS
-5/8 FS
-3/4 FS
-FS + 1LSB = -7/8 FS

ONES
COMP.
1 1 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
* 0 0 0 0
1 1 1 0
1 1 0 1
SIGN
MAG.
1 0 1 1
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
* 1 0 0 0
1 0 0 1
1 0 1 0
NOT NORMALLY USED
IN COMPUTATIONS
ONES
COMP.
TWOS
COMP.
0 0 0 0 1 0 0 0
1 1 1 1 1 0 0 0
0 +
0 -
*
9
Quantization: The Size of a Least
Significant Bit (LSB)
Resolution
N
2
N
VOLTAGE
(10V FS)
ppm FS % FS dB FS
2-bit 4 2.5V 250.000 25 -12
4-bit 16 625mV 62.500 6.25 -24
6-bit 64 156mV 15.625 1.56 -36
8-bit 256 39.1mV 3.906 0.39 -48
10-bit 1.024 9.77mV (10mV) 977 0.098 -60
12-bit 4.096 2.44mV 244 0.024 -72
14-bit 16.384 610V 61 0.0061 -84
16-bit 65.536 153V 15 0.0015 -96
18-bit 262.144 38V 4 0.0004 -108
20-bit 1.048.576 9.54V (10V) 1 0.001 -120
22-bit 4.194.304 2.38V 0.24 0.000024 -132
24-bit 16.777.216 596nV* 0.06 0.000006 -144
The resolution of data converters
( )
converter bit n for
1 2
FSR
LSB 1
n

=
10
The Ideal Transfer Function (ADC)
0 0.5 0 ... 000
0.5 1.5 0 ... 001
1.5 2.5 0 ... 010
2.5 3.5 0 ... 011
3.5 4.5 0 ... 100
RANGE OF
ANALOG
INPUT
CODE
DIGITAL
OUTPUT CODE
0
3 2 1 0
5 4 3 1 2
4 5
4.5 5.5 0 ... 101
0 ... 000
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
Digital Output
Code
Analog Input Value
Analog Input Value
Step
Ideal Straight Line
Step Width (1 LSB)
Center
CONVERSION CODE
Quantization
Error
+
LSB
-
LSB
Inherent Qiantization Error ( LSB)
The theoretical ideal transfer function for an ADC is a straight line, however, the
practical ideal transfer function is a uniform staircase characteristic shown in Figure .
11
The Ideal Transfer Function (DAC)
0...100
4
0...101
5
0
5
4
3
2
1
Analog Output
Value
Ideal Straight Line
Step Height (1 LSB)
0...000 0...101 0...100 0...011 0...010 0...001
Step Value
Digital Outpit Code
Step
0...001
1
0...010
2
0...011
3
0...000
0
Digital Input Code
Analog Output Value
Conversion Code
The DAC theoretical ideal transfer function would also be a straight line with an infinite
number of steps but practically it is a series of points that fall on the ideal straight line as
shown in Figure
12
Sources of Static Error
Static errors, that is those errors that affect the accuracy of the converter when it
is converting static (dc) signals, can be completely described by just four terms.
These are :
Each can be expressed in LSB units or sometimes as a percentage of the FSR
offset error,
gain error,
integral nonlinearity and
differential nonlinearity.
13
Offset Error - ADC
Nominal
Offset Point
Actual
Offset Point
001
010
011
000
Ideal
Diagram
Actual
Diagram
0 1 2 3
LSB 2 1 +
LSB 4 1 1 +
Offset Error
Analog Output Value
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
The offset error is efined
as the difference between
the nominal and actual
offset points.
14
Offset Error - DAC
1
2
3
0
Ideal Diagram
Actual
Diagram
000 001 010 011
LSB 4 1 1 +
Digital Input Code
Offset Error
Nominal
Offset Point
Actual
Offset Point
A
n
a
l
o
g

O
u
t
p
u
t

V
a
l
u
e

(
L
S
B
)
For a DAC it is the step value when the digital input is zero. This error affects all
codes by the same amount and can usually be compensated for by a trimming
process. If trimming is not possible, this error is referred to as the zero-scale error.
15
Gain Error - ADC
101
110
111
000
Ideal Diagram
Actual Diagram
0 5 6 7
LSB 2 1 +
Analog Input Value (LSB)
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
Nominal Gain
Point
Actual Gain Point
Gain Error
LSB 4 3 +
The gain error is defined as the difference between the nominal and actual gain
points on the transfer function after the offset error has been corrected to zero.
For an ADC, the gain point is the midstep value when the digital output is full scale,
16
Gain Error - DAC
4
5
6
0
Ideal Diagram
000 100 101 110
LSB 4 1 1
Digital Input Code
Offset Error A
n
a
l
o
g

O
u
t
p
u
t

V
a
l
u
e

(
L
S
B
)
7
111
Actual Gain Point
Gain Error
Nominal Gain Point
For a DAC it is the step value when the digital input is full scale. This error
represents a difference in the slope of the actual and ideal transfer functions
This error can also usually be adjusted to zero by trimming.
17
Differential Nonlinearity (DNL) Error - ADC
0
0 ... 001
6 5 4 3 2 1
0 ... 010
0 ... 011
0 ... 100
0 ... 101
0 ... 110
0 ... 000
LSB 1
LSB 1
Differential
Linearity Error
Differential
Linearity Error
Analog Input Value (LSB)
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
( ) LSB 2 1
( ) LSB 2 1
DNL is the difference between an actual step width (for an ADC) and the ideal value
of 1 LSB. Therefore if the step width is exactly 1 LSB, then the differential nonlinearity
error is zero.
If the DNL exceeds 1 LSB nonmonotonic (this means that the magnitude of the
output gets smaller for an increase in the magnitude of the input)
If the DNL error of 1 LSB there is also a possibility that there can be missing codes
i.e., one or more of the possible 2n binary codes are never output.
18
Differential Nonlinearity (DNL) Error - DAC
1
2
3
4
5
6
0
LSB 1
LSB 1
Diferential
Linearity Error
Diferential
Linearity Error
Digital Input Code

(
L
S
B
)
( ) LSB 4 1
( ) LSB 4 1 +
0 ... 000 0 ... 100 0 ... 010
0 ... 101 0 ... 011 0 ... 001
0 ... 110
A
n
a
l
o
g

O
u
t
p
u
t

V
a
l
u
e
The differential nonlinearity error shown in Figure is the difference between an
actual step height (for a DAC) and the ideal value of 1 LSB. Therefore if the step
height is exactly 1 LSB, then the differential nonlinearity error is zero
19
Integral Nonlinerity (INL) Error - ADC
0
001
6 5 4 3 2 1
010
011
100
101
110
000
Analog Input Value (LSB)
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
7
111
At Transition
001/010 (-1/4 LSB)
At Transition
011/100
(-1/2 LSB)
Ideal
Transition
Actual
Transition
End-Point Lin. Error
The integral nonlinearity error shown in Figure is the deviation of the values on the
actual transfer function from a straight line.
This straight line can be either a best straight line which is drawn so as to minimize
these deviations or
it can be a line drawn between the end points of the transfer function once the gain
and offset errors have been nullified (end-point linearity )
20
Integral Nonlinerity (INL) Error - DAC -
000
1
110 101 100 011 011 001
2
3
4
5
6
0
Digital Input Code
A
n
a
l
o
g

O
u
t
p
u
t

V
a
l
u
e

(
L
S
B
)
111
7
At Step
001 (1/4 LSB)
At Step
011 (1/2 LSB)
End-Point Lin. Error
The name integral
nonlinearity derives from
the fact that the
summation of the
differential
nonlinearities from the
bottom up to a particular
step, determines the value
of the integral nonlinearity
at that step.
21
Absolute Accuracy (Total) Error -ADC-
0
001
6 5 4 3 2 1
010
011
100
101
110
000
Analog Input Value (LSB)
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
7
111
Total Error
At Step
0 ... 001 (1/2 LSB)
Total Error
At Step 0 ... 101
(-1 1/4 LSB)
The absolute accuracy or total error of an ADC as shown in Figure is the maximum
value of the difference between an analog value and the ideal midstep value.
It includes offset, gain, and integral linearity errors and also the quantization error in
the case of an ADC
22
Absolute Accuracy (Total) Error -DAC-
0 ... 000
1
0 ... 110
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
2
3
4
5
6
0
Digital Input Code
A
n
a
l
o
g

I
n
p
u
t

V
a
l
u
e

(
L
S
B
)
0 ... 111
7
Total Error
At Step 0 ... 011
(1 1/4 LSB)
23
Sampling Theory
Prior to the actual analog-to-digital conversion, the analog signal usually
passes through some sort of signal conditioning circuitry which performs
such functions as amplification, attenuation, and filtering.
The lowpass/bandpass filter is required to remove unwanted signals
outside the bandwidth of interest and prevent aliasing.
There are two key concepts involved in the actual analog-to-digital and digital-
to-analog conversion process:
An understanding of these concepts is vital to data converter applications.
discrete time sampling and
finite amplitude resolution due to quantization.
24
Sampling Theory
The system shown in Figure is real-time system ; i.e., the signal to the ADC is
continuously sampled at a rate equal to f
S
, and the ADC presents a new sample to
the DSP at this rate.
In order to maintain real-time operation, the DSP must perform all its required
computation within the sampling interval, 1/f
S,
and present an output sample to
the DAC before arrival of the next sample from the ADC.
25
The Need for a Sample-and-Hold
Amplifier (SHA) Function
Most ADCs today have a built-in-sample-and-hold function, thereby allowing them
to process ac signals.
This type of ADC is referred to as a sampling ADC
If the input signal to a SAR ADC (assuming no SHA function) changes by more than
1LSB during the conversion time (8s is the example), the output data can have
large errors, depending on the location of the code
Most ADC architectures are subject to this type of error some more, some less
with the possible exception of flash converters having well-matched comparators
26
Input Frequency Limitations of
Nonsampling ADC (Encoder)
N-BIT
SAR ADC ENCODER
CONVERSION TIME = 8s
N
ANALOG INPUT
N
max
max
) 1 N (
max
max
) 1 N (
max
N
N
2 q
dt
dv
f
q 2 2
dt
dv
f
f 2 2 q
dt
dv
) ft 2 cos( f 2
2
2
q
dt
dv
) ft 2 sin(
2
2
q ) t ( v
t
t
t
t t
t
=
=
=
=
(

kSPS 100 f
S
=
4096 2 , 12 N
s 8 dt
q LSB 1 dv
: EXAMPLE
N
= =
=
= =

Hz 7 . 9 f
max
=
This implies any input
frequency greater than
9.7 Hz is subject to
conversion errors, even
though a sampling
frequency of 100 kSPS
is possible with the 8s
ADC (this allows an
extra 2s interval for an
external SHA to
reacquire the signal
after coming out of hold
mode).
27
Sample-and-Hold Function Required
for Digitizing AC Signals
Sample-and-hold
amplifier (SHA)
Track-and-hold
amplifier (THA).
TIMING
ADC
ENCODER
SAMPLING
CLOCK
ANALOG
INPUT
C
N
SW
CONTROL
HOLD
SAMPLE SAMPLE
ENCODER CONVERTS
DURING HOLD TIME
SW
CONTROL
28
The Nyquist Criteria
A continuous analog signal is sampled at discrete intervals, f
S
,which must be
carefully chosen to ensure an accurate representation of the original analog signal
The Nyquist criteria requiries that the sampling frequency be at least twice
the highest frequency contained in the signal, or information about the signal
will be lost
If the sampling frequency is less than twice the maximum analog signal frequency,
a phenomen know as aliasing will occur
A signal with a maximum frequency .. must be sampled at a rate .... or information
about the signal will be lost because of aliasing
Aliasing occurs whenever ...
A signal which has frequency components between .. and.... must be sampled at
a rate ...... in order to prevent alias components from overlapping the signal
frequencies
29
Aliasing in Time Domain
In order to understand the implications of aliasing in both the time and frequency
domain, first consider the case of a time domain representation of a single tone
sinewave sampled as shown in Figure
30
Matlab Example - 1
31
Matlab Example - 2
32
Matlab Example - 3
33
Matlab Example - 4
34
Matlab Example - 5
35
Aliasing in Frequency Domain
Consider the case of a single frequency sinewave of frequency f
a
sampled at
a frequency f
s
by an ideal impulse sampler.
Also assume that f
s
> 2f
a
as shown.
The frequency-domain output of the sampler shows aliases or images of the
original signal around every multiple of f
s
, i.e. at frequencies equal to | Kf
s
f
a
|, K
= 1, 2, 3, 4, .....
36
Baseband Antialiasing Filter
Baseband sampling implies that the signal to be sampled lies in the first Nyquist
zone.
It is important to note that with no input filtering at the input of the ideal sampler,
any frequency component (either signal or noise) that falls outside the
Nyquist bandwidth in any Nyquist zone will be aliased back into the first
Nyquist zone.
For this reason, an antialiasing filter is used in almost all sampling ADC
applications to remove these unwanted signals.
The antialiasing filter transition band is therefore determined by the corner
frequency fa, the stopband frequency fs fa, and the desired stopband
attenuation, DR. The required system dynamic range is chosen based on the
requirement for signal fidelity.
For instance, a Butterworth filter gives 6-dB attenuation per octave for each
filter pole (as do all filters). Achieving 60 dB attenuation in a transition
region between 1 MHz and 2 MHz (1 octave) requires a minimum of 10
polesnot a trivial filter, and definitely a design challenge.
37
Oversampling Relaxes Requirements
on Baseband Antialiasing Filter
The effects of increasing the sampling frequency by a factor of K, while
maintaining the same analog corner frequency, fa, and the same dynamic
range, DR, requirement. The wider transition band (f
a
to Kf
s
f
a
) makes this
filter easier to design
38
Comparing a Nyquist rate (a) and
Oversampling strategies (b)
39
Data Converter AC Error
The only errors (dc or ac) associated with an ideal N-bit data converter are
those related to the sampling and quantization processes.
The maximum error an ideal converter makes when digitizing a signal is
LSB.
The transfer function of an ideal N-bit ADC is shown in Figure
40
Quantization Noise as a Function of Time
41
FFT diagram of a multi-bit ADC with a
sampling frequency F
S
This noise is approximately Gaussian and spread more or less uniformly
over the Nyquist bandwidth dc to fs/2.
42
Theoretical Signal-to-Quantization Noise Ratio
of an Ideal N-Bit Converter
43
Procces Gain
In many applications,
the actual signal of interest occupies a smaller bandwidth, BW.
If digital filtering is used to filter out noise components outside the bandwidth
BW, then a correction factor (called process gain) must be included in the quation
to account for the resulting increase in SNR.
44
45
SINAD, ENOB, SNR
46
Dynamic Range
47
Spurious Free Dynamic Range (SFDR)
Probably the most significant specification for an ADC used in a communications
application is its spurious free dynamic range (SFDR).
SFDR of an ADC is defined as the ratio of the rms signal amplitude to the rms value
of the peak spurious spectral content measured over the bandwidth of interest.
SFDR is generally plotted as a function of signal amplitude and may be expressed
relative to the signal amplitude (dBc) or the ADC full-scale (dBFS) as shown in
Figure
48
Aperture Time, Aperture Delay Time,
and Aperture Jitter
49
Design a Low-Jitter Clock for High-Speed
Data Converter
Many modern, high speed, high performance ICs ADCs require a low-phase-noise
(low-jitter) clock that operates in the GHz range
Conventional crystal oscillators may provide a low jitter clock signal, but are not
generally available in oscilating frequencies above 120 MHz
Bandpass
Filter
1 GHz ADC
VCO PLL
Crystal
Oscillator
Analog
Input
High-Speed, Low-Jitter Clock
Typical high-speed data converter system
50
J itter in clock signal degrades the ADC
signal-to-noise ratio.
Time
A
m
p
l
i
t
u
d
e
t A t A t A t A
Jitter
Jitter is generally defined as short-term, non-cumulative variation of the
significant instant of a digital signal from its ideal position in time.
Figure illustrates a sampling clock signal that contains jitter. Jitter generated by the
clock is caused by various internal noise sources, such as thermal noise, phase
noise, and spurious noise.
A clock signal that has cycle-to-cycle variation in its duty cycle is said to
exhibit jitter. Clock jitter causes an uncertainty in the precise sampling time,
resulting in a reduction of dynamic performance.
51
How Clock Jitter Degrades ADC's
Signal-to-Noise Ratio (SNR)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time (s)
A
m
p
l
i
t
u
d
e
Continuous-Time Signal; x(t) = sin(7t)
A A
t A
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time (s)
A
m
p
l
i
t
u
d
e
Continuous-Time Signal; x(t) = sin(7t)
A A
t A
t
A
SLOPE
A
A
=
( )
e A A
e
A
A
e e
A
t
1
A
A
A
t
A
t cos A slope
A
A
=
=
= =
RMS RMS
ADC
f 2
1 1
SNR
o t e o
= =
ps 2 jitter RMS Maximum
dB 50 SNR
MHz 250 signal input log Ana
: Example
<
52
The functional diagram
an integer-N PLL system
Crystal
Oscilator
Phase
Comparator
Charge
Pump
VCO

M
R
A
P

Loop Filter
Consists of a phase detector (or comparator), an output charge-pump, a dual
modulus prescalar, an N counter, and an R counter. The N counter consists of a
main (M) counter and a swallow or auxiliary (A) counter. The N counter then works
in conjunction with the dual modulus pre-scalar (P)
REF VCO
f
R
N
f =
( ) M A A PM N < + =
53
Basic DAC Structures
V
REF
OUTPUT
1-Bit DAC: Changeover Switch (Single-Pole, Double Throw, SPDT)
Such a simple device is a component of many more complex DAC structures, and
is used, with oversampling, as the basic component in many of the sigma-delta
DACs
switching an output between a reference and ground or between
equal positive and negative reference voltages, as a 1-bit DAC
54
The Comparator: A 1-Bit ADC
+
-
LATCH
ENABLE
DIFERENTIAL
ANALOG
INPUT
LOGIC
OUTPUT
As a changeover switch is a 1-bit DAC, so a comparator is a 1-bit ADC.
If the input is above a threshold, the output has one logic value, below it has
another.
Comparators used as building blocks in ADCs need good resolution which
implies high gain. This can lead to uncontrolled oscillation when the differential
input approaches zero. In order to prevent this, hysteresis is often added to
comparators using a small amount of positive feedback
COMPARATOR
OUTPUT
0
V
HYSTERESIS
''1''
''0''
DIFFERENTIAL ANALOG INPUT
55
The Comparator: A 1-Bit ADC cont.
Most modern comparators used in ADCs include a built-in latch which makes
them sampling devices suitable for data converters.
A typical structure is shown in Figure
The latch thus performs a track-and-hold function, allowing short input signals
to be detected and held for further processing.
PREAMP
+
-
LATCH
ENABLE
LATCH
Q
Q
56
ADC Architectures
Flash Converters
Successive Aproximation ADCs
Pipelined ADCs
Integrating ADC
Sigma-Delta ADC
57
Classification ADC
Most ADC applications today can be classified into four broad market segments:
(a) data acquisition,
(b) precision industrial measurement,
(c) voiceband and audio, and
(d) high speed (implying sampling rates greater than about 5 MSPS).
A very large percentage of these applications can be filled by
A basic understanding of these, the three most popular ADC architecturesand their
relationship to the market segmentsis a useful supplement to the selection guides and
search engines.
successive-approximation (SAR),
sigma-delta (E-A), and
pipelined ADCs
58
ADC Architectures, applications,
resolution and sampling rates - 1
59
ADC Architectures, applications,
resolution and sampling rates - 2
Sigma Delta
and
Oversampling
Converters
6
16
14
12
10
8
20
18
1k 10G 1G 100M 10M 1M 100k 10k
Flash
converters
Pipeline
ADC
Error
calibration
Resolution vs. Speed
Sample Rate
R
e
s
o
l
u
t
i
o
n
Recent
Trends
60
Flash Converters
Flash analog-to-digital converters, also known as parallel ADC
S
, are the fastest way
to convert an analog signal to a digital signal.
An N-bit flash ADC consists of 2
N
resistors and 2
N
1 comparators arranged as in
Figure.
Since 2
N
1 data outputs are not really practical, they are processed by a decoder to
generate an N-bit binary output.
very large bandwidths.
consume a lot of power,
have relatively low resolution,
can be quite expensive
61
Architecture Detail
The reference voltage for each comparator is one least significant bit (LSB)
greater than the reference voltage for the comparator immediately below it.
PRIORITY
ENCODER
AND
LATCH
62
Sparkle Codes and Metastability
Normally, the comparator outputs will be a thermometer code, such as 00011111.
Errors may cause an output like 00010111 (i.e., there is a spurious zero in the
result).
This out of sequence "0" is called a sparkle. This may be caused by imperfect input
settling or comparator timing mismatch.
The magnitude of the error can be quite large.
Modern converters employ an input track-and-hold in front of the ADC along
with an encoding technique that suppresses sparkle codes.
When a digital output of a comparator is ambiguous (neither a one nor a zero), the
output is defined as metastable. Metastability can be reduced by allowing more
time for regeneration. Gray-code encoding can also greatly improve metastability.
63
Successive-Approximation ADCs
The successive-approximation ADC is by far the most popular architecture for data-acquisition
applications, especially when multiple channels require input multiplexing.
Modern IC SAR ADCs are available in resolutions from 8 bits to 18 bits, with sampling rates up
to several MHz.
Output data is generally provided via a standard serial interface (I2C or SPI), but some devices
are available with parallel outputs
64
Operation Algorithm
In order to process rapidly changing signals, SAR ADCs have an input sample-and-hold (SHA) to keep
the signal constant during the conversion cycle.
The conversion starts with the internal D/A converter (DAC) set to midscale.
The comparator determines whether the SHA output is greater or less than the DAC output, and the
result (the most-significant bit (MSB) of the conversion) is stored in the successive-approximation register
(SAR) as a 1 or a 0.
The DAC is then set either to 14 scale or 34 scale (depending on the value of the MSB), and the
comparator makes the decision for the second bit of the conversion
The result (1 or 0) is stored in the register, and the process continues until all of the bit values have been
determined.
At the end of the conversion process, a logic signal (EOC, DRDY, BUSY, etc.) is asserted.
The acronym, SAR, which actually stands for successive-approximation registerthe logic block that
controls the conversion processis universally understood as an abbreviated name for the entire
architecture.
65
Basic Successive-Approximation ADC
The overall accuracy and linearity of the
SAR ADC are determined primarily by the
internal DACs characteristics
66
Functional block Diagram of a modern
1-MSPS SAR
The sequencer allows automatic conversion of the selected channels, or channels
can be addressed individually if desired. Data is transferred via the serial port.
SAR ADCs are popular in multichannel data-acquisition applications
67
Pipelined ADCs for High-Speed Applications
(Sampling Rates Greater than 5 MSPS)
instrumentation applications (digital oscilloscopes,
spectrum analyzers, and medical imaging).
video, radar, communications (IF sampling, software
radio, base stations, set-top boxes, etc.),
consumer electronics (digital cameras, display
electronics, DVD, enhanced-definition TV, and high-
definition TV)
The low-power CMOS pipelined converter is the ADC of choice, not only for the video market but for
many others as well
Today, markets that require high speed ADCs include many types of:
The pipelined ADC has its origins in the subranging architecture
A block diagram of a simple 6-bit, two-stage subranging ADC is shown in Figure
68
6-bit, two-stage subranging ADC
The output of the SHA is digitized by the first-stage 3-bit sub-ADC (SADC)usually a flash converter.
The coarse 3-bit MSB conversion is converted back to an analog signal using a 3-bit sub-DAC (SDAC).
Then the SDAC output is subtracted from the SHA output, the difference is amplified, and this residue
signal is digitized by a second-stage 3-bit SADC to generate the three LSBs of the total 6-bit output word
69
Residue waveform at input of
second-stage SADC
This waveform is typical for a low-frequency ramp signal applied to the analog input of the ADC.
In order for there to be no missing codes, the residue waveform must not exceed the input range of the
second-stage ADC, (Figure A).
The situation shown in Figure B will result in missing codes when the residue waveform goes outside the
range of the N2 SADC, R, and falls within the X or Y regionswhich might be caused by a nonlinear
N1 SADC or a mismatch of interstage gain and/or offset.
70
The error-corrected subranging ADC
architecture
A basic 6-bit subranging ADC with error correction is shown in Figure, with the second-stage
resolution increased to 4 bits, rather than the original 3 bits. Additional logic, required to modify
the results of the N1 SADC when the residue waveform falls in the X or Y overrange regions, is
implemented with a simple adder in conjunction with a dc offset voltage added to the residue
waveform. In this arrangement, the MSB of the second-stage SADC controls whether the MSBs are
incremented by 001 or passed through unmodified.
71
Pipelined architecture
In order to increase the speed of the basic subranging ADC, the pipelined
architecture has become very popular.
This pipelined ADC has a digitally corrected subranging architecture in
which each of the two stages operates on the data for one-half of the conversion
cycle, and then passes its residue output to the next stage in the pipeline prior
to the next phase of the sampling clock.
The interstage track-and-hold (T/H) serves as an analog delay line it is
timed to enter the hold mode when the first-stage conversion is complete. This
allows more settling time for the internal SADCs, SDACs, and amplifiers, and
allows the pipelined converter to operate at a much higher overall sampling rate
than a nonpipelined version.
72
Generalized pipeline stages
and timing
73
Clock Issues in Pipelined ADCs
Notice that the phases of the clocks to the T/H amplifiers are alternated from stage
to stage such that when a particular T/H in the ADC enters the hold mode it holds
the sample from the preceding T/H, and the preceding T/H returns to the track
mode. The held analog signal is passed along from stage to stage until it reaches
the final stage in the pipelined ADC
74
Dual Slope ADCs
The dual-slope ADC architecture was truly a breakthrough in ADCs for high
resolution applications such as digital voltmeters, etc.
The input signal is applied to an integrator; at the same time a counter is started,
counting clock pulses. After a pre-determined amount of time (T), a reference voltage
having opposite polarity is applied to the integrator. At that instant, the accumulated
charge on the integrating capacitor is proportional to the average value of the input
over the interval T.
75
Dual Slope ADCs cont.
The integral of the reference is an opposite-going ramp having a slope of V
REF
/RC. At
the same time, the counter is again counting from zero. When the integrator output
reaches zero, the count is stopped, and the analog circuitry is reset. Since the charge
gained is proportional to V
IN
T, and the equal amount of charge lost is proportional to
V
REF
tx, then the number of counts relative to the full scale count is proportional to tx/T,
or V
IN
/V
REF
. If the output of the counter is a binary number, it will therefore be a binary
representation of the input voltage.
76
E-A ADC architecture
Modern E-A ADCs for applications requiring high resolution (16 bits to 24 bits)
and effective sampling rates up to a few hundred hertz.
High resolution, together with on-chip programmable-gain amplifiers (PGAs),
allows the small output voltages of sensors such as weigh scales and
thermocouples to be digitized directly.
Proper selection of sampling rate and digital filter bandwidth also yields excellent
rejection of 50-Hz and 60-Hz power-line frequencies.
E-A ADCs offer an attractive alternative to traditional approaches using an
instrumentation amplifier (in-amp) and a SAR ADC.
77
The basic concepts
E-A ADC architecture - 1
Figure A shows a noise spectrum for traditional Nyquist operation, where
the ADC input signal falls between dc and fS/2, and the quantization noise is
uniformly spread over the same bandwidth
78
The basic concepts
E-A ADC architecture - 2
In Figure B, the sampling frequency has been increased by a factor, K, (the
oversampling ratio), but the input signal bandwidth is unchanged.
The quantization noise falling outside the signal bandwidth is then removed with a
digital filter.
The output data rate can now be reduced (decimated) back to the original sampling
rate, f
S
. This process of oversampling, followed by digital filtering and decimation,
increases the SNR within the Nyquist bandwidth (dc to fS/2).
For each doubling of K, the SNR within the dc-to-f
S
/2 bandwidth increases by 3 dB.
79
The basic concepts
E-A ADC architecture - 3
Figure C shows the basic E-A architecture, where the traditional ADC is
replaced by a E-A modulator.
The effect of the modulator is to shape the quantization noise so that most of it
occurs outside the bandwidth of interest, thereby greatly increasing the SNR in
the dc-to-f
S
/2 region.
80
First-order sigma-delta ADC
The heart of this basic modulator is a 1-bit ADC (comparator) and a 1-bit DAC (switch).
The output of the modulator is a 1-bit stream of data.
The noise-shaping function by acting as a low-pass filter for the signal and a high-
pass filter for the quantization noise.
81
Sigma-Delta Modulator Waveforms
Because of negative feedback around the integrator, the average value of the
signal at B must equal V
IN
. If V
IN
is zero (i.e., midscale), there are an equal
number of 1s and 0s in the output data stream. As the input signal goes more
positive, the number of 1s increases, and the number of 0s decreases. Likewise,
as the input signal goes more negative, the number of 1s decreases, and the
number of 0s increases. The ratio of the 1s in the output stream to the total
number of samples in the same intervalthe ones densitymust therefore be
proportional to the dc value of the input
82
Example:
8
3
16
6
=
Analog input 3/8
83
Second-order E-A modulator
84
24-bit E-A Converter
85
Some General Trends in Data
Converters
The general trends in data converters are summarized in Figure :
86
Low Power, Sleep, and Standby Modes
In order to conserve power, especially in battery-powered applications, most modern
data converters have some type of low-power, sleep, or standby mode, where the
major portion of the internal circuitry is powered downusually initiated by
the application of a signal to one of the pins,
software control via internal control registers.
additional power savings can be achieved by disabling some
or all of the external clocks.
Sleep-mode power supply current from a few Ato tens of mA depending
upon the normal-mode power dissipation.
Recovery time from the sleep mode, or power-up time but generally is in the
order of a few s to 100 s.
87
ADC Serial Output Interfaces
Serial outputs on SAR-based and - ADCs since their conversion architecture is
essentially serial.
If an ADC is operating continuously, the period of the sampling clock must be
long enough to transfer all the serial data across the interface at the interface data
rate, with some appropriate amount of headroom.
A 16-bit, 1-MSPS sampling ADC requires a serial output data rate of at least 16
MHz, which would not be a problem with most modern P, Cor DSPs.
Example:
88
ADC Parallel Output Interfaces
Parallel ADC output interfaces are popular, straightforward, and must be used when
the product of sampling rate and resolution exceeds the capacity available
serial links.
Using a maximum LVDS serial data link of 600 Mbits/s requires parallel data
transmission for resolutions/sampling rates greater than 8 bits at 75 MSPS, 10
bits at 60 MSPS, 12 bits at 50 MSPS, 14 bits at 43 MSPS, 16 bits at 38 MSPS, etc.
Example:
89
Data Converter Voltage
References
The accuracy of a data converter is determined by a voltage reference of some
sort.
An exception to this, of course, is an ADC which operates in a ratiometric mode,
where both the input signal and input range scale proportionally to the reference.
Voltage references have a major impact on the performance and accuracy of
analog systems. A 5-mV tolerance on a 5-V reference corresponds to 0.1%
absolute accuracyonly 10 bits. For a 12-bit system, choosing a reference that
has a 1-mV tolerance may be far more cost effective than performing manual
calibration, while both high initial accuracy and calibration will be necessary in a
system making absolute 16-bit measurements.
Example:
90
Ratiometric
ADC can be driven from a single supply voltage which is also used to excite the
remote bridge. Both the analog input and the reference input to the ADC are high
impedance and fully differential. By using the + and SENSE outputs from the
bridge as the differential reference to the ADC, the reference voltage is proportional
to the excitation voltage which is also proportional to the bridge output voltage.
91
Some Popular ADC/DAC Reference Options
92
converter which requires an external reference. It is generally recommended
that a suitable decoupling capacitor be added close to the ADC/DAC REF IN pin
converter that has an internal reference, where the reference is also brought
out to a pin on the device. This allows it to be used other places in the circuit,
provided the loading does not exceed the rated value.
converter which can use either the internal reference or an external
one, but an extra package pin is required. If the internal reference is used,
REF OUT is simply externally connected to REF IN, and decoupled if required.
If an external reference is used as shown, REF OUT is left floating, and the
external reference decoupled and applied to the REF IN pin.
shows an arrangement whereby an external reference can override the
internal reference using a single package pin. The value of the resistor, R, is
typically a few k, thereby allowing the low impedance external reference to
override the internal one when connected to the REF OUT/IN pin.
shows how the external reference is connected to override the internal
reference.
93
Types of Voltage References
Simple Diode Reference Circuits
Basic Bandgap Reference
94
Selecting an A/D Converter
The selection checklist can be broken up into two areas
primary facts which cannot be compromised, and
secondary factors which may allow the designer
some flexibility
Primary
What is the required level of system accuracy?
How many bits of resolution are required?
What is the nature of the analog input signal?
How fast must the converter operate (conversion speed)?
What are the environmental conditions?
Is a track-and-hold circuit required?
95
Selecting an A/D Converter
Secondary
Does the system have multiple channels?
Should the reference be internal or external?
What are the drive amplifier requirements?
What are the digital interface requirements?
What type of digital output format is required?
What are the timing conditions?
96
Caracteristics ADC
Flash
+ High resolution and accuracy
+ Low power consumption
+ Fev external components
- Low input bandwidth
- Limited sampling rate
- V
IN
must retain constant during
conv.
+ Extremly fast
+ High input bandwidth
- Higher power consumption
- Large die size
- High input capacitance
- Expansive
- Sparkle codes
1MSPS 80MSPS
> 200 kSPS
+ High resolution
+ High input bandwidth
+ Digital on-chip filtering
- External T/H
- Limited sampling rate
250MSPS 1GSPS
12 bits 16 bits
< 50 kSPS
+ High resolution
+ Low supplay current
+ Excelant noise rejection
- Low speed
76kSPS 250kSPS
> 16 bits
Pipeline
Sigma-Delta
(EA)
> 18 bits Integrating
10 bits 16 bits SAR
8 bits
SYSTEM
ARCHITECTURE
RESOLUTION
+ High throughtput rate
+ Low power consumption
+ Digital error correction and on-
chip self- calibration
- Required duty-cycle typical
- Required minimum clock
frequency
SPEED ADVANTAGE / DRAWBACKS
97
How to Save Power ?
shows how the power-down mode can be
entered by controlling the CS signal
The serial interface consists of the CS, SCLK, and SDATA lines
A normal conversion requires sixteen serial clock pulses for completion.
98
Texas Instruments - ADS7807
99
Analog Devices - AD7466
The AD7466, a micropower, 12-bit SAR-type ADC housed in a 6-lead SOT-23
package. It can be operated from 1.6 V to 3.6 V and is capable of throughput rates of
up to 200 kSPS.
The current consumption in power-down mode is typically 8 nA. The AD7466
consumes 0.9 mW max when operating at 3 V, and 0.3 mW max for 1.8 V
operation at 100 kSPS.