G 7728

Reg. No
Name ~

.
.

First Semester Branch-Electronics and Communication Engineering and Embedded System

Specialization-VLSI LMV lOl-ANALOG

INTEGRATED CIRCUIT DESIGN

Answer any five questions. Each question carries 4 marks.

1. What is subthreshold current in MOSFET? What are the applications of the subthreshold in" the small signal high frequency What are its effects in a current explain the features mirror? mirror. equivalent operation ?

2. List and explain the capacitors MOSFET. 3. 4. What is oxide encroachment? With a neat circuit diagram,

circuit model of

of a Wilson current

5. What is Operational 6.

Transconductance

Amplifier (OTA) ? Expain its applications. What are its advantages and applications?

What is a common mode feedback (CMFB) circuit?

7. With necessary graphs, show how the linearity of an CMOS op-amp can be improved with feedback. 8. An op-amp is designed so that the open loop gain is 1.5 x 105 10 % v/v. If the amplifier is to be used in a closed loop configuration with ~ :::;0.1 vlv, calculate the tolerance of the closed loop gain. (5 X,4 :::;20 marks)

Answer four questions. Each question carries 20 marks.

9. (a) Sketch to scale the output characteristics of an enhancement P-channel device ifVT:::; - 0.7 V and In:::; - 500 !-lAwhen VGS:::;- 5 V in saturation. Choose values ofVGs:::; - 1, - 2, - 3 and - 4. Assume that the channel modulation parameter is zero. (10 marks) (b) Obtain the low frequency model parameters gm' gmb' In for an N-channel transistor that has a doping concentrations NA:::; 1022,Nn:::; 1025,!-l"Cox:::; 90 !J.A/v2,W:::; 20 !-lm,L:::; 2 !-lm,Vgs:::; 1.1 V, Vth
:::;

0.8 V, Vns :::;Vetl' y:::; 0.5 V05, 'A:::;95 m.lv, by 0.5 V.

1 I:::;
2 \!I F

1.8 V, Vsb

:::;

0.5 V. Calculate

the new

value of 1'0if the Vns is increased

10. (a)

With neat constructional diagrams, describe the working of MOSFET when operated (i) in the linear region; (ii) at the onset of saturation region and (iii) beyond saturation region. (12 marks)

(b)

Derive the expressions for ID anli gm for a Pchannel ~OSFET considering the channel length modulation. (8 marks)

11. (a)

The following circuit is used to generate a reference voltage 6" VOL-l

VREF"

Calculate its value:

~ft' 1.. -

(b)

Using low frequency model, derive the expression for the voltage gain and input resistance of common source amplifier.

12. ,(a)

Draw a MOS diode circuit, its I-V characteristics and small signal model and explain its principle. With circuit diagrams, explain its application.

(b)

U sing high frequency model, derive the expressions for voltage gain and upper 3 dB cut-off frequency of a MOSFET.

13. (a)

For an op-amp model with three poles and no zero, prove that if the highest pole is ten times GB, then in order to achieve 60 phase margin, the second pole must be placed at least 2.2 times GB.

(b)

Use the null port concept to find the voltage transfer function of the non-inverting voltage amplifier shown in Fig. 2.

t; l
Or 14. (a) Sketch circuit configurations suitable for simulating the following op-amp characteristics (i) (ii) (iii) (iv) (b) Slew rate. Transient response. :-

ICMR.
Output voltage swing. (10 marks) (10 marks)

Derive the expression for the voltage gain of a differential pair using MOSFET?

15. With a neat circuit diagram, explain the perfcirmace of a low noise CMOS op-amp. Draw the noise model for the above. Or 16. (a) Explain the non-linearity of differential amplifier circuit?

(10 marks) [4 x 20

= 80 marks]

G 7729

First Semester Branch: Electronics and Communication Engineering Specialization-VSLI LMV l02-CMOS and Embedded System

DIGITAL INTEGRATED CIRCUITS

Answer any five questions. Each question carries 4 marks.

L Discuss double metal CMOS process design rules. 2. How are the basic gates realized with CMOS switches? 3. Draw the layout diagram for two-input NOR gate. 4. Draw the stick diagram and mask layout of a CMOS inverter. 5. Design CMOS gates for the following :-

Z=((AoBoC)

+D)

7. Design a 3 : 2 priority encoder defined by Z = A

. A1.
(5 x 4

8. Explain the working principle of carry look ahead adder? What are its merits and demerits?

= 20 marks)

Part B Answer any four questions. Each question carries 20 marks.

9. (a) Explain how the parasitic channel, which couples unrelated process is reduced.

nMOS transistor in an n-well

(10 marks)

(b) 10. (a)

What is latch up? How does a "dummy collector" prevent latch up?

(10 marks)

Or
Draw the layout for a pMOS transistor in a n-well process that has active, p-select, n-select, polysilicon, contact and metall marks. Include the well contact to VDD ? (14 marks) (b) Explain the difference between a polycide .and a salicide CMOS process. Which would have higher performance ? Why ? (6 marks)

Turn over

G 7729

11. Find the rising and falling propagation delays of an AND-OR-INVERT gate using Elmore delay model. Estimate the diffusion capacitance based on a stick diagram of the layout. Or 12. (a) Suppose a unit inverter with three units of input capaictance has unit drive: (i) (ii) (b) What is the drive of a 4X inverter? What is the drive of a 2-input NAND gate with 3 units of input capacitance? (10 marks) Sketch a 4 input NAND gate with transistor widths chosen to achieve equal rise and fall resistance as a unit inverter. Show why the logical effort is 6/3. (10 marks) 13. (a) Explain "set up time" and "hold time" in relation to a CMOS D register. If the clock is delayed to a register with regard to the data input, which of these parameters varies and how? (10 marks) (b) Prove that the PIN ratio that gives lowest average delay in a logic gate is the square root of the ratio that gives equal rise and fall delays. Or Consider a flip-flop built from a pair of transparent latches using non overlapping clocks. Express set up time, hold time, and clock-to-Q delay of the flip flop in terms ofthe latch timing parameters. (10 marks) Sketch the stick diagram for a two-input multiplexed latch, placing the two transmission gates side-by-side. (10 marks) The output of an adder feeds one input to a second adder; the ses:ond adder's other input comes directly from a primary input. Sketch the critical delay path througb this system of two adders. (10 marks) Design the stick diagram of a serial adder cell. Or Draw a block diagram of an array multiplier that uses booth encoding. Use adder-subtractor as a basic building block of the array. ' (b) Design a 4 : 1 multiplexer: (i) (ii) Using a combination of CMOS switches and logic gates. Using only CMOS logic gates. (10 marks)

Assess the efficiency of each implementation by counting the total number of switches used in each implementation. Which is more efficient? Why ? (10 marks) [4 x 20

= 80 marks]

Branch:

Electronics

and Communication

Engineering Systems

Specialisation LMV-I03

: VLSI and Embedded

ADVANCED

DIGITAL SYSTEM DESIGN

Answer any five questions. Each question carries 4 marks.

1. Draw a general model for a Mealy network using clocked D flip-flops. 2. Explain the fault coverage and system reliability.

3. Discuss the hazards in segmental networks. 4. With an example, explain testing of a combinational logic. 5. List the advantages of FPGA based design. 6. Show how a CPLD device can be programmed.

7. List and explain the reduction operators in verilog. 8. Write a verilog program to realise a full adder.

Answer four questions. Each question carries 20 marks.

9. (a) With a neat block diagram, explain synchronous digital system. Give the timing chart for system with rising edge devices. (19 marks) (b) Explain the steps involved in sensitised path based testing with an example. Or (10 marks)

(b) Check the circuit in fig. 1 for static hazards. If the circuit contains hazard, give the hazard free circuit.

11. With appropriate examples, distinguish: (i) (ii) (iii) (iv) Signal assignment versus Variable assignment statements. Transport and Initial delay. Concurrent and Sequential statements. Static and Dynamic hazards. (4 x 5 = 20 ma::ks)

12. Analyse the following circuit in fig 2 for static hazards. Redesign the circuit so that it becomes hazard free.

13. With necessary usingPLA: -

diagram, explain PLA structure.

Show the implementation

of the following

Fo =Im(O,1,4,6) F} F2

=Im(O,1,2,6)
=

I m (2,3,4,6,7) F3 = I m (2,3,5,6,7)

14. (a) Explain the architecture and characteristic features of Xilinx series FPGA. . (b) Compare and contrast PLD and CPLD. 15. Design and write verilog code for a divide-by-3 counter.

(10 marks) (10 marks) (20 marks)

Or
(20 marks) (4 x 20

= 80 marks)

G 7731

First Semester Branch-Electronics and Communication Engineering and Embedded Systems

Specialization-VLSI LMV lO4--INTRODUCTION

TO VLSI TECHNOLOGY AND DESIGN

Answer any five questions. Each carries 4 marks. 1. Explain the silicon oxidation process. 2. What are thin film circuits? Describe the fabrication of thin film resistor for hybrid circuits. 3. What are the differences between plasma etching and wet etching? Explain. 4. Describe the low pressure CVD. 5. What are the advantages of nwell CMOS technology ? 6. Explain the process oflatchup in a CMOS transistor.

7.

Draw the stick diagram and mask layout of a CMOS inverter.

Answer four questions. Each carries 20 marks. 9. (a) (b) What are photo resists? Describe their role in IC fabrication. With neat diagrams explain the process of ion implantation in detail. (10 marks) (10 marks)

Or
10. (a) Define a set of conditions to minimize the chance ofinverling the surface of an n-type substrate (containing a boron diffusion) when oxidising the wafer:

(b)

For selective oxidation, show how you might prevent lateral oxidation during oxide growth. (10 marks) Turn over

11. With neat diagram explain coherent and non-coherent illumination . compare MTF for different optical conditions.

of projection printers

and

12. (a) (b) Describe the photo etching process. How many masks are required to complete an IC ? Explain the function performed by each mask. (10 marks) 13. (a) Why the electrical properties ofMOS transistors are important from fabrication point of view ? (5 marks) (b) Why the stick diagrams are important in integrating various colour coding schemes. devices in microelectronics? Discuss

Or
14. (a) (b) 15. (a) With neat diagrams, explain twin tub CMOS process in detail? Explain BiCMOS transistor design rules. (10 marks) (10 marks)

Explain in detail, giving neat sketches; the fabrication of thin film resistors and circuits. (10 marks) (10 marks)

Or
16. (a) (b) Discuss the design rules used for powell CMOS process. What are data path logic cells? Give their merits, demerits and applications. (10 marks) (10 marks)

[4 x 20

= 80 marks]