Chapter 9 Analog to Digital Conversion

Analog-to-digital and digital-to-analog I/O concepts Analog refers to physical quantities that vary continuously instead of discretely. Physical phenomena typically involve analog signals. Examples include temperature, speed, position, pressure, voltage, altitude, etc. Microprocessors work with digital quantities (values taken from the discrete domain). For a digital system to interact with analog systems, conversion between analog and digital values is needed. Building blocks to perform the conversions are: (1) Digital to analog converters (DACs), (2) Analog to digital converters (ADCs). A digital to analog converter has a digital input that specifies an output whose value changes in steps. These step changes are in volts or amperes. The analog to digital converter has an input that can vary from a minimum to a maximum value of volts or amperes. The output is a digital number that represents the input value.

Transducers A device that converts a process variable (ex. Car speed) into an electrical signal or vice versa. Sensors (Input transducers): Potentiometer (position); strain gauge, piezoelectric device (force); thermistor, thermocouple (temperature); photoconductive cell, phototransistor (light); current transformer, SENSEFET (current); microphone (sound), etc. Actuators (Output transducers): solenoids, relays, speakers; darlington transistors, triacs, etc. Some common sensors

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Signal Conditioning Signal conditioning is sometimes necessary because raw sensor outputs are not always suitable for analog-to-digital conversion. Amplification : Op amps are preferred because of their performance characteristics Open Loop gain: several hundred thousand, input current ~0, output impedance ~0. Filtering: LPF

Concepts and terminology Definitions Offset: minimum value Span: maximum value minimum value o Some common spans: range of 0 V to 5 V: span = 5 V range of 12 V to 12 V: span = 24 V range of 4 mA to 20 mA: span = 16 mA Weight: The analog change corresponding to a change in a bit in the digital number. Step size: span / 2n (Typically, the digital representation is an unsigned n- bit integer) (n is the number of bits in the corresponding digital code. e.g. n=0 for a 1-bit number) Resolution: Same as step size. Weight of the LSB.

Example: Analog signal in range +5 to -5 volts, 8- bit ADC: Offset = 5 V Span = 10 V Step size = 10 / 256 = 39.1 mV Notice that the MSB has a weight of 5 V (= span/ 2), and the LSB has a weight of .0391 V Equations Analog number = (bn-1 21 + bn-2 22 + +b0 2n ) x stepsize + offset = (digital number x step size) + offset Digital number = (analog number offset)/ (step size) These equations hold true as long as the numbers are within the range. If the input of an A/D is below the minimum or above the maximum of the range, the corresponding digital value will be minimum or maximum, respectively. In practice, extreme input swing beyond the specified range may damage the device. Example: 6-bit D/A converter, analog output range :-2.5 to 5 volts. Calculate the analog output when the input is %010101 (decimal 21) Offset : -2.5 V Span: 7.5 V Step size: 0.1172 V Analog number = 21 x 0.1171 2.5 = -0.039 V

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Example: As an example the following table lists some values for -5 V to +5 V analog range to 8-bit digital conversion: Analog (V) Digital (hex) -5 00 -3.75 20 -2.5 40 -1.25 60 0 80 1.25 A0 2.5 C0 3.75 E0 5-0.0391=4.961 FF Digital-to-Analog Converters A DAC takes an n- bit digital input and output a corresponding analog voltage. DAC systems normally consist of three components: (a) A reference voltage, (b) The DAC itself, (c) An op amp for output buffering.

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Many digital-to-analog converters use R-2R ladder network. Inverted ladder type of network is shown in the figure below. The switches are analog switches controlled by digital signals. The output voltage (Vo) is proportional to the binary input. Each branch of the ladder network contributes current whose value is proportional to the bit weight of that branch. The amplifier circuit sums the current components to produce a voltage proportional to the binary input.

Interfacing DAC to microprocessor system DAC integrated circuits are available with different bit resolutions. In principle, any DAC can be interfaced to any microprocessor system. In practice, some combinations of DACs and microprocessors are easier than others and require much simpler hardware and software in the interface. Here, interfacing a 12-bit DAC to an 8-bit microprocessor will be considered. This will serve to show how to mate different bit resolutions with different size data buses. Also, the importance of double buffering will be illustrated.

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The figure given above shows an interface for a microprocessor operating in expanded multiplexed mode. The latches are used to convert a sequence of 2 bytes into one 12-bit word. To output a 12-bit word, the microprocessor writes the data in two steps. First, it puts the upper 4 bits on the lower nibble of the data bus. Then it selects the latch address. The address decoder decodes the address and drives the latch chip select input low. Also, the microprocessor drives the address line A0 low so that only the 4-bit latch accepts data from the data bus. Then the microprocessor repeats the sequence for the lower 8 bits except that it drives A0 high. The other purpose of the latches is to provide the double buffering. The updated latch data is not transferred to the DAC until the microprocessor drives the control line to latch in data to the buffer in the DAC. DAC does not change its output until L is driven low. Note that this is important when there is a change in the upper nibble. Analog-to-Digital Converters The function of ADCs is to quantize the analog voltage and then output the corresponding digital code value. As with the DAC conversion, a full- scale analog voltage will be divided into 2n quantization levels or steps for an n- bit digital coding scheme. Several techniques are used to do the conversion. Among them successive approximation which has a medium conversion speed (nominally 20 ms) is common in computer systems.

The ADC has a built in DAC. A sample and hold circuit stores an analog input. The ADC logic steps through a sequence of trial-and-error guessing to find the digital equivalent of the input. It begins the sequence by sending a digital signal that is at midrange to the DAC. The analog output Vout from the DAC is compared to the analog input Vin from the sample-and-hold circuit. Thus, the ADC determines whether the analog input is above, at or below half scale. It continues determining to which half of the next range selection the analog input belongs.

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Successive Approximation example

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68HC11 A/D Converter

The 68HC11 has a built-in A/D subsystem, but it does not have a D/A, although it can easily be interfaced to one. External D/A converter such as DAC0808 ( 8-bit D/A) can be used. 68HC11 uses an A/D which in turn uses a D/A to generate internal signals as part of the process to convert analog to digital. This is common to many types of A/Ds. 68HC11 supports 8 input ADC channels Channels are located on port E (Channel 0 on PE0, Channel 1 on PE1, etc.) In performing A/D conversions, 4 conversions are performed as a "block," each taking 32 cycles -- 128 cycles total Control registers: o OPTION ($ 1039): ADPU and CSEL bits o ADCTL ($ 1030): Control and status information o ADR1 - ADR4 ($ 1031 - $1034): Result registers

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More detailed description for conversion

DAC is replaced by a series of capacitors that are charged to the voltages that correspond to the weights of each bit During the sample mode, the capacitors are charged. This total charge is proportional to the input analog signal. For the duration of the conversion process, this total charge remains conserved. The A/D switches to the hold mode and then to the approximation mode. The approximation mode is a sequence of successive approximation steps that switches different capacitors to modify the input voltage to the comparator. The result of each step sets or resets a corresponding bit in a successive approximation register (SAR). VRH is normally set to the signal maximum (analog value for digital data $FF) and VRL is set to minimum (analog value of $00). However, VRH should not be higher than 6 V and VRL should not be lower than ground, and VRH - VRL should be greater than 2.5 V. 8-bit outputs from four successive conversions are placed into analog data registers ADR1ADR4.

68HC11 A/D related Registers The MCU on the EVB has an 8-bit register at location $1030 that is the A/Ds control and status register (ADCTL). Bits 0-5 are the control bits and may be read from or written to. Bit 6 is not used and is always read as logic 0. Bit 7 is a status bit and can only be read. Data written to this bit is ignored.

Conversion Complete Flag (CCF) Bit 7: Bit 7 is a read-only status flag. It is set automatically by the MCU after the A/D completes the fourth conversion and the results are stored in the result registers. This bit is cleared each time the ADCTL register is written to. Also, any time the ADCTL register is written to, a new conversion sequence begins immediately. Note that a conversion operation begins immediately after writing to the ADCTL register. Also, by writing to the ADCTL

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register, the programmer stops any conversion in progress and begins a new one. If the MCU is programmed for the continuous scan mode (bit 5 = logic 1), then the CCF bit may remain set and the result registers are updated automatically. Scan Control (SCAN) Bit 5: This bit is also known as continuous scan control. It allows the programmer to choose between a single conversion sequence and a continuous sequence. When the SCAN bit is 0, the A/D is in the single conversion mode, thereby performing four conversions and filling the four result registers. No more conversions are performed at this time. When this bit is 1, the A/D is in its continuous conversion mode. Conversions are performed in a round-robin fashion and the result registers are continuously updated. Multiple/Single Channel Control (MULT) Bit 4: Bit 4 of the ADCTL register is used to select between a single-channel conversion or a four-channel conversion. When this bit is 0, single-channel conversion is selected. The A/D selects a single channel (according to the binary pattern in the CDCC-CB-CA bits) and performs four consecutive conversions placing the digital data into the result registers. The first conversion goes to ADR1, the second into ADR2, and so forth. When bit 4 is set, the A/D performs a single conversion on each channel in the group selected by the CD and CC bits (CB and CA are ignored). Tables given below show which group is selected and which register stores the data for each channel. Binary patterns in the CD-CA bits for 8 to 11 are reserved and 12 to 15 are for factory testing and are not shown in this table. Channel Select Bits (CD, CC, CB, CA) Bits 3-0: These four bits select the channel or channels to be used for the A/D conversion. Channel selection when MULT (Bit 4) = 0 CC CB CA Port E 0 0 0 PE 0 0 0 1 PE 1 0 1 0 PE 2 0 1 1 PE 3 1 0 0 PE 4 1 0 1 PE 5 1 1 0 PE 6 1 1 1 PE 7 Channel selection when MULT (Bit 4) = 1 CA ADR1 ADR2 ADR3 x PE0 PE1 PE2 x PE4 PE5 PE6

CD 0 0 0 0 0 0 0 0

CD 0 0

CC 0 1

CB x x

ADR4 PE3 PE7

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Timing Diagram for 4 conversions

Initialization The software initialization procedure for the A/D includes enabling the charge pump and defining the conversion clock source.A charge pump is a system of switching capacitors to redistribute a stored charge. The A/D power-up (ADPU) bit in the system configuration option register (OPTION) is set to charge pump (ADPU = 1 means A/D charge pump is powered up). Then, the MCU should wait at least 100sec. It is only necessary to enable it once after a power-on reset. The successive approximation circuit can use the system clock E, if it is greater than 750 kHz. This low-frequency limit is necessary to minimize charge leakage. The software selects E as the clock source by clearing the clock select bit (CSEL) in OPTION register residing at $1039. To select an internal RC oscillator (around 2 MHz), the software should set the CSEL bit. 7 ADPU 6 CSEL 5 IRQE 4 3 2 DLY CME 0 Option Register, $1039 1 CR1 0 CR0

Example: Initialization subroutine for A/D * Subroutine STARTAD * Powers up A/D. Must be run before using it after reset or a power-down sequence. * In this case, uses E clock as source. No calling or return registers except CCR affected STARTAD PSHX LDX #REGBAS BSET OPTION,X $80 BCLR OPTION,X $40 JSR DLY100 PULX RTS ; preserve IX ; point to registers ; ADPU = 1 to power up ; CSEL = 0 to select E clock ; wait 100 us ; restore IX ; return

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Example: Subroutine for single channel operation * Subroutine INAD * I/O handler routine for analog input using continuous scan. Calling program must execute * this subroutine after subroutine STARTAD and before reading the result. * Calling registers * IX = register block address * ACCA = channel number from 0 to 7 * Return registers * ACCA = analog result INAD ANDA #$07 * ORAA #$20 STAA ADCTL,X * * wait for first conversion done INAD1 BRCLR ADCTL,X $80 INAD1 * LDAA ADR4,X RTS ; ensure that bits 3 to 7 clear ; note that others select channel ; SCAN=1, MULT=0 ; start conversion ; also clears CCF

; CCF set at this point ; read any result register ;in this case, the most recent ; return

Example: You are required to design a M68HC11 based system, which continously monitors eight analog voltages v0 to v7 (all within 0-5V range) and displays the index of the channel with the smallest analog voltage at a single digit commonanode seven-segment display. a) Give a simple connection diagram of the system assuming that the display is connected to port B of the M68HC11, which operates in the single-chip micro-controller mode. b) Write a complete program using M68HC11 assembly language with labels to perform the required task. Write explanotary comments and use a reasonable number of instructions. Solution: PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 M68HC11 +5v
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 a b c d e f g Anode

V7
. . .

V0

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REGBASE EQU $1000 PORTB EQU $04 ADCTL EQU $30 ADR1 EQU $31 ADR2 EQU $32 ADR3 EQU $33 ADR4 EQU $34 OPTION EQU $39 ORG $5000 LDS #STACKBASE LDX #REGBASE BSET OPTION,X $80 BCLR OPTION,X $40 JSR DLY100 START LDAB #$FF CLR MININDEX CLRA CONVERT STAA ADCTL,X WAIT BRCLR ADCTL,X $80 WAIT CMPB ADR4,X BCS SKIP LDAB ADR4,X STAA MININDEX SKIP INCA CMPA #$08 BNE CONVERT LDAA MININDEX STAA PORTB,X BRA START ; holds channel index ; single scan, single channel, channel no in AccA ; also clears CCF and starts conversion ; wait until CCF is set

; ADPU = 1 to power up ; CSEL = 0 to select E clock ; wait 100 us assuming that the subroutine exists

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