J. Cent. South Univ. Technol. (2011) 18: 20362044 DOI: 10.

1007/s1177101109394

Design of 512-bit logic process-based single poly EEPROM IP

JIN Li-yan(), JANG Ji-Hye, YU Yi-ning(), HA Pan-Bong, KIM Young-Hee Department of Electronic Engineering, Changwon National University, Changwon 641-773, Korea Central South University Press and Springer-Verlag Berlin Heidelberg 2011
Abstract: A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 m2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DCDC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18 m logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 W, respectively, and the EEPROM size is 0.12 mm2. Key words: single poly EEPROM cell; Fowler-Nordheim tunneling; logic process; radio frequency identification; small area

1 Introduction
Radio frequency identification (RFID) is a technology that provides various communication services between objects by collecting, storing and revising information based on RFID tags installed or attached to them. Currently, passive RFID tags are more widely used than their active counterparts because they have advantages such as low cost and small size. Therefore, more efforts have been devoted to the development of the passive tags [1]. The required memory capacity of an EEPROM used for a tag chip is 512 bits or more including a reserved memory space. The capacities of recently published EEPROM IPs are in the range of 224 bit to 64 kbit [15]. To reduce the cost of a tag chip, a single poly EEPROM cell based on logic process rather than EEPROM process is required [2]. For the EEPROM cell, the cell size should be small and the cell uses the Fowler-Nordheim (FN) tunneling scheme by which the current dissipation of a DCDC converter is small in writing. The single poly EEPROM does not require an additional mask layer. In addition, the process turn-around time (TAT) is short and the manufacturing cost is low [69]. There are two methods to write with the FN tunneling scheme for a single poly EEPROM cell: using a high voltage VPP (Boosted voltage) [10] and using a back-gate bias voltage VNN (Negative voltage) [2]. Although high-voltage (HV) devices are required in designing with a high voltage VPP, they are not required

with a back-gate bias voltage VNN. Instead, deep N-wells (DNWs) are required to prevent the well junction from being turned on when a negative voltage is applied. Also, there is a disadvantage that the more isolated the DNWs and N-wells (NWs) are, the bigger a cell size is. When an EEPROM IP used for a RFID tag chip is designed independently, an EEPROM and an analog block need their own reference voltage generators. Thus, the size of the tag chip grows bigger and the power consumption increases in write mode. In this work, a method was established to reduce the size of a single poly EEPROM such that a cell array of 512 bits shares the DNW. Also, methods to increase the recognition distance of an RFID tag chip in write mode and to reduce a leakage current when over-erased were established. In addition, a design technique implementing a reference voltage generator of a DCDC converter with a resistive divider was introduced. Furthermore, schemes to secure the operation of the proposed cell with 3.3 V devices and the reliability of the used devices were also described by proposing an EEPROM core circuit (a control gate driving circuit and a tunnel gate driving circuit) and a DCDC converter (VPP, VNN and VNNL (=VNN/2)). The 512-bit EEPROM IP was designed with Towers 0.18 m logic process.

2 Circuit design
The capacities and IP sizes of recently published EEPROM IPs are compared in Table 1. It is required to

Foundation item: Project(10039239) supported by the Industrial Strategic Technology Development Program Funded by the Ministry of Knowledge Economy, Korea Received date: 20110426; Accepted date: 20111010 Corresponding author: KIM Young-Hee, Professor, PhD; Tel: +82552851023; E-mail: youngkim@changwon.ac.kr

J. Cent. South Univ. Technol. (2011) 18: 20362044 Table 1 Comparison of EEPROM capacities and IP sizes Memory Memory Reference Memory Cell No. process size/m2 capacity/bit IP size/mm2 [1] [2] [7] [8] [9] 0.25 m EEPROM 0.18 m Logic 0.18 m EEPROM 0.35 m EEPROM 0.35 m EEPROM 65 512 64 000 640 224 2 000 0.6 0.216

2037 Table 2 Bias voltage conditions of c-flash memory cell for different operation modes Terminal VDD VSS VCG VTG VC_DNW VT_DNW NW WL BL Program 0 0 4.75 V 4.75 V 4.8 V 0 0 0 Erase 0 0 4.75 V 4.75 V 0 4.8 V 0 0 Read 1.8 V 0 SWEEP 0 MAX_SWEEP 0 1.8 V 3V Sensing

have a single ploy EEPROM using the FN tunneling scheme for the effect of the reduced size and cost. A circuit of a c-flash cell and a process cross-section for a single ploy EEPROM using the FN tunneling scheme are shown in Fig.1 [2]. As shown in Fig.1(a), a c-flash cell circuit consists of a control gate (CG) capacitor (C1), a tunnel gate (TG) capacitor (C2), a CMOS inverter (MP1 and MN1) and an NMOS switch (MN2). As shown in Fig.1(b), C1 and C2 must be formed to two isolated deep N-wells (C_DNW and T_DNW) and a PMOS transistor MP1 in the NW (N-well). Thus, the more isolated the N-wells, the bigger the cell size is. The size of a c-flash cell with the 0.18 m logic process is 65 m2 [2]. Table 2 shows the bias voltage conditions of a c-flash memory cell for different operation modes. Bias voltages of CG and TG are 4.75 V and +4.75 V in the

Fig.1 Schematic maps of single EEPROM using FN tunneling scheme: (a) A circuit of c-flash cell; (b) A process cross-section

erase mode and +4.75 V and 4.75 V in the program mode. The output of the inverter is high when electrons are injected to the floating gate, and it is low when electrons are ejected from the floating gate. In the read mode, the inverter output voltage of the cell selected by word-line (WL) cell is transferred to BL. As shown in Fig.2(a), a single poly EEPROM cell consists of a CG capacitor (C1), a TG capacitor (C2), a sense transistor (MN1) and a select transistor (MN2) to reduce the off-leakage current when over-erased. As shown in Fig.2(b), the cell size is minimized since a cell array of 512 bits shares the deep N-well and so the space equivalent to the DNW space of at least 5 m is removed. The size of an EEPROM cell using the 0.18 m process is 4.71 m 8.76 m (41.26 m2) and the coupling ratio is 0.927. The cell size of the newly proposed EEPROM is 37% smaller than the conventional cell size. Figure 3 shows the EEPROM cell array having 32 rows and 16 columns. Table 3 lists the bias voltage conditions of a single poly EEPROM cell for different operation modes. In the erase mode, electrons of the floating gate are ejected by the Fowler-Nordheim (FN) tunneling with the CG and the TG of the selected cell applied with 4.75 V and +4.75 V, respectively. And in the program mode, electrons of the floating gate are ejected by the same FN tunneling with the CG and the TG of the selected cell applied with +4.75 V and 4.75 V, respectively. In the read mode, the erased cell outputs 0 V on the bit line (BL) while the programmed cell outputs a voltage of VDD. Major specifications of the designed 512-bit EEPROM IP using the proposed EEPROM cell in Fig.2 are listed in Table 4. The memory is based on the Towers 0.18 m logic CMOS process and uses dual power supply voltage: VDD (1.2 V) and VDDP (2.2 V). There are four operation modes: program, erase, read and reset mode. The clock frequency of the tag chip is 3.846 MHz. The write time is 1.2 ms.

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Fig.2 Schematic maps of proposed single poly EEPROM cell: (a) A circuit; (b) A process cross-section; (c) A layout plot

Fig.3 Cell array circuit with 32 rows and 16 columns

Figure 4 shows a block diagram of the designed 512 bit EEPROM. It consists of a cell array (32 rows 16 columns), a row decoder, a control logic to generate control signals at different operation modes, a row driver

supplying voltages to any WL and CG selected by the address bus A[4:0], a bit line sense amplifier (BL S/A) sensing the read-out data, a TG driver and a DCDC converter to provide high voltages (VPP, VNN, and VNNL)

J. Cent. South Univ. Technol. (2011) 18: 20362044 Table 3 Bias voltage conditions of single poly cell at different operation modes Erase mode Signal Selected Not selected cell cell CG TG WL BL DNW 4.75 V 4.75 V 0V Floating 4.75 V 0V 4.75 V 0V Floating 4.75 V DIN=1 4.75 V 4.75 V 0V Floating 4.75 V Program mode Selected cell DIN=0 4.75 V 0V 0V Floating 4.75 V Not selected cell DIN=1 0V 4.75 V 0V Floating 4.75 V DIN=0 0V 0V 0V Floating 4.75 V DIN=1 1.2 V 0V 1.2 V 1.2 V 1.2 V Read mode Selected cell DIN=0 1.2 V 0V 1.2 V 0V 1.2 V

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Not selected cell DIN=1 0V 0V 0V 1.2 V DIN=0 0V 0V 0V 1.2 V

Fig.4 Block diagram of a designed 512-bit EEPROM Table 4 Major specifications of 512-bit EEPROM Item Process EEPROM cell array Cell type VDD VDDP Operating mode Clock frequency Write time Main feature Towers 0.18 m logic process 32 rows 16 columns Single poly EEPROM cell 1.2 V 2.2 V Erase/program/read/reset 3.846 MHz 1.2 ms

necessary for EEPROM programming. The interface signals are control signals (RSTb, READ, ERS and PGM), the address bus A[4:0], the input data DIN[15:0] and the output data DOUT[15:0]. Read and write functions are performed word by word. Figure 5(a) shows the timing diagram in the erase mode of the designed EEPROM. If ERASE is activated to be high after the address to erase is applied at first, a word of data from the selected cells is erased. Figure 5(b) shows the timing diagram in the program mode of the designed EEPROM. Erasing should be performed before

programming. If PROGRAM is activated to be high after the address to program and a word of data DIN[15:0] are applied at first, a word of data DIN[15:0] is programmed into the address. tERS (erase time) and tPGM (program time) are all set to 1.2 ms to consider the settling time of the DCDC converter. The timing diagram in the read mode of the EEPROM memory is shown in Fig.5(c). If READ is activated to be high after the address to read out from is applied at first, a word of data from the selected cells is outputted on the DOUT port at tAC (access time). Towers 0.18 m logic CMOS process requires that the devices of 3.3 V are limited within 5.5 V in the write mode to secure the reliability of 1 000 erase and program cycles as well as ten years of data retention. To meet the above conditions, control gate (CG) and tunnel gate (TG) driving circuit are designed, as shown in Fig.6. To have a switching voltage under 4.75 V, the CG driving circuit uses three stages of level translators: VDDVNNL_CG, CG_HVVNNL_CG, and CG_HVCG_LV. Table 5 gives the output voltages of switching powers according to the operation modes. It can be seen that switching voltages of voltage level translators are all under 4.75 V. In

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Fig.5 Timing diagrams of designed EEPROM in different modes: (a) Erase mode; (b) Program mode; (c) Read mode

Fig.6 Schematic diagram of core driving circuit: (a) CG driving circuit; (b) TG driving circuit

J. Cent. South Univ. Technol. (2011) 18: 20362044 Table 5 Output voltages of switching powers according to operation modes Mode CG_HV CG_LV TG_HV TG_LV VNNL_CG VNNL_TG Reset VDD 0V VDD 0V 0V 0V Read VDD 0V VDD 0V 0V 0V Program 4.75 V 0V 0V 4.75 V 0V 1.58 V Erase 0V 4.75 V 4.75 V 0V 1.58 V 0V

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addition, since the TG driving circuit uses three stages of level translators like the CG driving circuit, it is designed that the maximum voltage to be applied to the devices of 3.3 V is also under 4.75 V. Table 6 compares the power consumptions of band-gap reference voltage generators. The current dissipation of the reference voltage generator supplying reference voltages in writing is an order of several tens A as listed in Table 6. The analog block supplies the logic voltage VDD. Although VDD is used as the reference voltage, if its variation is small in the case of an EEPROM of a tag chip, the output voltage of DCDC converter can be stable. Thus, the layout size can be smaller because the reference voltage generator can be removed. Figure 7 shows the distribution of output voltages of a VDD voltage regulator with Towers 0.18 m logic process. The average voltage of V DD is
Table 6 Comparison of power consumptions of reference voltage generators Reference No. [11] [12] [13] [14] [15] Process 0.6 m CMOS 0.18 m CMOS 0.5 m CMOS 0.6 m CMOS 0.35 m CMOS Reference voltage/V 1.142 0.75 0.631 0.309 0.75 Dissipating current/A 23 10.1 10 9.7 4.5

1.181 5 V and the three-sigma (3) limit is 50.42 mV. These values are beside the question as the reference voltage of the DCDC converter. Thus, a voltage divider circuit is proposed using a resistive divider for the DCDC converter in this work. The current dissipation of the voltage divider is 1 A, which means a large reduction. Figure 8 shows the block diagram of the DCDC converter using a resistive divider. It consists of a reference voltage divider, VPP (boosted voltage) generation circuit and VNN (negative voltage) generation circuit. The reference voltage divider supplies VREF_VPP and VREF_VNN. VPP and VNN are generated with 5VREF_VPP and 13.57VREF_VNN by a negative feedback. VNNL is generated with VNN/2 by the VNN generation circuit. In Fig.9, a NMOS switch MN_OFF is used to reduce the power consumption since it is turned on in the write mode and shut down in the rest.

Fig.8 Block diagram of DCDC converter

Fig.9 Reference voltage divider circuit using resistors

Fig.7 Distribution of output voltages (VDD) of voltage regulator

Voltage generation circuits for VPP (+4.75 V), VNN (4.75 V) and VNNL (=VNN/2) in the write mode are shown in Figs.10 and 11. The VPP generation circuit consists of two stages of cross-coupled charge pumps, a control logic, a ring oscillator and a VPP level detector. The VPP level detector compares VPP/5 with VREF_VPP. VPP goes up by a positive pumping since the output signal of the VPP level detector, VPP_OSC_ENb, is low when VPP/5 is lower than VREF_VPP. VPP is kept to the target voltage of 4.75 V since VPP_OSC_ENb is high and as a result, the charge pumping stops from a negative feedback when VPP/5 is greater than VREF_VPP. Figure 11 shows a negative charge pump circuit for

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Fig.10 Block diagram of VPP generation circuit

Fig.11 Block diagram of negative voltage generation circuit

VNN and VNNL using six stages of Dickson charge pumps. VNN is kept to 4.75 V by a negative feedback and VNNL supplies VNN/2. The layout image of the designed 512 bit EEPROM IP using Towers 0.18 m logic process is shown in Fig.12 and the layout size is 326.675 m 367.27 m (=0.12 mm2).

3 Simulation results
Figure 13 shows the simulation results for the control signals of a cell in the erase mode and in the program mode. It can be seen that the voltages of the selected CG and the non-selected CG are 4.75 V and +4.75 V, and the voltage of TG is +4.75 V in the erase mode. Also, it can be seen that the voltages of the selected CG and TG to be programmed are +4.75 V and

Fig.12 Layout image of designed 512 bit EEPROM IP

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Fig.14 Simulation result for control signals of EEPROM IP in read mode Table 7 Simulation results of active currents and power dissipations for different operation modes Signal Fig.13 Simulation results for control signals of cell in writing: (a) Erase mode; (b) Program mode VDD VDDP Total Operating current/A Read Program 9.85 0 8.38 6.86 Erase 8.41 6.36 Power dissipation/W Read Program Erase 11.82 0 11.82 10.06 15.09 25.15 10.09 13.99 24.08

4.75 V, and the voltages of the non-selected CG and TG not to be programmed are all 0 V in the program mode. It is confirmed that the results are consistent with the values in Table 3. Figure 14 shows the timing diagram for the control signals in the read mode. If READ signal enters in the read mode, WL is activated and a cell datum is transferred to BL immediately, and then the BL datum is sensed by BL S/A and outputted to DOUT if SAENb signal is activated low. Table 7 shows the simulation results for active currents and power dissipations. The power dissipation under the typical condition is 11.82 W in the read mode, 25.15 W in the program mode and 24.08 W in the erase mode, respectively.

4 Conclusions
1) A 512 bit EEPROM IP used for a passive RFID tag chip is designed. A single poly EEPROM cell is proposed by the 0.18 m process-based FN tunneling scheme. Since the proposed cell shares the deep N-well of a cell array, the cell size is 4.71 m 8.76 m, 37% smaller than the conventional cell. 2) To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit (a control gate driving circuit and a tunnel gate driving circuit) and a DCDC converter are proposed. 3) A design technique implementing a reference

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voltage generator of the DCDC converter with a resistive divider is proposed. The technique uses a stable VDD from the analog block to reduce the power dissipation of the reference voltage generator and the size of the EEPROM IP. 4) The 512 bit EEPROM IP is designed with Towers 0.18 m logic process. The layout size is 326.675 m 367.27 m. It is confirmed by the computer simulation that the power dissipation is 11.82 W in read mode, 25.15 W in the program mode, and 24.08 W in the erase mode, respectively. A test chip is in the making with Towers 0.18 m logic process.

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