B.E/B.

TECH DEGREE EXAMINATION,NOV/DEC 2013 Fifth Semester (Regulation 2011) UEC11501 MICROPROCESSORS AND ITS APPLICATIONS (Electronics and Communication Engineering) ANSWER-KEY PREPARED BY: Ms.A.Kirthika,Assistant Professor/ECE __________________________________________________________________ Part-A 1. Draw the pin out diagram of 8085 Microprocessor.(2)

2. Distinguish I/O Mapped I/O and Memory Mapped I/O. (2) (Any 4 points-each point mark)
SL: NO Memory Mapped I/O 1 16-bit device address 2 Data transfer between any generalpurpose register and I/O port. The memory map (64K) is shared between I/O device and system memory. More hardware is required to decode16-bit address Peripheral I/O 8-bit device address Data is transfer only between accumulator and I.O port The I/O map is independent of the memory map; 256 input device and 256 output device can be connected Less hardware is required to decode 8-bit address

3 4

5 6

Arithmetic or logic operation can be Arithmetic or logical operation cannot be directly performed with I/O data directly performed with I/O data Memory related instructions are used. Eg. LDA,MOV,STA and so on I/O instructions are used Eg. IN, OUT

3. Write the command word format of 8255. (2)

4. What is the specific advantage of 8254 timer over software timer? (2) When 8254 is used as a timing and delay generation peripheral, the microprocessor becomes free from tasks related to the counting process and can execute the programs in memory, while the timer device may perform the counting tasks. This minimizes the software overhead on the microprocessor. 5. What are the types of Interrupts of 8086 Microprocessor? (2) Non-maskable interrupt (TRAP,NMI,divide by zero) (1) Maskable interrupt (INTR) (1) (or) Type 1 interrupt Type 2 interrupt

Type 3 interrupt Type 4 interrupt

6. What are the functionalities of bus interface unit in 8086 microprocessor? (2) The bus interface unit contains the circuit for physical address calculations and a predecoding instruction byte queue (6 bytes long).The bus interface unit is responsible for establishing communications with external devices and peripherals including memory via the bus. 7. What are the data types supported by 80386 processor? (2) (Any 4 data types from below) Bit Bit String Bit Field String Character Signed Byte Unsigned Byte Integer word Long Integer Unsigned Integer word Unsigned Long Integer Signed Quad word Unsigned Quad Word Offset Pointer BCD Packed BCD 8. What do you mean by Real address mode of 80386? (2) After reset, the 80386 starts from memory location FFFFFFF0H under the real address mode. In the real mode, 80386 works as a fast 8086 with 32-bit registers and data types. In real mode, the default operand size is 16 bit but 32- bit operands and addressing modes may be used with the help of override prefixes. The segment size in real mode is 64k, hence the 32-bit effective addressing must be less than 0000FFFFFH. The real mode initializes the 80386 and prepares it for protected mode.

9. What are the sensors used for Electronic Weighing Bridge design? (2) Weighbridge sensors, Position sensors, Level sensors 10. Draw the block diagram of stepper motor control system? (2)

8085/ 8086

8255

__________________________________________________________________ Part-B 11.a) Explain the Instructions set of 8085 with example. (16) Definition: (1) An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. Types (2) These instructions can be classified into the following five functional categories: data transfer (copy) operations, arithmetic operations, logical operations, branching operations, and machine-control operations. Data Transfer (Copy) Operations: (3) This group of instructions copy data from a location called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. The various types of data transfer (copy) are listed below MOV Rd,Rs MVI Rd,data LDA 16-bit address LXI 16-bit adress Arithmetic Operations: (3) These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement. Addition - Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the contents of the accumulator and the sum is stored in the accumulator. Subtraction - Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from the contents of the accumulator and the results stored in the accumulator.

Increment/Decrement - The 8-bit contents of a register or a memory location can be incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such as BC) can be incremented or decrement by 1. Logical Operations: (2) These instructions perform various logical operations with the contents of the accumulator. AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator. The results are stored in the accumulator. Complement - The contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s are replaced by 0s. Branching Operations(2) This group of instructions alters the sequence of program execution either conditionally or unconditionally. Jump - Conditional jumps are an important aspect of the decision-making process in the programming. These instructions test for a certain conditions (e.g., Zero or Carry flag) and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump. Call, Return, and Restart - These instructions change the sequence of a program either by calling a subroutine or returning from a subroutine. The conditional Call and Return instructions also can test condition flags. Machine Control Operations:(2) These instructions control machine functions such as Halt, Interrupt, or do nothing. NOP HLT 11.b) Explain the different addressing modes of 8085 with example. (16) The various formats for specifying operands are called the ADDRESSING MODES. (1) Types (3) a. Immediate addressing. b. Register addressing. c. Direct addressing. d. Indirect addressing. a. Immediate Addressing: (3) In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction. EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H. b. Direct Addressing: (3) In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory. EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD 3000H c. Register Addressing: (3)

In register addressing mode, the instruction specifies the name of the register in which the data is available. EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C. d. Indirect Addressing: (3) In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair. EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B.

12.a) Explain about 8279 keyboard and display controller with neat diagram. (16) The 8279 is specially developed for interfacing keyboard and display devices to 8085 microprocessor based system. The important features of 8279 are, (1) o Simultaneous keyboard and display operations. o Scanned keyboard mode. o Scanned sensor mode. o 8-character keyboard FIFO. o 1 6-character display. o Right or left entry 1 6-byte display RAM. o Programmable scan timing. Block Diagram: (8)

The four major sections of 8279 are keyboard, scan, display and CPU interface. (1)

Keyboard section: (1.5) The keyboard section consists of eight return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix. It has two additional input: shift and control/strobe. The keys are automatically debounced. The two operating modes of keyboard section are 2-key lockout and N-key rollover. In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized. In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also has an 8 x 8 FIFO (First in First Out) RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is, In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor. Display section: (1.5) The display section has eight output lines divided into two groups A0-A3 and B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display. The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs. The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD (low) line. The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM. Scan section: (1.5) The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output. The scan lines are common for keyboard and display. The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF. CPU interface section: (1.5) The CPU interface section takes care of data transfer between 8279 and the processor.

This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU. It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of 8279. The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279. It has an interrupt request line IRQ, for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler. The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

12.b) Briefly explain about the Interfacing schemes of ADC with neat diagram. (16) Description: (2) PIO 8255 is used for interfacing the analog to digital converters with microprocessor. The analog to digital converters is treated as an input device by the microprocessor, that sends an initialising signal to the ADC to start the analogy to digital data conversation process. The start of conversation signal is a pulse of a specific duration. Block diagram of ADC 0808/0809: (2)

Pin Diagram of ADC 0808/0809: (2)

Timing Diagram of ADC 0808/0809: (2)

ALP to interface ADC with 8085/8086 (3) MOV AL, 98h ;initialise 8255 as OUT CWR, AL ;discussed above. MOV AL, 02h ;Select I/P 2 as analog OUT Port B, AL ;input. MOV AL, 00h ;Give start of conversion OUT Port C, AL ; pulse to the ADC MOV AL, 01h OUT Port C, AL MOV AL, 00h OUT Port C, AL

WAIT: IN AL, Port C ;Check for EOC by RCR ; reading port C upper and JNC WAIT ;rotating through carry. IN AL, Port A ;If EOC, read digital equivalent ;in AL HLT ;Stop.

Interfacing 0808 with 8086 (5) 13.a) Write in detail about Branch instructions of 8086 with example. (16) Branch Instruction:(1) The control of transfer instruction transfer the flow of execution of the program to new address specified in the instruction directly or indirectly Two types:(2) Unconditional branch instructions Conditional branch instructions Unconditional branch instruction: (5) In this case,execution control is transferred to the specified location independent of any condition Instructions: CALL(unconditional call) RET(Return) INT N(Interrupt type N) JMP(Jump) LOOP(Loop unconditionally) Conditional branch instruction: (8) In this case, execution control is transferred to the specified location dependent of any condition

13.b) Explain in detail about the architecture of 8086 with neat diagram. (16) Features: (1) It is 16 bit processor. So that it has 16 bit ALU, 16 bit registers and internal data bus and 16 bit external data bus. It makes faster processing. 8086 has 20 bit address lines to access memory. Hence it can access 2^20 = 1 MB memory location. There are two units in 8086, they are (1) Bus Interface unit (BIU) Execution Unit(EU) 8086 has a 16-bit flags register. Nine of these condition code flags are active, and indicate the current state of the processor: Carry flag (CF), Parity flag(PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF), and Overflow flag (OF). 8086 internal architecture:(8)

Block diagram of 8086 (8) Description of block diagram :(6) Bus Interface unit (BIU) This unit handles all transfer of data and addresses on the buses for the EU (execution unit). This unit sends out addresses, fetches instructions from memory, reads data from ports and memory and writes data to ports and memory. Different Parts of BIU: a.Segment Register b.Instruction Pointer c.The Queue Segment Register: BIU contains four 16-bit segment registers as follows: Code segment (CS) register Stack segment (SS) register Extra segment (ES) register

Data segment (DS) register Function of Segment Register: In 8086 complete 1MB memory is divided into 16 logical segments. Each segment thus contains 64 KB of memory. While addressing any location in the memory bank, the Physical address is calculated from two parts, the first part is Segment address, and the second is Offset. Memory Address generation: Generation of physical address: Segment address- 1005H Offset address - 5555H Segment address-1005H- 0001 0000 0000 0101 Shifted by 4-bit positions-0001 0000 0000 0101 0000 + Offset address 0101 0101 0101 0101 Physical address -0001 0101 0101 1010 0101 1 5 5 A 5 Instruction Pointer: It is 16-bit register, which identifies the location of the next word of instruction code that is to be fetched in the current code segment. The Queue: The last section of BIU is the FIFO group of registers called a queue. It is basically a group of registers. This arrangement makes possible for the BIU to fetch the instruction byte while EU is decoding an instruction or executing an instruction which does not require use of buses. 14.a) Write about the addressing modes of 80386 with example. (16) The 80386 supports overall eleven addressing modes to facilitate efficient execution of higher level language programs. Types of addressing modes of 80386 (2) Scaled Indexed Mode Based Scaled Indexed Mode Based Scaled Indexed Mode with Displacement register operand mode immediate operand mode direct mode register mode based mode indexed mode

based indexed mode with displacement The different scaled modes are as follows. Scaled Indexed Mode: (2) Contents of an index register are multiplied by a scale factor that may be added further to get the operand offset. Eg: Mov EBX, LIST [ESI*2] Based Scaled Indexed Mode: (2) Contents of an index register are multiplied by a scale factor and then added to base register to obtain the offset. Eg: Mov EBX, [EDX*4][ECX] Based Scaled Indexed Mode with Displacement: (2) The Contents of an index register are multiplied by a scaling factor and the result is added to a base register and a displacement to get the offset of an operand. Eg: Mov EBX, [ESI*2][EBX + 0800] Register operand mode: (1) Data is provided through the registers. Eg: MOV Rd, Rs Immediate Operand mode: (1) Data is present in the instruction. Load the immediate data to the destination provided Eg: MVI R, data Direct mode: (1) Offset is part of instruction either as 8 or 16 bit immediate operand Register mode: (1) Operand is stored in any of the general purpose registers or in SI,DI,BX or BP Based mode: (1) Offset is obtained by adding a displacement Indexed mode: (1) Offset is obtained by adding a displacement with the contents of index registers Based Indexed mode: (1) Operand is stored at a location whose address is calculated by adding the contents of any of the base registers with contents of any of the index registers. Based indexed mode with Displacement: (1) Offset is obtained by adding a 8 or 16 bit immediate displacement with contents of any of the base registers with contents of any of the index registers. 14.b) Explain about segmentation and paging concepts in 80386. (16) The paging unit operates under the control of segmentation unit. The paging unit if enabled converts linear addresses into physical address, in protected mode. Segmentation: Descriptor tables: (1) Three types of the 80386 descriptor tables are listed as follows:

 GLOBAL DESCRIPTOR TABLE ( GDT ) LOCAL DESCRIPTOR TABLE ( LDT ) INTERRUPT DESCRIPTOR TABLE ( IDT ) Descriptors:(1) The 80386 descriptors have a 20-bit segment limit and 32-bit segment address. The descriptor of 80386 are 8-byte quantities access right or attribute bits along with the base and limit of the segments. Descriptor Attribute Bits: (1) The A (accessed) attributed bit indicates whether the segment has been accessed by the CPU or not. The TYPE field decides the descriptor type and hence the segment type. The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor ( S=1). The DPL field specifies the descriptor privilege level. The D bit specifies the code segment operation size. If D=1, the segment is a 32-bit operand segment, else, it is a 16-bit operand segment. The P bit (present) signifies whether the segment is present in the physical memory or not. If P=1, the segment is present in the physical memory. The G (granularity) bit indicates whether the segment is page addressable. The zero bit must remain zero for compatibility with future process. The AVL (available) field specifies whether the descriptor is for user or for operating system. The 80386 has five types of descriptors listed as follows (2) 1.Code or Data Segment Descriptors. 2.System Descriptors. 3.Local descriptors. 4.TSS (Task State Segment) Descriptors. 5.GATE Descriptors. The 80386 provides a four level protection mechanism.(2)

Paging:

Paging Operation (1) Paging is one of the memory management techniques used for virtual memory multitasking operating system. The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages. The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program. The pages are just fixed size portions of the program module or data. The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time. Paging Unit: (1) The paging unit of 80386 uses a two level table mechanism to convert a linear address provided by segmentation unit into physical addresses. The paging unit converts the complete map of a task into pages, each of size 4K. The task is further handled in terms of its page, rather than segments. The paging unit handles every task in terms of three components namely page directory, page tables and page itself. Paging Descriptor Base Register (1) The control register CR2 is used to store the 32-bit linear address. The CR3 is used as page directory physical base address register, to store the physical starting address of the page directory. Page Directory: (1) This is at the most 4Kbytes in size. Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory. The upper 10 bits of the linear address are used as an index to the corresponding page directory entry. The page directory entries point to page tables. Page Tables: (1) Each page table is of 4Kbytes in size and many contain a maximum of 1024 entries. The page table entries contain the starting address of the page and the statistical information about the page. The P bit of the above entries indicate, if the entry can be used in address translation.If P=1, the entry can be used in address translation, otherwise it cannot be used.The P bit of the currently executed page is always high. The accessed bit A is set by 80386 before any access to the page. If A=1, the page is accessed, else unaccessed. The D bit (Dirty bit) is set before a write operation to the page is carried out. The Dbit is undefined for page director entries.

The OS reserved bits are defined by the operating system software. The User / Supervisor (U/S) bit and read/write bit are used to provide protectio n. These bits are decoded to provide protection under the 4 level protection model. The level 0 is supposed to have the highest privilege, while the level 3 is supposed to have the least privilege. This protection provide by the paging unit is transparen t to the segmentation unit.

Paging mechanism of 80386 (4)

15.a) Explain Microcontroller based Aluminum Smelter controller system Design.(16) ------------------------------Out of Portion ----------------------------15.b) Explain Microcontroller based Electronic Weighing Bridge System Design.(16) ------------------------------Out of Portion -----------------------------