02 Singlecycle

This Unit: Single-Cycle Datapaths
App App App
! Digital logic basics

! Focus on useful components
System software
CIS 371 Computer Organization and Design

Unit 2: Single-Cycle Datapath and Control
Mem
CPU
I/O
! Mapping an ISA to a datapath

! MIPS example
! Single-cycle control
CIS371 (Roth/Martin): Datapath and Control
Readings
! Digital logic
! P&H, Appendix C (on CD)
So You Have an ISA

! not useful without a piece of hardware to execute it
! Basic datapath
! P&H, Chapter 4.1 4.4 (well-written, relates to lecture well)
Implementing an ISA
datapath fetch
PC Insn memory Register File Data Memory
Two Types of Components

datapath fetch
control ! Datapath: performs computation (registers, ALUs, etc.)

! ISA specific: can implement every insn (single-cycle: in one pass!)
control ! Purely combinational: stateless computation

! ALUs, muxes, control ! Arbitrary Boolean functions
! Control: determines which computation is performed

! Routes data through datapath (which regs, which ALU op)
! Fetch: get insn, translate opcode into control ! Fetch ! Decode ! Execute cycle
CIS371 (Roth/Martin): Datapath and Control 5
! Combinational/sequential: storage
! PC, insn/data memories, register file ! Internally contain some combinational components
Building Blocks: Logic Gates

! Logic gates: implement Boolean functions
! Basic gates: NOT, NAND, NOR ! Underlying CMOS transistors are naturally inverting ( = NOT) NOT (INV)
A A A B
NAND
(AB) A B
NOR
(A+B)
! NAND, NOR are Boolean complete
Digital Logic Review
BUF
A A A B
AND
AB A B
OR
A+B
AND3
A B C A B
ANDNOT
AB A B
XOR
AB+AB (A^B)
Boolean Functions and Truth Tables

! Any Boolean function can be represented as a truth table
! Truth table: point-wise input ! output mapping ! Function is disjunction of all rows in which Out is 1 A,B,C 0,0,0 0,0,1 0,1,0 0,1,1 1,0,0 1,0,1 1,1,0 1,1,1 ! ! ! ! ! ! ! ! ! Out 0 0 0 0 0 1 1 1
Truth Tables and PLAs

! Implement Boolean function by implementing its truth table
! Takes two levels of logic ! Assumes inputs and inverses of inputs are available (usually are) ! First level: ANDs (product terms) ! Second level: ORs (sums of product terms)
! PLA (programmable logic array)

! Flexible circuit for doing this
! Example above: Out = ABC + ABC + ABC

CIS371 (Roth/Martin): Datapath and Control 9 CIS371 (Roth/Martin): Datapath and Control 10
PLA Example
! PLA with 3 inputs, 2 outputs, and 4 product terms
! Out0 = ABC + ABC + ABC A B C Programmable connections (unconnected) Out0 Out1
Boolean Algebra
! Boolean Algebra: rules for rewriting Boolean functions
! Useful for simplifying Boolean functions ! Simplifying = reducing gate count, reducing gate levels ! Rules: similar to logic (0/1 = F/T) ! Identity: A1 = A, A+0 = A ! 0/1: A0 = 0, A+1 = 1 ! Inverses: (A) = A ! Idempotency: AA = A, A+A = A ! Tautology: AA = 0, A+A = 1 ! Commutativity: AB = BA, A+B = B+A ! Associativity: A(BC) = (AB)C, A+(B+C) = (A+B)+C ! Distributivity: A(B+C) = AB+AC, A+(BC) = (A+B)(A+C) ! DeMorgans: (AB) = A+B, (A+B) = AB
Permanent connections
Logic Minimization
! Logic minimization
! Iterative application of rules to reduce function to simplest form ! There are tools for automatically doing this ! Example below: function from slide #8 Out Out Out Out Out Out Out Out Out = = = = = = = = = ABC + ABC + ABC A(BC + BC + BC) A(BC + (BC + BC)) A(BC + B(C+C)) A(BC + B1) A(BC + B) A((B+B)(C+B)) A(1(B+C)) A(B+C)
Non-Arbitrary Boolean Functions

! PLAs implement Boolean functions point-wise
! E.g., represent f(X) = X+5 as [0!5, 1!6, 2!7, 3!8, ] ! Mainly useful for arbitrary functions, no compact representation
! Many useful Boolean functions are not arbitrary

// distributivity // associativity // distributivity (on B) // tautology // 0/1 // distributivity (on +B) // tautology // 0/1
13
! Have a compact representation ! E.g., represent f(X) = X+5 as X+5 ! Examples ! Decoder ! Multiplexer ! Adder: e.g., X+5 (or more generally, X+Y)
14
Decoder
! Decoder: converts binary integer to 1-hot representation
! Binary representation of 02N1: N bits ! 1 hot representation of 02N1: 2N bits ! J represented as Jth bit 1, all other bits zero ! Example below: 2-to-4 decoder
B[0] B[1] 1H[0] 1H[1]
Multiplexer (Mux)
! Multiplexer (mux): selects output from N inputs
! Example: 1-bit 4-to-1 mux ! Not shown: N-bit 4-to-1 mux = N 1-bit 4-to-1 muxes + 1 decoder S (binary) S (1-hot) S (binary)
A A B C D
B
1H[2] 1H[3]
1H
B C D
15
16
Adder
! Adder: adds/subtracts two 2C binary integers
! ! ! ! Half adder: adds two 1-bit integers, no carry-in Full adder: adds three 1-bit integers, includes carry-in Ripple-carry adder: N chained full adders add 2 N-bit integers To subtract: negate B input, set bit 0 carry-in to 1
Full Adder
! What is the logic for a full adder?
! Look at truth table CI 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 ! ! ! ! ! ! ! ! ! C0 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 CI S
A B
CI A B FA S
CO CO
! S = CAB + CAB + CAB + CAB = C ^ A ^ B ! CO = CAB + CAB + CAB + CAB = CA + CB + AB

N-bit Adder/Subtracter
0 1 A0 B0 A1 B1 FA FA AN-1 BN-1 FA SN-1 S0 S1 A B
Sequential Logic & Synchronous Systems

Combinational Logic Clock Storage Element
! Processors are complex fine state machines (FSMs)

! Combinational (compute) blocks separated by storage elements ! State storage: memories, registers, etc.
+/-
! Synchronous systems
! Clock: global signal acts as write enable for all storage elements ! Typically marked as triangle ! All state elements write together, values move forward in lock-step +! Simplifies design: design combinational blocks independently
+/
! Aside: asynchronous systems

! Same thing, but no clock ! Values move forward using explicit handshaking ! May have some advantages, but difficult to design
19 CIS371 (Roth/Martin): Datapath and Control 20
+/ ! More later when we cover arithmetic

Datapath Storage Elements

datapath fetch
Cross-Coupled Inverters (CCIs)

! Cross-coupled inverters (CCIs)
! Primitive storage element for storing state ! Most storage arrays (regfile, caches) implemented this way ! Where is the input and where is the output?
control ! Three main types of storage elements

! Singleton registers: PC ! Register files: ISA registers ! Memories: insn/data memory
21
22
S-R Latch
! S-R (set-reset) latch
! Cross-coupled NOR gates ! Distinct inputs/outputs S,R 0,0 0,1 1,0 1,1 ! ! ! ! ! Q oldQ 0 1 0
D Latch
R Q S R S Q ! D latch: S-R latch + Q
! control that makes S=R=1 impossible E,D ! Q D 0,0 ! oldQ 0,1 ! oldQ 1,0 ! 0 1,1 ! 1 E ! In other words 0,D ! oldQ 1,D ! D ! In words ! When E is 1, Q gets D ! When E is 0, Q retains old value
23 CIS371 (Roth/Martin): Datapath and Control
SR
! S=0, R=0? circuit degenerates to cross-coupled INVs ! S=1, R=1? not very useful ! Not really used except as component in something else
D E
DL
24
Timing Diagrams
! Voltage {0,1} diagrams for different nodes in system
! Digitally stylized: changes are vertical lines (instantaneous?) ! Reality is analog, changes are continuous and smooth
Triggering: Level vs. Edge

E D Q
! Timing diagram for a D latch

E D Q
! The D-latch is level-triggered

! The latch is open for writing as long as E is 1 ! If D changes continuously, so does Q ! May not be the functionality we want
! Often easier to reason about an edge-triggered latch

! The latch is open for writing only on E transition (0 ! 1 or 1 ! 0) +! Dont need to worry about fluctuations in value of D
D Flip-Flop
! D Flip-Flop: also called master-slave flip-flop
! ! ! ! ! Sequential D-latches D Enabled by inverse signals First latch open when E = 0 E Second latch open when E = 1 Overall effect? ! D FF latches D on 0!1 transition ! E is the clock signal input E D Q
FFWE: FF with Separate Write Enable

! FFWE: FF with separate write enable
Q ! FF D(ata) input is MUX of D and Q, WE selects
DL
DL
D Q FF WE D Q FFWE WE
D E
FF
! Alternative: FF E(nable) input is AND of CLK and WE +! Fewer gates ! Creates timing problems !! Do not try to do logic on CLK in Verilog !! No, really.
Singleton Register
D0 FFWE N D N Q DN-1 FFWE WE D1 FFWE QN-1 Q1 Q0
Register File
RegDestVal Register File RegSource1Val RegSource2Val
WE
RD RS1 RS2
! Register file: M N-bit storage words

! Multiplexed input/output: data buses write/read random word
! Register: one N-bit storage word
WE ! Non-multiplexed input/output: data buses write/read same word ! FFs written on CLK edge if WE is 1 (or if there is no WE)
! Port: set of buses for accessing a random word in array

! Data bus (N-bits) + address bus (log2M-bits) + optional WE bit ! P ports = P parallel and independent accesses
! Implementation: FFWE array with shared write-enable (WE)

! MIPS integer register file

! 32 32-bit words, two read ports + one write port (why?)
Register File (Port) Implementation
Add a Read Port
RSrc1Val
RS1
! Register file with four registers
! Output of each register into 4to1 mux (RSrc1Val)

! RS1 is select input of RSrc1Val mux
31
32
Add Another Read Port
Add a Write Port

RDestVal RSrc2Val RSrc2Val
RSrc1Val
RSrc1Val
RS2 RS1
WE
RD
RS2 RS1
! Output of each register into another 4to1 mux (RSrc2Val)

! RS2 is select input of RSrc2Val mux
! Input RegDestVal into each register

! Enable only one registers WE: (Decoded RD) & (WE)
! What if we needed two write ports?

Another Useful Component: Memory

DATAIN ADDRESS WE Memory DATAOUT
! Register file: M N-bit storage words

! Few words (< 256), many ports, dedicated read and write ports ! Synchronous
! Memory: M N-bit storage words, yet not a register file

! Many words (> 1024), few ports (1, 2), shared read/write ports
MIPS Datapath & Control
! Leads to different implementation choices

! Lots of circuit tricks and such
35
36
Unified vs Split Memory Architecture

datapath fetch
PC Register File
Datapath for MIPS ISA

! Registers in MIPS are $0, $2 $31 ! Consider only the following instructions
add $1,$2,$3 $1 = $2 + $3 (add) addi $1,2,$3 $1 = 2 + $3 (add immed) lw $1,4($3) $1 = Memory[4+$3] (load) sw $1,4($3) Memory[4+$3] = $1 (store) beq $1,$2,PC_relative_target (branch equal) j absolute_target (unconditional jump)
control
Insn/Data Memory
! Unified architecture: unified insn/data memory

! LC3, MIPS, every other ISA
! Why only these?

! Most other instructions are the same from datapath viewpoint ! The ones that arent are left for you to figure out
37 CIS371 (Roth/Martin): Datapath and Control 38
! Harvard architecture: split insn/data memories

! LC4
Start With Fetch
First Instruction: add
+ 4
+ 4
P C
Insn Mem
P C
Insn Mem
Register File
s1 s2 d
! PC and instruction memory (Harvard architecture, for now) ! A +4 incrementer computes default next instruction PC
! Add register file and ALU

Second Instruction: addi
Third Instruction: lw
+ 4
+ 4
P C
Insn Mem
Register File
s1 s2 d
S X
P C
Insn Mem
Register File
s1 s2 d
S X
Data Mem d
! Destination register can now be either Rd or Rt ! Add sign extension unit and mux into second ALU input
! Add data memory, address is ALU output ! Add register write data mux to select memory output or ALU output
Fourth Instruction: sw
Fifth Instruction: beq

<< 2
+ 4
+ 4
P C
Insn Mem
Register File
s1 s2 d
S X
Data Mem d
P C
Insn Mem
Register File
s1 s2 d
S X
Data Mem d
! Add path from second input register to data memory data input
! Add left shift unit and adder to compute PC-relative branch target ! Add PC input mux to select PC+4 or branch target
Sixth Instruction: j
<< 2 << 2
Continuous Read Datapath Timing

+ 4
+ 4
P C
a
Insn Mem
Register File
s1 s2 d
S X
Data Mem d
P C
Insn Mem
Register File
s1 s2 d
S X
Data Mem d
Time
Read IMem
Read Registers
Read DMEM
Write DMEM Write Registers Write PC
! Add shifter to compute left shift of 26-bit immediate ! Add additional PC input mux for jump target
! Works because writes (PC, RegFile, DMem) are independent ! And because no read logically follows any write
What Is Control?
<< 2 << 2
Example: Control for add

BR JP
+ 4
<< 2 << 2
BR=0 JP=0
+ 4
P C
Insn Mem
Register File
s1 s2 d
Data Mem d
S X
Rwd
P C
Insn Mem
Register File
s1 s2 d
Data Mem d
S X
Rwd=0
Rwe Rdst
ALUop ALUinB
DMwe
Rwe=1 Rdst=1
ALUop=0 DMwe=0 ALUinB=0
! 9 signals control flow of data through this datapath

! MUX selectors, or register/memory write enable signals ! A real datapath has 300-500 control signals
Example: Control for sw

<< 2 << 2
Example: Control for beq

BR=0 JP=0
+ 4
<< 2 << 2
BR=1 JP=0
+ 4
P C
Insn Mem
Register File
s1 s2 d
Data Mem d
S X
Rwd=X
P C
Insn Mem
Register File
s1 s2 d
Data Mem d
S X
Rwd=X
Rwe=0 Rdst=X
Rwe=0 Rdst=X
! Difference between sw and add is 5 signals

! 3 if you dont count the X (dont care) signals
! Difference between sw and beq is only 4 signals
50
How Is Control Implemented?

<< 2 << 2
Implementing Control
BR JP
! Each instruction has a unique set of control signals

! Most are function of opcode ! Some may be encoded in the instruction itself ! E.g., the ALUop signal is some portion of the MIPS Func field +! Simplifies controller implementation ! Requires careful ISA design
+ 4
P C
Insn Mem
Register File
s1 s2 d
Data Mem d
S X
Rwd
Rwe Rdst
ALUop ALUinB Control?
DMwe
51
52
Control Implementation: ROM

! ROM (read only memory): like a RAM but unwritable
! ! ! ! Bits in data words are control signals Lines indexed by opcode Example: ROM control for 6-insn MIPS datapath X is dont care
Control Implementation: Logic

! Real machines have 100+ insns 300+ control signals
! 30,000+ control bits (~4KB) ! Not huge, but hard to make faster than datapath (important!)
! Alternative: logic gates or random logic (unstructured)

! Exploits the observation: many signals have few 1s or few 0s ! Example: random logic control for 6-insn MIPS datapath
Rwe 1 1 1 0 0 0 Rdst 0 1 1 X X X
53
BR add addi 0 0 0 0 1 0
JP 0 0 0 0 0 1
ALUinB 0 1 1 1 0 0
ALUop 0 0 0 0 1 0
DMwe 0 0 0 1 0 0
Rwd 0 0 X X X 1
sw beq j
opcode
opcode
lw
add addi lw sw beq j BR JP DMwe Rwe Rwd Rdst ALUop ALUinB

54
Datapath and Control Timing

+ 4
Single-Cycle Datapath Performance

<< 2
P C
Insn Mem
Register File
s1 s2 d
S X
Data Mem d P C
+ 4
Insn Mem
Register File
s1 s2 d
S X
Time
Control ROM/random logic
Data Mem d
Read IMem
Read Registers Read DMEM Write DMEM Write Registers (Read Control ROM) Write PC
55
! One instruction per cycle (1 IPC or 1 CPI) ! Clock cycle time proportional to worst-case logic delay
! In this datapath: insn fetch, decode, register read, ALU, data memory access, write register ! Can we do better?
Foreshadowing: Pipelined Datapath

PC + 4 A O B B
S X
Summary
App App App System software Mem CPU I/O
PC
<< 2
! Digital logic review ! Single-cycle datapath and control ! Next up:

! Arithmetic ! Performance & metrics
PC
Insn Mem
Register File
s1 s2 d
Data Mem d
IR
IR
IR
IR
! Split datapath into multiple stages

! Assembly line analogy ! 5 stages results in up to 5x clock & performance improvement

02 Singlecycle

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02 Singlecycle

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This Unit: Single-Cycle Datapaths

App App App

! Digital logic basics

CIS 371 Computer Organization and Design

! Mapping an ISA to a datapath

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

So You Have an ISA

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

Two Types of Components

control ! Datapath: performs computation (registers, ALUs, etc.)

control ! Purely combinational: stateless computation

! Control: determines which computation is performed

Building Blocks: Logic Gates

! NAND, NOR are Boolean complete

Digital Logic Review

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

Boolean Functions and Truth Tables

Truth Tables and PLAs

! PLA (programmable logic array)

! Example above: Out = ABC + ABC + ABC

Non-Arbitrary Boolean Functions

! Many useful Boolean functions are not arbitrary

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

! S = CAB + CAB + CAB + CAB = C ^ A ^ B ! CO = CAB + CAB + CAB + CAB = CA + CB + AB

Sequential Logic & Synchronous Systems

! Processors are complex fine state machines (FSMs)

! Aside: asynchronous systems

+/ ! More later when we cover arithmetic

Datapath Storage Elements

Cross-Coupled Inverters (CCIs)

control ! Three main types of storage elements

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

Triggering: Level vs. Edge

! Timing diagram for a D latch

! The D-latch is level-triggered

! Often easier to reason about an edge-triggered latch

FFWE: FF with Separate Write Enable

! Register file: M N-bit storage words

! Register: one N-bit storage word

! Port: set of buses for accessing a random word in array

! Implementation: FFWE array with shared write-enable (WE)

! MIPS integer register file

Register File (Port) Implementation

Add a Read Port

! Register file with four registers

! Output of each register into 4to1 mux (RSrc1Val)

CIS371 (Roth/Martin): Datapath and Control

CIS371 (Roth/Martin): Datapath and Control

Add Another Read Port

Add a Write Port

! Output of each register into another 4to1 mux (RSrc2Val)

! Input RegDestVal into each register

! What if we needed two write ports?

Another Useful Component: Memory

! Register file: M N-bit storage words

! Memory: M N-bit storage words, yet not a register file

MIPS Datapath & Control