Documente Academic
Documente Profesional
Documente Cultură
Data width 8 16 16 32
80486
Pentium Pentium II Pentium III Pentium 4
1989
1993
1.2 M
3.1M
20 -100 MHz
60-200 MHz 233-450 MHz 450 -933 MHz 1.5 GHz
32
32 /64 32/ 64 32 /64 32/ 64
Memory Interface
2
3
ES CS SS DS IP
Instruction Queue
4 5 6
BIU
AH BH CH
AL BL CL
ALU
DH
BP SP SI DI
DL
Operands Flags
8086 - Buses
A0 A19 D0
Add Bus
8086
D15
Data Bus
Control signals
1.1
Microprocessor
Fetches Instruction Executes Instruction
BIU EU
Address bus
BIU
ROM RAM
I/o Ports
Discs Video
Data Bus
ALU
CLK
Control & Timing
EU
X86 - ISA
8086-80486 Programmers Model BIU
Memory Addressing
Real
Access only 1 MB of Memory Only 20 Address Lines Required
Protected
CS DS ES SS FS GS
Code Segment
Data Segment
Extra Segment
Stack Segment
CS = 2000H IP = 3000H
Base address
Offset address
CS
2000H : 3000H
DS ES
SS
2000
0000
FFFF
Advantage of Segmentation
Relocation Program Specify only offset Program F0000H 10000H Program contents need not be change only Segment needs to change from F000H 0000H
58FFFH
Extra
49000H 43FFFH
Stack
4900 ES 3400 SS
Code
34000H 2FFFFH
20000H 1FFFFH
10000H 00000H
2000 CS
Data
1000
DS
High Memory
HIMEM.SYS A20 Segment Address FFFFH Offset Address 4000H 103FF0H 03FF0H
X86 - ISA
Programmers Model
AX BX
Accumulator
Base Index Count Data Stack Pointer Base Pointer Source Index Destination Index
CX
DX SP
BP
SI DI
Registers
MULTIPURPOSE REGISTERS
AX, BX, CX, DX, BP, DI, SI
Registers - MPR
AH (8 bit) (Accumulator) AX BH BX (Base Register) CH CX (Used as a counter) DX DH AL (8 bit) BL CL DL
Programmers Model-MPR
EAX AH AL
BH CH DH
BP SI DI SP
BL CL DL
ES
Flags
Status Control
Flag Register
A V R C M F N IOPL O D I T S Z T A P C
80x86-Summary
BIU (Bus Interface Unit) provides hardware funcns for generation of the memory and I/O addresses for the transfer of data between itself and the outside world
EU (Execution Unit) receives program instruction codes and data from the BIU executes these instructions and stores the results in the general- purpose registers